| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 2 | |* *| |
| 3 | |* Target Register Enum Values *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | |
| 10 | #ifdef GET_REGINFO_ENUM |
| 11 | #undef GET_REGINFO_ENUM |
| 12 | |
| 13 | namespace llvm { |
| 14 | |
| 15 | class MCRegisterClass; |
| 16 | extern const MCRegisterClass AArch64MCRegisterClasses[]; |
| 17 | |
| 18 | namespace AArch64 { |
| 19 | enum { |
| 20 | NoRegister, |
| 21 | FFR = 1, |
| 22 | FP = 2, |
| 23 | LR = 3, |
| 24 | NZCV = 4, |
| 25 | SP = 5, |
| 26 | VG = 6, |
| 27 | WSP = 7, |
| 28 | WZR = 8, |
| 29 | XZR = 9, |
| 30 | B0 = 10, |
| 31 | B1 = 11, |
| 32 | B2 = 12, |
| 33 | B3 = 13, |
| 34 | B4 = 14, |
| 35 | B5 = 15, |
| 36 | B6 = 16, |
| 37 | B7 = 17, |
| 38 | B8 = 18, |
| 39 | B9 = 19, |
| 40 | B10 = 20, |
| 41 | B11 = 21, |
| 42 | B12 = 22, |
| 43 | B13 = 23, |
| 44 | B14 = 24, |
| 45 | B15 = 25, |
| 46 | B16 = 26, |
| 47 | B17 = 27, |
| 48 | B18 = 28, |
| 49 | B19 = 29, |
| 50 | B20 = 30, |
| 51 | B21 = 31, |
| 52 | B22 = 32, |
| 53 | B23 = 33, |
| 54 | B24 = 34, |
| 55 | B25 = 35, |
| 56 | B26 = 36, |
| 57 | B27 = 37, |
| 58 | B28 = 38, |
| 59 | B29 = 39, |
| 60 | B30 = 40, |
| 61 | B31 = 41, |
| 62 | D0 = 42, |
| 63 | D1 = 43, |
| 64 | D2 = 44, |
| 65 | D3 = 45, |
| 66 | D4 = 46, |
| 67 | D5 = 47, |
| 68 | D6 = 48, |
| 69 | D7 = 49, |
| 70 | D8 = 50, |
| 71 | D9 = 51, |
| 72 | D10 = 52, |
| 73 | D11 = 53, |
| 74 | D12 = 54, |
| 75 | D13 = 55, |
| 76 | D14 = 56, |
| 77 | D15 = 57, |
| 78 | D16 = 58, |
| 79 | D17 = 59, |
| 80 | D18 = 60, |
| 81 | D19 = 61, |
| 82 | D20 = 62, |
| 83 | D21 = 63, |
| 84 | D22 = 64, |
| 85 | D23 = 65, |
| 86 | D24 = 66, |
| 87 | D25 = 67, |
| 88 | D26 = 68, |
| 89 | D27 = 69, |
| 90 | D28 = 70, |
| 91 | D29 = 71, |
| 92 | D30 = 72, |
| 93 | D31 = 73, |
| 94 | H0 = 74, |
| 95 | H1 = 75, |
| 96 | H2 = 76, |
| 97 | H3 = 77, |
| 98 | H4 = 78, |
| 99 | H5 = 79, |
| 100 | H6 = 80, |
| 101 | H7 = 81, |
| 102 | H8 = 82, |
| 103 | H9 = 83, |
| 104 | H10 = 84, |
| 105 | H11 = 85, |
| 106 | H12 = 86, |
| 107 | H13 = 87, |
| 108 | H14 = 88, |
| 109 | H15 = 89, |
| 110 | H16 = 90, |
| 111 | H17 = 91, |
| 112 | H18 = 92, |
| 113 | H19 = 93, |
| 114 | H20 = 94, |
| 115 | H21 = 95, |
| 116 | H22 = 96, |
| 117 | H23 = 97, |
| 118 | H24 = 98, |
| 119 | H25 = 99, |
| 120 | H26 = 100, |
| 121 | H27 = 101, |
| 122 | H28 = 102, |
| 123 | H29 = 103, |
| 124 | H30 = 104, |
| 125 | H31 = 105, |
| 126 | P0 = 106, |
| 127 | P1 = 107, |
| 128 | P2 = 108, |
| 129 | P3 = 109, |
| 130 | P4 = 110, |
| 131 | P5 = 111, |
| 132 | P6 = 112, |
| 133 | P7 = 113, |
| 134 | P8 = 114, |
| 135 | P9 = 115, |
| 136 | P10 = 116, |
| 137 | P11 = 117, |
| 138 | P12 = 118, |
| 139 | P13 = 119, |
| 140 | P14 = 120, |
| 141 | P15 = 121, |
| 142 | Q0 = 122, |
| 143 | Q1 = 123, |
| 144 | Q2 = 124, |
| 145 | Q3 = 125, |
| 146 | Q4 = 126, |
| 147 | Q5 = 127, |
| 148 | Q6 = 128, |
| 149 | Q7 = 129, |
| 150 | Q8 = 130, |
| 151 | Q9 = 131, |
| 152 | Q10 = 132, |
| 153 | Q11 = 133, |
| 154 | Q12 = 134, |
| 155 | Q13 = 135, |
| 156 | Q14 = 136, |
| 157 | Q15 = 137, |
| 158 | Q16 = 138, |
| 159 | Q17 = 139, |
| 160 | Q18 = 140, |
| 161 | Q19 = 141, |
| 162 | Q20 = 142, |
| 163 | Q21 = 143, |
| 164 | Q22 = 144, |
| 165 | Q23 = 145, |
| 166 | Q24 = 146, |
| 167 | Q25 = 147, |
| 168 | Q26 = 148, |
| 169 | Q27 = 149, |
| 170 | Q28 = 150, |
| 171 | Q29 = 151, |
| 172 | Q30 = 152, |
| 173 | Q31 = 153, |
| 174 | S0 = 154, |
| 175 | S1 = 155, |
| 176 | S2 = 156, |
| 177 | S3 = 157, |
| 178 | S4 = 158, |
| 179 | S5 = 159, |
| 180 | S6 = 160, |
| 181 | S7 = 161, |
| 182 | S8 = 162, |
| 183 | S9 = 163, |
| 184 | S10 = 164, |
| 185 | S11 = 165, |
| 186 | S12 = 166, |
| 187 | S13 = 167, |
| 188 | S14 = 168, |
| 189 | S15 = 169, |
| 190 | S16 = 170, |
| 191 | S17 = 171, |
| 192 | S18 = 172, |
| 193 | S19 = 173, |
| 194 | S20 = 174, |
| 195 | S21 = 175, |
| 196 | S22 = 176, |
| 197 | S23 = 177, |
| 198 | S24 = 178, |
| 199 | S25 = 179, |
| 200 | S26 = 180, |
| 201 | S27 = 181, |
| 202 | S28 = 182, |
| 203 | S29 = 183, |
| 204 | S30 = 184, |
| 205 | S31 = 185, |
| 206 | W0 = 186, |
| 207 | W1 = 187, |
| 208 | W2 = 188, |
| 209 | W3 = 189, |
| 210 | W4 = 190, |
| 211 | W5 = 191, |
| 212 | W6 = 192, |
| 213 | W7 = 193, |
| 214 | W8 = 194, |
| 215 | W9 = 195, |
| 216 | W10 = 196, |
| 217 | W11 = 197, |
| 218 | W12 = 198, |
| 219 | W13 = 199, |
| 220 | W14 = 200, |
| 221 | W15 = 201, |
| 222 | W16 = 202, |
| 223 | W17 = 203, |
| 224 | W18 = 204, |
| 225 | W19 = 205, |
| 226 | W20 = 206, |
| 227 | W21 = 207, |
| 228 | W22 = 208, |
| 229 | W23 = 209, |
| 230 | W24 = 210, |
| 231 | W25 = 211, |
| 232 | W26 = 212, |
| 233 | W27 = 213, |
| 234 | W28 = 214, |
| 235 | W29 = 215, |
| 236 | W30 = 216, |
| 237 | X0 = 217, |
| 238 | X1 = 218, |
| 239 | X2 = 219, |
| 240 | X3 = 220, |
| 241 | X4 = 221, |
| 242 | X5 = 222, |
| 243 | X6 = 223, |
| 244 | X7 = 224, |
| 245 | X8 = 225, |
| 246 | X9 = 226, |
| 247 | X10 = 227, |
| 248 | X11 = 228, |
| 249 | X12 = 229, |
| 250 | X13 = 230, |
| 251 | X14 = 231, |
| 252 | X15 = 232, |
| 253 | X16 = 233, |
| 254 | X17 = 234, |
| 255 | X18 = 235, |
| 256 | X19 = 236, |
| 257 | X20 = 237, |
| 258 | X21 = 238, |
| 259 | X22 = 239, |
| 260 | X23 = 240, |
| 261 | X24 = 241, |
| 262 | X25 = 242, |
| 263 | X26 = 243, |
| 264 | X27 = 244, |
| 265 | X28 = 245, |
| 266 | Z0 = 246, |
| 267 | Z1 = 247, |
| 268 | Z2 = 248, |
| 269 | Z3 = 249, |
| 270 | Z4 = 250, |
| 271 | Z5 = 251, |
| 272 | Z6 = 252, |
| 273 | Z7 = 253, |
| 274 | Z8 = 254, |
| 275 | Z9 = 255, |
| 276 | Z10 = 256, |
| 277 | Z11 = 257, |
| 278 | Z12 = 258, |
| 279 | Z13 = 259, |
| 280 | Z14 = 260, |
| 281 | Z15 = 261, |
| 282 | Z16 = 262, |
| 283 | Z17 = 263, |
| 284 | Z18 = 264, |
| 285 | Z19 = 265, |
| 286 | Z20 = 266, |
| 287 | Z21 = 267, |
| 288 | Z22 = 268, |
| 289 | Z23 = 269, |
| 290 | Z24 = 270, |
| 291 | Z25 = 271, |
| 292 | Z26 = 272, |
| 293 | Z27 = 273, |
| 294 | Z28 = 274, |
| 295 | Z29 = 275, |
| 296 | Z30 = 276, |
| 297 | Z31 = 277, |
| 298 | Z0_HI = 278, |
| 299 | Z1_HI = 279, |
| 300 | Z2_HI = 280, |
| 301 | Z3_HI = 281, |
| 302 | Z4_HI = 282, |
| 303 | Z5_HI = 283, |
| 304 | Z6_HI = 284, |
| 305 | Z7_HI = 285, |
| 306 | Z8_HI = 286, |
| 307 | Z9_HI = 287, |
| 308 | Z10_HI = 288, |
| 309 | Z11_HI = 289, |
| 310 | Z12_HI = 290, |
| 311 | Z13_HI = 291, |
| 312 | Z14_HI = 292, |
| 313 | Z15_HI = 293, |
| 314 | Z16_HI = 294, |
| 315 | Z17_HI = 295, |
| 316 | Z18_HI = 296, |
| 317 | Z19_HI = 297, |
| 318 | Z20_HI = 298, |
| 319 | Z21_HI = 299, |
| 320 | Z22_HI = 300, |
| 321 | Z23_HI = 301, |
| 322 | Z24_HI = 302, |
| 323 | Z25_HI = 303, |
| 324 | Z26_HI = 304, |
| 325 | Z27_HI = 305, |
| 326 | Z28_HI = 306, |
| 327 | Z29_HI = 307, |
| 328 | Z30_HI = 308, |
| 329 | Z31_HI = 309, |
| 330 | D0_D1 = 310, |
| 331 | D1_D2 = 311, |
| 332 | D2_D3 = 312, |
| 333 | D3_D4 = 313, |
| 334 | D4_D5 = 314, |
| 335 | D5_D6 = 315, |
| 336 | D6_D7 = 316, |
| 337 | D7_D8 = 317, |
| 338 | D8_D9 = 318, |
| 339 | D9_D10 = 319, |
| 340 | D10_D11 = 320, |
| 341 | D11_D12 = 321, |
| 342 | D12_D13 = 322, |
| 343 | D13_D14 = 323, |
| 344 | D14_D15 = 324, |
| 345 | D15_D16 = 325, |
| 346 | D16_D17 = 326, |
| 347 | D17_D18 = 327, |
| 348 | D18_D19 = 328, |
| 349 | D19_D20 = 329, |
| 350 | D20_D21 = 330, |
| 351 | D21_D22 = 331, |
| 352 | D22_D23 = 332, |
| 353 | D23_D24 = 333, |
| 354 | D24_D25 = 334, |
| 355 | D25_D26 = 335, |
| 356 | D26_D27 = 336, |
| 357 | D27_D28 = 337, |
| 358 | D28_D29 = 338, |
| 359 | D29_D30 = 339, |
| 360 | D30_D31 = 340, |
| 361 | D31_D0 = 341, |
| 362 | D0_D1_D2_D3 = 342, |
| 363 | D1_D2_D3_D4 = 343, |
| 364 | D2_D3_D4_D5 = 344, |
| 365 | D3_D4_D5_D6 = 345, |
| 366 | D4_D5_D6_D7 = 346, |
| 367 | D5_D6_D7_D8 = 347, |
| 368 | D6_D7_D8_D9 = 348, |
| 369 | D7_D8_D9_D10 = 349, |
| 370 | D8_D9_D10_D11 = 350, |
| 371 | D9_D10_D11_D12 = 351, |
| 372 | D10_D11_D12_D13 = 352, |
| 373 | D11_D12_D13_D14 = 353, |
| 374 | D12_D13_D14_D15 = 354, |
| 375 | D13_D14_D15_D16 = 355, |
| 376 | D14_D15_D16_D17 = 356, |
| 377 | D15_D16_D17_D18 = 357, |
| 378 | D16_D17_D18_D19 = 358, |
| 379 | D17_D18_D19_D20 = 359, |
| 380 | D18_D19_D20_D21 = 360, |
| 381 | D19_D20_D21_D22 = 361, |
| 382 | D20_D21_D22_D23 = 362, |
| 383 | D21_D22_D23_D24 = 363, |
| 384 | D22_D23_D24_D25 = 364, |
| 385 | D23_D24_D25_D26 = 365, |
| 386 | D24_D25_D26_D27 = 366, |
| 387 | D25_D26_D27_D28 = 367, |
| 388 | D26_D27_D28_D29 = 368, |
| 389 | D27_D28_D29_D30 = 369, |
| 390 | D28_D29_D30_D31 = 370, |
| 391 | D29_D30_D31_D0 = 371, |
| 392 | D30_D31_D0_D1 = 372, |
| 393 | D31_D0_D1_D2 = 373, |
| 394 | D0_D1_D2 = 374, |
| 395 | D1_D2_D3 = 375, |
| 396 | D2_D3_D4 = 376, |
| 397 | D3_D4_D5 = 377, |
| 398 | D4_D5_D6 = 378, |
| 399 | D5_D6_D7 = 379, |
| 400 | D6_D7_D8 = 380, |
| 401 | D7_D8_D9 = 381, |
| 402 | D8_D9_D10 = 382, |
| 403 | D9_D10_D11 = 383, |
| 404 | D10_D11_D12 = 384, |
| 405 | D11_D12_D13 = 385, |
| 406 | D12_D13_D14 = 386, |
| 407 | D13_D14_D15 = 387, |
| 408 | D14_D15_D16 = 388, |
| 409 | D15_D16_D17 = 389, |
| 410 | D16_D17_D18 = 390, |
| 411 | D17_D18_D19 = 391, |
| 412 | D18_D19_D20 = 392, |
| 413 | D19_D20_D21 = 393, |
| 414 | D20_D21_D22 = 394, |
| 415 | D21_D22_D23 = 395, |
| 416 | D22_D23_D24 = 396, |
| 417 | D23_D24_D25 = 397, |
| 418 | D24_D25_D26 = 398, |
| 419 | D25_D26_D27 = 399, |
| 420 | D26_D27_D28 = 400, |
| 421 | D27_D28_D29 = 401, |
| 422 | D28_D29_D30 = 402, |
| 423 | D29_D30_D31 = 403, |
| 424 | D30_D31_D0 = 404, |
| 425 | D31_D0_D1 = 405, |
| 426 | Q0_Q1 = 406, |
| 427 | Q1_Q2 = 407, |
| 428 | Q2_Q3 = 408, |
| 429 | Q3_Q4 = 409, |
| 430 | Q4_Q5 = 410, |
| 431 | Q5_Q6 = 411, |
| 432 | Q6_Q7 = 412, |
| 433 | Q7_Q8 = 413, |
| 434 | Q8_Q9 = 414, |
| 435 | Q9_Q10 = 415, |
| 436 | Q10_Q11 = 416, |
| 437 | Q11_Q12 = 417, |
| 438 | Q12_Q13 = 418, |
| 439 | Q13_Q14 = 419, |
| 440 | Q14_Q15 = 420, |
| 441 | Q15_Q16 = 421, |
| 442 | Q16_Q17 = 422, |
| 443 | Q17_Q18 = 423, |
| 444 | Q18_Q19 = 424, |
| 445 | Q19_Q20 = 425, |
| 446 | Q20_Q21 = 426, |
| 447 | Q21_Q22 = 427, |
| 448 | Q22_Q23 = 428, |
| 449 | Q23_Q24 = 429, |
| 450 | Q24_Q25 = 430, |
| 451 | Q25_Q26 = 431, |
| 452 | Q26_Q27 = 432, |
| 453 | Q27_Q28 = 433, |
| 454 | Q28_Q29 = 434, |
| 455 | Q29_Q30 = 435, |
| 456 | Q30_Q31 = 436, |
| 457 | Q31_Q0 = 437, |
| 458 | Q0_Q1_Q2_Q3 = 438, |
| 459 | Q1_Q2_Q3_Q4 = 439, |
| 460 | Q2_Q3_Q4_Q5 = 440, |
| 461 | Q3_Q4_Q5_Q6 = 441, |
| 462 | Q4_Q5_Q6_Q7 = 442, |
| 463 | Q5_Q6_Q7_Q8 = 443, |
| 464 | Q6_Q7_Q8_Q9 = 444, |
| 465 | Q7_Q8_Q9_Q10 = 445, |
| 466 | Q8_Q9_Q10_Q11 = 446, |
| 467 | Q9_Q10_Q11_Q12 = 447, |
| 468 | Q10_Q11_Q12_Q13 = 448, |
| 469 | Q11_Q12_Q13_Q14 = 449, |
| 470 | Q12_Q13_Q14_Q15 = 450, |
| 471 | Q13_Q14_Q15_Q16 = 451, |
| 472 | Q14_Q15_Q16_Q17 = 452, |
| 473 | Q15_Q16_Q17_Q18 = 453, |
| 474 | Q16_Q17_Q18_Q19 = 454, |
| 475 | Q17_Q18_Q19_Q20 = 455, |
| 476 | Q18_Q19_Q20_Q21 = 456, |
| 477 | Q19_Q20_Q21_Q22 = 457, |
| 478 | Q20_Q21_Q22_Q23 = 458, |
| 479 | Q21_Q22_Q23_Q24 = 459, |
| 480 | Q22_Q23_Q24_Q25 = 460, |
| 481 | Q23_Q24_Q25_Q26 = 461, |
| 482 | Q24_Q25_Q26_Q27 = 462, |
| 483 | Q25_Q26_Q27_Q28 = 463, |
| 484 | Q26_Q27_Q28_Q29 = 464, |
| 485 | Q27_Q28_Q29_Q30 = 465, |
| 486 | Q28_Q29_Q30_Q31 = 466, |
| 487 | Q29_Q30_Q31_Q0 = 467, |
| 488 | Q30_Q31_Q0_Q1 = 468, |
| 489 | Q31_Q0_Q1_Q2 = 469, |
| 490 | Q0_Q1_Q2 = 470, |
| 491 | Q1_Q2_Q3 = 471, |
| 492 | Q2_Q3_Q4 = 472, |
| 493 | Q3_Q4_Q5 = 473, |
| 494 | Q4_Q5_Q6 = 474, |
| 495 | Q5_Q6_Q7 = 475, |
| 496 | Q6_Q7_Q8 = 476, |
| 497 | Q7_Q8_Q9 = 477, |
| 498 | Q8_Q9_Q10 = 478, |
| 499 | Q9_Q10_Q11 = 479, |
| 500 | Q10_Q11_Q12 = 480, |
| 501 | Q11_Q12_Q13 = 481, |
| 502 | Q12_Q13_Q14 = 482, |
| 503 | Q13_Q14_Q15 = 483, |
| 504 | Q14_Q15_Q16 = 484, |
| 505 | Q15_Q16_Q17 = 485, |
| 506 | Q16_Q17_Q18 = 486, |
| 507 | Q17_Q18_Q19 = 487, |
| 508 | Q18_Q19_Q20 = 488, |
| 509 | Q19_Q20_Q21 = 489, |
| 510 | Q20_Q21_Q22 = 490, |
| 511 | Q21_Q22_Q23 = 491, |
| 512 | Q22_Q23_Q24 = 492, |
| 513 | Q23_Q24_Q25 = 493, |
| 514 | Q24_Q25_Q26 = 494, |
| 515 | Q25_Q26_Q27 = 495, |
| 516 | Q26_Q27_Q28 = 496, |
| 517 | Q27_Q28_Q29 = 497, |
| 518 | Q28_Q29_Q30 = 498, |
| 519 | Q29_Q30_Q31 = 499, |
| 520 | Q30_Q31_Q0 = 500, |
| 521 | Q31_Q0_Q1 = 501, |
| 522 | X22_X23_X24_X25_X26_X27_X28_FP = 502, |
| 523 | X0_X1_X2_X3_X4_X5_X6_X7 = 503, |
| 524 | X2_X3_X4_X5_X6_X7_X8_X9 = 504, |
| 525 | X4_X5_X6_X7_X8_X9_X10_X11 = 505, |
| 526 | X6_X7_X8_X9_X10_X11_X12_X13 = 506, |
| 527 | X8_X9_X10_X11_X12_X13_X14_X15 = 507, |
| 528 | X10_X11_X12_X13_X14_X15_X16_X17 = 508, |
| 529 | X12_X13_X14_X15_X16_X17_X18_X19 = 509, |
| 530 | X14_X15_X16_X17_X18_X19_X20_X21 = 510, |
| 531 | X16_X17_X18_X19_X20_X21_X22_X23 = 511, |
| 532 | X18_X19_X20_X21_X22_X23_X24_X25 = 512, |
| 533 | X20_X21_X22_X23_X24_X25_X26_X27 = 513, |
| 534 | W30_WZR = 514, |
| 535 | W0_W1 = 515, |
| 536 | W2_W3 = 516, |
| 537 | W4_W5 = 517, |
| 538 | W6_W7 = 518, |
| 539 | W8_W9 = 519, |
| 540 | W10_W11 = 520, |
| 541 | W12_W13 = 521, |
| 542 | W14_W15 = 522, |
| 543 | W16_W17 = 523, |
| 544 | W18_W19 = 524, |
| 545 | W20_W21 = 525, |
| 546 | W22_W23 = 526, |
| 547 | W24_W25 = 527, |
| 548 | W26_W27 = 528, |
| 549 | W28_W29 = 529, |
| 550 | LR_XZR = 530, |
| 551 | X28_FP = 531, |
| 552 | X0_X1 = 532, |
| 553 | X2_X3 = 533, |
| 554 | X4_X5 = 534, |
| 555 | X6_X7 = 535, |
| 556 | X8_X9 = 536, |
| 557 | X10_X11 = 537, |
| 558 | X12_X13 = 538, |
| 559 | X14_X15 = 539, |
| 560 | X16_X17 = 540, |
| 561 | X18_X19 = 541, |
| 562 | X20_X21 = 542, |
| 563 | X22_X23 = 543, |
| 564 | X24_X25 = 544, |
| 565 | X26_X27 = 545, |
| 566 | Z0_Z1 = 546, |
| 567 | Z1_Z2 = 547, |
| 568 | Z2_Z3 = 548, |
| 569 | Z3_Z4 = 549, |
| 570 | Z4_Z5 = 550, |
| 571 | Z5_Z6 = 551, |
| 572 | Z6_Z7 = 552, |
| 573 | Z7_Z8 = 553, |
| 574 | Z8_Z9 = 554, |
| 575 | Z9_Z10 = 555, |
| 576 | Z10_Z11 = 556, |
| 577 | Z11_Z12 = 557, |
| 578 | Z12_Z13 = 558, |
| 579 | Z13_Z14 = 559, |
| 580 | Z14_Z15 = 560, |
| 581 | Z15_Z16 = 561, |
| 582 | Z16_Z17 = 562, |
| 583 | Z17_Z18 = 563, |
| 584 | Z18_Z19 = 564, |
| 585 | Z19_Z20 = 565, |
| 586 | Z20_Z21 = 566, |
| 587 | Z21_Z22 = 567, |
| 588 | Z22_Z23 = 568, |
| 589 | Z23_Z24 = 569, |
| 590 | Z24_Z25 = 570, |
| 591 | Z25_Z26 = 571, |
| 592 | Z26_Z27 = 572, |
| 593 | Z27_Z28 = 573, |
| 594 | Z28_Z29 = 574, |
| 595 | Z29_Z30 = 575, |
| 596 | Z30_Z31 = 576, |
| 597 | Z31_Z0 = 577, |
| 598 | Z0_Z1_Z2_Z3 = 578, |
| 599 | Z1_Z2_Z3_Z4 = 579, |
| 600 | Z2_Z3_Z4_Z5 = 580, |
| 601 | Z3_Z4_Z5_Z6 = 581, |
| 602 | Z4_Z5_Z6_Z7 = 582, |
| 603 | Z5_Z6_Z7_Z8 = 583, |
| 604 | Z6_Z7_Z8_Z9 = 584, |
| 605 | Z7_Z8_Z9_Z10 = 585, |
| 606 | Z8_Z9_Z10_Z11 = 586, |
| 607 | Z9_Z10_Z11_Z12 = 587, |
| 608 | Z10_Z11_Z12_Z13 = 588, |
| 609 | Z11_Z12_Z13_Z14 = 589, |
| 610 | Z12_Z13_Z14_Z15 = 590, |
| 611 | Z13_Z14_Z15_Z16 = 591, |
| 612 | Z14_Z15_Z16_Z17 = 592, |
| 613 | Z15_Z16_Z17_Z18 = 593, |
| 614 | Z16_Z17_Z18_Z19 = 594, |
| 615 | Z17_Z18_Z19_Z20 = 595, |
| 616 | Z18_Z19_Z20_Z21 = 596, |
| 617 | Z19_Z20_Z21_Z22 = 597, |
| 618 | Z20_Z21_Z22_Z23 = 598, |
| 619 | Z21_Z22_Z23_Z24 = 599, |
| 620 | Z22_Z23_Z24_Z25 = 600, |
| 621 | Z23_Z24_Z25_Z26 = 601, |
| 622 | Z24_Z25_Z26_Z27 = 602, |
| 623 | Z25_Z26_Z27_Z28 = 603, |
| 624 | Z26_Z27_Z28_Z29 = 604, |
| 625 | Z27_Z28_Z29_Z30 = 605, |
| 626 | Z28_Z29_Z30_Z31 = 606, |
| 627 | Z29_Z30_Z31_Z0 = 607, |
| 628 | Z30_Z31_Z0_Z1 = 608, |
| 629 | Z31_Z0_Z1_Z2 = 609, |
| 630 | Z0_Z1_Z2 = 610, |
| 631 | Z1_Z2_Z3 = 611, |
| 632 | Z2_Z3_Z4 = 612, |
| 633 | Z3_Z4_Z5 = 613, |
| 634 | Z4_Z5_Z6 = 614, |
| 635 | Z5_Z6_Z7 = 615, |
| 636 | Z6_Z7_Z8 = 616, |
| 637 | Z7_Z8_Z9 = 617, |
| 638 | Z8_Z9_Z10 = 618, |
| 639 | Z9_Z10_Z11 = 619, |
| 640 | Z10_Z11_Z12 = 620, |
| 641 | Z11_Z12_Z13 = 621, |
| 642 | Z12_Z13_Z14 = 622, |
| 643 | Z13_Z14_Z15 = 623, |
| 644 | Z14_Z15_Z16 = 624, |
| 645 | Z15_Z16_Z17 = 625, |
| 646 | Z16_Z17_Z18 = 626, |
| 647 | Z17_Z18_Z19 = 627, |
| 648 | Z18_Z19_Z20 = 628, |
| 649 | Z19_Z20_Z21 = 629, |
| 650 | Z20_Z21_Z22 = 630, |
| 651 | Z21_Z22_Z23 = 631, |
| 652 | Z22_Z23_Z24 = 632, |
| 653 | Z23_Z24_Z25 = 633, |
| 654 | Z24_Z25_Z26 = 634, |
| 655 | Z25_Z26_Z27 = 635, |
| 656 | Z26_Z27_Z28 = 636, |
| 657 | Z27_Z28_Z29 = 637, |
| 658 | Z28_Z29_Z30 = 638, |
| 659 | Z29_Z30_Z31 = 639, |
| 660 | Z30_Z31_Z0 = 640, |
| 661 | Z31_Z0_Z1 = 641, |
| 662 | NUM_TARGET_REGS // 642 |
| 663 | }; |
| 664 | } // end namespace AArch64 |
| 665 | |
| 666 | // Register classes |
| 667 | |
| 668 | namespace AArch64 { |
| 669 | enum { |
| 670 | FPR8RegClassID = 0, |
| 671 | FPR16RegClassID = 1, |
| 672 | FPR16_loRegClassID = 2, |
| 673 | PPRRegClassID = 3, |
| 674 | PPR_3bRegClassID = 4, |
| 675 | GPR32allRegClassID = 5, |
| 676 | FPR32RegClassID = 6, |
| 677 | GPR32RegClassID = 7, |
| 678 | GPR32spRegClassID = 8, |
| 679 | GPR32commonRegClassID = 9, |
| 680 | FPR32_with_hsub_in_FPR16_loRegClassID = 10, |
| 681 | GPR32argRegClassID = 11, |
| 682 | CCRRegClassID = 12, |
| 683 | GPR32sponlyRegClassID = 13, |
| 684 | WSeqPairsClassRegClassID = 14, |
| 685 | WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 15, |
| 686 | WSeqPairsClass_with_sube32_in_GPR32argRegClassID = 16, |
| 687 | GPR64allRegClassID = 17, |
| 688 | FPR64RegClassID = 18, |
| 689 | GPR64RegClassID = 19, |
| 690 | GPR64spRegClassID = 20, |
| 691 | GPR64commonRegClassID = 21, |
| 692 | GPR64noipRegClassID = 22, |
| 693 | GPR64common_and_GPR64noipRegClassID = 23, |
| 694 | tcGPR64RegClassID = 24, |
| 695 | GPR64noip_and_tcGPR64RegClassID = 25, |
| 696 | FPR64_loRegClassID = 26, |
| 697 | GPR64x8ClassRegClassID = 27, |
| 698 | GPR64x8Class_with_x8sub_0_in_GPR64noipRegClassID = 28, |
| 699 | GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID = 29, |
| 700 | GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 30, |
| 701 | GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 31, |
| 702 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID = 32, |
| 703 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 33, |
| 704 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 34, |
| 705 | GPR64x8Class_with_x8sub_0_in_tcGPR64RegClassID = 35, |
| 706 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 36, |
| 707 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 37, |
| 708 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 38, |
| 709 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClassID = 39, |
| 710 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID = 40, |
| 711 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 41, |
| 712 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 42, |
| 713 | GPR64x8Class_with_x8sub_1_in_tcGPR64RegClassID = 43, |
| 714 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 44, |
| 715 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 45, |
| 716 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 46, |
| 717 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 47, |
| 718 | GPR64argRegClassID = 48, |
| 719 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID = 49, |
| 720 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 50, |
| 721 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 51, |
| 722 | GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClassID = 52, |
| 723 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 53, |
| 724 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 54, |
| 725 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 55, |
| 726 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 56, |
| 727 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClassID = 57, |
| 728 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 58, |
| 729 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 59, |
| 730 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 60, |
| 731 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 61, |
| 732 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 62, |
| 733 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID = 63, |
| 734 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 64, |
| 735 | GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClassID = 65, |
| 736 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 66, |
| 737 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 67, |
| 738 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 68, |
| 739 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClassID = 69, |
| 740 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 70, |
| 741 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 71, |
| 742 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID = 72, |
| 743 | GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClassID = 73, |
| 744 | GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClassID = 74, |
| 745 | GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClassID = 75, |
| 746 | GPR64x8Class_with_sub_32_in_GPR32argRegClassID = 76, |
| 747 | GPR64x8Class_with_x8sub_2_in_GPR64argRegClassID = 77, |
| 748 | GPR64x8Class_with_x8sub_4_in_GPR64argRegClassID = 78, |
| 749 | rtcGPR64RegClassID = 79, |
| 750 | GPR64sponlyRegClassID = 80, |
| 751 | GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClassID = 81, |
| 752 | GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClassID = 82, |
| 753 | GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClassID = 83, |
| 754 | GPR64x8Class_with_x8sub_6_in_GPR64argRegClassID = 84, |
| 755 | GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClassID = 85, |
| 756 | DDRegClassID = 86, |
| 757 | DD_with_dsub0_in_FPR64_loRegClassID = 87, |
| 758 | DD_with_dsub1_in_FPR64_loRegClassID = 88, |
| 759 | XSeqPairsClassRegClassID = 89, |
| 760 | DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID = 90, |
| 761 | XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 91, |
| 762 | XSeqPairsClass_with_subo64_in_GPR64noipRegClassID = 92, |
| 763 | XSeqPairsClass_with_sube64_in_GPR64noipRegClassID = 93, |
| 764 | XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 94, |
| 765 | XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID = 95, |
| 766 | XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 96, |
| 767 | XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID = 97, |
| 768 | XSeqPairsClass_with_sub_32_in_GPR32argRegClassID = 98, |
| 769 | XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID = 99, |
| 770 | FPR128RegClassID = 100, |
| 771 | ZPRRegClassID = 101, |
| 772 | FPR128_loRegClassID = 102, |
| 773 | ZPR_4bRegClassID = 103, |
| 774 | ZPR_3bRegClassID = 104, |
| 775 | DDDRegClassID = 105, |
| 776 | DDD_with_dsub0_in_FPR64_loRegClassID = 106, |
| 777 | DDD_with_dsub1_in_FPR64_loRegClassID = 107, |
| 778 | DDD_with_dsub2_in_FPR64_loRegClassID = 108, |
| 779 | DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID = 109, |
| 780 | DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID = 110, |
| 781 | DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID = 111, |
| 782 | DDDDRegClassID = 112, |
| 783 | DDDD_with_dsub0_in_FPR64_loRegClassID = 113, |
| 784 | DDDD_with_dsub1_in_FPR64_loRegClassID = 114, |
| 785 | DDDD_with_dsub2_in_FPR64_loRegClassID = 115, |
| 786 | DDDD_with_dsub3_in_FPR64_loRegClassID = 116, |
| 787 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID = 117, |
| 788 | DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID = 118, |
| 789 | DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID = 119, |
| 790 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID = 120, |
| 791 | DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID = 121, |
| 792 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID = 122, |
| 793 | QQRegClassID = 123, |
| 794 | ZPR2RegClassID = 124, |
| 795 | QQ_with_dsub_in_FPR64_loRegClassID = 125, |
| 796 | QQ_with_qsub1_in_FPR128_loRegClassID = 126, |
| 797 | ZPR2_with_dsub_in_FPR64_loRegClassID = 127, |
| 798 | ZPR2_with_zsub1_in_ZPR_4bRegClassID = 128, |
| 799 | QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 129, |
| 800 | ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID = 130, |
| 801 | ZPR2_with_zsub0_in_ZPR_3bRegClassID = 131, |
| 802 | ZPR2_with_zsub1_in_ZPR_3bRegClassID = 132, |
| 803 | ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID = 133, |
| 804 | QQQRegClassID = 134, |
| 805 | ZPR3RegClassID = 135, |
| 806 | QQQ_with_dsub_in_FPR64_loRegClassID = 136, |
| 807 | QQQ_with_qsub1_in_FPR128_loRegClassID = 137, |
| 808 | QQQ_with_qsub2_in_FPR128_loRegClassID = 138, |
| 809 | ZPR3_with_dsub_in_FPR64_loRegClassID = 139, |
| 810 | ZPR3_with_zsub1_in_ZPR_4bRegClassID = 140, |
| 811 | ZPR3_with_zsub2_in_ZPR_4bRegClassID = 141, |
| 812 | QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 142, |
| 813 | QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 143, |
| 814 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID = 144, |
| 815 | ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 145, |
| 816 | QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 146, |
| 817 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID = 147, |
| 818 | ZPR3_with_zsub0_in_ZPR_3bRegClassID = 148, |
| 819 | ZPR3_with_zsub1_in_ZPR_3bRegClassID = 149, |
| 820 | ZPR3_with_zsub2_in_ZPR_3bRegClassID = 150, |
| 821 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID = 151, |
| 822 | ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 152, |
| 823 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID = 153, |
| 824 | QQQQRegClassID = 154, |
| 825 | ZPR4RegClassID = 155, |
| 826 | QQQQ_with_dsub_in_FPR64_loRegClassID = 156, |
| 827 | QQQQ_with_qsub1_in_FPR128_loRegClassID = 157, |
| 828 | QQQQ_with_qsub2_in_FPR128_loRegClassID = 158, |
| 829 | QQQQ_with_qsub3_in_FPR128_loRegClassID = 159, |
| 830 | ZPR4_with_dsub_in_FPR64_loRegClassID = 160, |
| 831 | ZPR4_with_zsub1_in_ZPR_4bRegClassID = 161, |
| 832 | ZPR4_with_zsub2_in_ZPR_4bRegClassID = 162, |
| 833 | ZPR4_with_zsub3_in_ZPR_4bRegClassID = 163, |
| 834 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 164, |
| 835 | QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 165, |
| 836 | QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 166, |
| 837 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID = 167, |
| 838 | ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 168, |
| 839 | ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 169, |
| 840 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 170, |
| 841 | QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 171, |
| 842 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID = 172, |
| 843 | ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 173, |
| 844 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 174, |
| 845 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID = 175, |
| 846 | ZPR4_with_zsub0_in_ZPR_3bRegClassID = 176, |
| 847 | ZPR4_with_zsub1_in_ZPR_3bRegClassID = 177, |
| 848 | ZPR4_with_zsub2_in_ZPR_3bRegClassID = 178, |
| 849 | ZPR4_with_zsub3_in_ZPR_3bRegClassID = 179, |
| 850 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID = 180, |
| 851 | ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 181, |
| 852 | ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 182, |
| 853 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID = 183, |
| 854 | ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 184, |
| 855 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID = 185, |
| 856 | |
| 857 | }; |
| 858 | } // end namespace AArch64 |
| 859 | |
| 860 | |
| 861 | // Register alternate name indices |
| 862 | |
| 863 | namespace AArch64 { |
| 864 | enum { |
| 865 | NoRegAltName, // 0 |
| 866 | vlist1, // 1 |
| 867 | vreg, // 2 |
| 868 | NUM_TARGET_REG_ALT_NAMES = 3 |
| 869 | }; |
| 870 | } // end namespace AArch64 |
| 871 | |
| 872 | |
| 873 | // Subregister indices |
| 874 | |
| 875 | namespace AArch64 { |
| 876 | enum : uint16_t { |
| 877 | NoSubRegister, |
| 878 | bsub, // 1 |
| 879 | dsub, // 2 |
| 880 | dsub0, // 3 |
| 881 | dsub1, // 4 |
| 882 | dsub2, // 5 |
| 883 | dsub3, // 6 |
| 884 | hsub, // 7 |
| 885 | qhisub, // 8 |
| 886 | qsub, // 9 |
| 887 | qsub0, // 10 |
| 888 | qsub1, // 11 |
| 889 | qsub2, // 12 |
| 890 | qsub3, // 13 |
| 891 | ssub, // 14 |
| 892 | sub_32, // 15 |
| 893 | sube32, // 16 |
| 894 | sube64, // 17 |
| 895 | subo32, // 18 |
| 896 | subo64, // 19 |
| 897 | x8sub_0, // 20 |
| 898 | x8sub_1, // 21 |
| 899 | x8sub_2, // 22 |
| 900 | x8sub_3, // 23 |
| 901 | x8sub_4, // 24 |
| 902 | x8sub_5, // 25 |
| 903 | x8sub_6, // 26 |
| 904 | x8sub_7, // 27 |
| 905 | zsub, // 28 |
| 906 | zsub0, // 29 |
| 907 | zsub1, // 30 |
| 908 | zsub2, // 31 |
| 909 | zsub3, // 32 |
| 910 | zsub_hi, // 33 |
| 911 | dsub1_then_bsub, // 34 |
| 912 | dsub1_then_hsub, // 35 |
| 913 | dsub1_then_ssub, // 36 |
| 914 | dsub3_then_bsub, // 37 |
| 915 | dsub3_then_hsub, // 38 |
| 916 | dsub3_then_ssub, // 39 |
| 917 | dsub2_then_bsub, // 40 |
| 918 | dsub2_then_hsub, // 41 |
| 919 | dsub2_then_ssub, // 42 |
| 920 | qsub1_then_bsub, // 43 |
| 921 | qsub1_then_dsub, // 44 |
| 922 | qsub1_then_hsub, // 45 |
| 923 | qsub1_then_ssub, // 46 |
| 924 | qsub3_then_bsub, // 47 |
| 925 | qsub3_then_dsub, // 48 |
| 926 | qsub3_then_hsub, // 49 |
| 927 | qsub3_then_ssub, // 50 |
| 928 | qsub2_then_bsub, // 51 |
| 929 | qsub2_then_dsub, // 52 |
| 930 | qsub2_then_hsub, // 53 |
| 931 | qsub2_then_ssub, // 54 |
| 932 | x8sub_7_then_sub_32, // 55 |
| 933 | x8sub_6_then_sub_32, // 56 |
| 934 | x8sub_5_then_sub_32, // 57 |
| 935 | x8sub_4_then_sub_32, // 58 |
| 936 | x8sub_3_then_sub_32, // 59 |
| 937 | x8sub_2_then_sub_32, // 60 |
| 938 | x8sub_1_then_sub_32, // 61 |
| 939 | subo64_then_sub_32, // 62 |
| 940 | zsub1_then_bsub, // 63 |
| 941 | zsub1_then_dsub, // 64 |
| 942 | zsub1_then_hsub, // 65 |
| 943 | zsub1_then_ssub, // 66 |
| 944 | zsub1_then_zsub, // 67 |
| 945 | zsub1_then_zsub_hi, // 68 |
| 946 | zsub3_then_bsub, // 69 |
| 947 | zsub3_then_dsub, // 70 |
| 948 | zsub3_then_hsub, // 71 |
| 949 | zsub3_then_ssub, // 72 |
| 950 | zsub3_then_zsub, // 73 |
| 951 | zsub3_then_zsub_hi, // 74 |
| 952 | zsub2_then_bsub, // 75 |
| 953 | zsub2_then_dsub, // 76 |
| 954 | zsub2_then_hsub, // 77 |
| 955 | zsub2_then_ssub, // 78 |
| 956 | zsub2_then_zsub, // 79 |
| 957 | zsub2_then_zsub_hi, // 80 |
| 958 | dsub0_dsub1, // 81 |
| 959 | dsub0_dsub1_dsub2, // 82 |
| 960 | dsub1_dsub2, // 83 |
| 961 | dsub1_dsub2_dsub3, // 84 |
| 962 | dsub2_dsub3, // 85 |
| 963 | dsub_qsub1_then_dsub, // 86 |
| 964 | dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 87 |
| 965 | dsub_qsub1_then_dsub_qsub2_then_dsub, // 88 |
| 966 | qsub0_qsub1, // 89 |
| 967 | qsub0_qsub1_qsub2, // 90 |
| 968 | qsub1_qsub2, // 91 |
| 969 | qsub1_qsub2_qsub3, // 92 |
| 970 | qsub2_qsub3, // 93 |
| 971 | qsub1_then_dsub_qsub2_then_dsub, // 94 |
| 972 | qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 95 |
| 973 | qsub2_then_dsub_qsub3_then_dsub, // 96 |
| 974 | sub_32_x8sub_1_then_sub_32, // 97 |
| 975 | x8sub_0_x8sub_1, // 98 |
| 976 | x8sub_2_x8sub_3, // 99 |
| 977 | x8sub_4_x8sub_5, // 100 |
| 978 | x8sub_6_x8sub_7, // 101 |
| 979 | x8sub_6_then_sub_32_x8sub_7_then_sub_32, // 102 |
| 980 | x8sub_4_then_sub_32_x8sub_5_then_sub_32, // 103 |
| 981 | x8sub_2_then_sub_32_x8sub_3_then_sub_32, // 104 |
| 982 | sub_32_subo64_then_sub_32, // 105 |
| 983 | dsub_zsub1_then_dsub, // 106 |
| 984 | zsub_zsub1_then_zsub, // 107 |
| 985 | dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 108 |
| 986 | dsub_zsub1_then_dsub_zsub2_then_dsub, // 109 |
| 987 | zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 110 |
| 988 | zsub_zsub1_then_zsub_zsub2_then_zsub, // 111 |
| 989 | zsub0_zsub1, // 112 |
| 990 | zsub0_zsub1_zsub2, // 113 |
| 991 | zsub1_zsub2, // 114 |
| 992 | zsub1_zsub2_zsub3, // 115 |
| 993 | zsub2_zsub3, // 116 |
| 994 | zsub1_then_dsub_zsub2_then_dsub, // 117 |
| 995 | zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, // 118 |
| 996 | zsub1_then_zsub_zsub2_then_zsub, // 119 |
| 997 | zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, // 120 |
| 998 | zsub2_then_dsub_zsub3_then_dsub, // 121 |
| 999 | zsub2_then_zsub_zsub3_then_zsub, // 122 |
| 1000 | NUM_TARGET_SUBREGS |
| 1001 | }; |
| 1002 | } // end namespace AArch64 |
| 1003 | |
| 1004 | // Register pressure sets enum. |
| 1005 | namespace AArch64 { |
| 1006 | enum RegisterPressureSets { |
| 1007 | GPR32sponly = 0, |
| 1008 | rtcGPR64 = 1, |
| 1009 | PPR_3b = 2, |
| 1010 | GPR64x8Class_with_x8sub_0_in_rtcGPR64 = 3, |
| 1011 | PPR = 4, |
| 1012 | FPR16_lo = 5, |
| 1013 | GPR64x8Class_with_x8sub_0_in_tcGPR64 = 6, |
| 1014 | ZPR_3b = 7, |
| 1015 | FPR16_lo_with_ZPR_3b = 8, |
| 1016 | DD_with_dsub1_in_FPR64_lo_with_ZPR_3b = 9, |
| 1017 | DDD_with_dsub2_in_FPR64_lo_with_ZPR_3b = 10, |
| 1018 | DDD_with_dsub2_in_FPR64_lo_with_ZPR4_with_zsub1_in_ZPR_3b = 11, |
| 1019 | DDDD_with_dsub3_in_FPR64_lo_with_ZPR_3b = 12, |
| 1020 | DDDD_with_dsub3_in_FPR64_lo_with_ZPR4_with_zsub1_in_ZPR_3b = 13, |
| 1021 | DDDD_with_dsub3_in_FPR64_lo_with_ZPR4_with_zsub2_in_ZPR_3b = 14, |
| 1022 | FPR16_lo_with_ZPR4_with_zsub1_in_ZPR_3b = 15, |
| 1023 | FPR8 = 16, |
| 1024 | FPR16_lo_with_ZPR4_with_zsub2_in_ZPR_3b = 17, |
| 1025 | GPR32 = 18, |
| 1026 | FPR16_lo_with_ZPR4_with_zsub3_in_ZPR_3b = 19, |
| 1027 | ZPR4_with_zsub3_in_ZPR_4b = 20, |
| 1028 | ZPR_4b = 21, |
| 1029 | FPR8_with_ZPR_3b = 22, |
| 1030 | FPR8_with_ZPR4_with_zsub1_in_ZPR_3b = 23, |
| 1031 | FPR8_with_ZPR4_with_zsub2_in_ZPR_3b = 24, |
| 1032 | FPR8_with_ZPR4_with_zsub3_in_ZPR_3b = 25, |
| 1033 | ZPR4_with_zsub2_in_ZPR_4b = 26, |
| 1034 | FPR8_with_ZPR_4b = 27, |
| 1035 | FPR8_with_ZPR4_with_zsub1_in_ZPR_4b = 28, |
| 1036 | FPR8_with_ZPR4_with_zsub2_in_ZPR_4b = 29, |
| 1037 | FPR8_with_ZPR4_with_zsub3_in_ZPR_4b = 30, |
| 1038 | ZPR = 31, |
| 1039 | }; |
| 1040 | } // end namespace AArch64 |
| 1041 | |
| 1042 | } // end namespace llvm |
| 1043 | |
| 1044 | #endif // GET_REGINFO_ENUM |
| 1045 | |
| 1046 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 1047 | |* *| |
| 1048 | |* MC Register Information *| |
| 1049 | |* *| |
| 1050 | |* Automatically generated file, do not edit! *| |
| 1051 | |* *| |
| 1052 | \*===----------------------------------------------------------------------===*/ |
| 1053 | |
| 1054 | |
| 1055 | #ifdef GET_REGINFO_MC_DESC |
| 1056 | #undef GET_REGINFO_MC_DESC |
| 1057 | |
| 1058 | namespace llvm { |
| 1059 | |
| 1060 | extern const MCPhysReg AArch64RegDiffLists[] = { |
| 1061 | /* 0 */ 64585, 1, 1, 1, 1, 1, 1, 1, 0, |
| 1062 | /* 9 */ 1, 76, 1, 1, 1, 1, 1, 1, 0, |
| 1063 | /* 18 */ 64965, 1, 1, 1, 74, 1, 1, 1, 0, |
| 1064 | /* 27 */ 65105, 1, 1, 1, 0, |
| 1065 | /* 32 */ 65201, 1, 1, 1, 0, |
| 1066 | /* 37 */ 31, 287, 17, 65504, 1, 1, 1, 0, |
| 1067 | /* 45 */ 31, 288, 17, 65504, 1, 1, 1, 0, |
| 1068 | /* 53 */ 31, 289, 17, 65504, 1, 1, 1, 0, |
| 1069 | /* 61 */ 31, 290, 17, 65504, 1, 1, 1, 0, |
| 1070 | /* 69 */ 31, 291, 17, 65504, 1, 1, 1, 0, |
| 1071 | /* 77 */ 31, 292, 17, 65504, 1, 1, 1, 0, |
| 1072 | /* 85 */ 31, 293, 17, 65504, 1, 1, 1, 0, |
| 1073 | /* 93 */ 31, 294, 17, 65504, 1, 1, 1, 0, |
| 1074 | /* 101 */ 31, 295, 17, 65504, 1, 1, 1, 0, |
| 1075 | /* 109 */ 304, 65504, 1, 1, 1, 0, |
| 1076 | /* 115 */ 305, 65504, 1, 1, 1, 0, |
| 1077 | /* 121 */ 306, 65504, 1, 1, 1, 0, |
| 1078 | /* 127 */ 307, 65504, 1, 1, 1, 0, |
| 1079 | /* 133 */ 308, 65504, 1, 1, 1, 0, |
| 1080 | /* 139 */ 309, 65504, 1, 1, 1, 0, |
| 1081 | /* 145 */ 310, 65504, 1, 1, 1, 0, |
| 1082 | /* 151 */ 311, 65504, 1, 1, 1, 0, |
| 1083 | /* 157 */ 312, 65504, 1, 1, 1, 0, |
| 1084 | /* 163 */ 31, 286, 17, 65495, 9, 1, 1, 0, |
| 1085 | /* 171 */ 31, 287, 17, 65495, 9, 1, 1, 0, |
| 1086 | /* 179 */ 303, 65495, 9, 1, 1, 0, |
| 1087 | /* 185 */ 304, 65495, 9, 1, 1, 0, |
| 1088 | /* 191 */ 7, 29, 1, 1, 0, |
| 1089 | /* 196 */ 7, 29, 1, 1, 46, 29, 1, 1, 0, |
| 1090 | /* 205 */ 64933, 1, 1, 75, 1, 1, 0, |
| 1091 | /* 212 */ 65073, 1, 1, 0, |
| 1092 | /* 216 */ 65169, 1, 1, 0, |
| 1093 | /* 220 */ 31, 295, 17, 65505, 1, 1, 0, |
| 1094 | /* 227 */ 31, 296, 17, 65505, 1, 1, 0, |
| 1095 | /* 234 */ 312, 65505, 1, 1, 0, |
| 1096 | /* 239 */ 313, 65505, 1, 1, 0, |
| 1097 | /* 244 */ 31, 285, 17, 65494, 10, 1, 0, |
| 1098 | /* 251 */ 31, 286, 17, 65494, 10, 1, 0, |
| 1099 | /* 258 */ 302, 65494, 10, 1, 0, |
| 1100 | /* 263 */ 303, 65494, 10, 1, 0, |
| 1101 | /* 268 */ 7, 1, 29, 1, 0, |
| 1102 | /* 273 */ 7, 1, 29, 1, 46, 1, 29, 1, 0, |
| 1103 | /* 282 */ 7, 30, 1, 0, |
| 1104 | /* 286 */ 7, 30, 1, 46, 30, 1, 0, |
| 1105 | /* 293 */ 64997, 1, 76, 1, 0, |
| 1106 | /* 298 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 298, 1, 0, |
| 1107 | /* 313 */ 65204, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 330, 1, 0, |
| 1108 | /* 328 */ 64527, 1, 0, |
| 1109 | /* 331 */ 64561, 1, 0, |
| 1110 | /* 334 */ 65137, 1, 0, |
| 1111 | /* 337 */ 65207, 1, 0, |
| 1112 | /* 340 */ 65208, 1, 0, |
| 1113 | /* 343 */ 65209, 1, 0, |
| 1114 | /* 346 */ 65210, 1, 0, |
| 1115 | /* 349 */ 65211, 1, 0, |
| 1116 | /* 352 */ 65212, 1, 0, |
| 1117 | /* 355 */ 65213, 1, 0, |
| 1118 | /* 358 */ 65214, 1, 0, |
| 1119 | /* 361 */ 65215, 1, 0, |
| 1120 | /* 364 */ 65216, 1, 0, |
| 1121 | /* 367 */ 65217, 1, 0, |
| 1122 | /* 370 */ 65218, 1, 0, |
| 1123 | /* 373 */ 65219, 1, 0, |
| 1124 | /* 376 */ 65220, 1, 0, |
| 1125 | /* 379 */ 65221, 1, 0, |
| 1126 | /* 382 */ 65233, 1, 0, |
| 1127 | /* 385 */ 64, 80, 65424, 80, 124, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 107, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, |
| 1128 | /* 418 */ 124, 159, 1, 62, 65503, 34, 65503, 34, 65503, 1, 107, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, |
| 1129 | /* 438 */ 65504, 299, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0, |
| 1130 | /* 449 */ 64, 80, 65424, 80, 124, 64, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 77, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, |
| 1131 | /* 482 */ 124, 160, 31, 33, 65504, 62, 65503, 34, 65503, 1, 77, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, |
| 1132 | /* 502 */ 65504, 300, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0, |
| 1133 | /* 513 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 108, 63, 65503, 34, 65503, 1, 0, |
| 1134 | /* 531 */ 64, 80, 65424, 80, 124, 63, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 77, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, |
| 1135 | /* 564 */ 124, 159, 1, 63, 1, 65503, 1, 62, 65503, 1, 77, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, |
| 1136 | /* 584 */ 65504, 299, 1, 63, 1, 65503, 1, 62, 65503, 1, 0, |
| 1137 | /* 595 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 77, 64, 65504, 63, 65503, 1, 0, |
| 1138 | /* 613 */ 65503, 1, 128, 65503, 1, 172, 65503, 1, 0, |
| 1139 | /* 622 */ 31, 296, 17, 65506, 1, 0, |
| 1140 | /* 628 */ 31, 297, 17, 65506, 1, 0, |
| 1141 | /* 634 */ 313, 65506, 1, 0, |
| 1142 | /* 638 */ 314, 65506, 1, 0, |
| 1143 | /* 642 */ 2, 0, |
| 1144 | /* 644 */ 2, 4, 0, |
| 1145 | /* 647 */ 65008, 4, 0, |
| 1146 | /* 650 */ 6, 0, |
| 1147 | /* 652 */ 31, 284, 17, 65493, 11, 0, |
| 1148 | /* 658 */ 31, 285, 17, 65493, 11, 0, |
| 1149 | /* 664 */ 301, 65493, 11, 0, |
| 1150 | /* 668 */ 302, 65493, 11, 0, |
| 1151 | /* 672 */ 1, 505, 16, 0, |
| 1152 | /* 676 */ 65323, 511, 16, 0, |
| 1153 | /* 680 */ 7, 1, 1, 29, 0, |
| 1154 | /* 685 */ 7, 1, 1, 29, 46, 1, 1, 29, 0, |
| 1155 | /* 694 */ 64, 80, 65424, 80, 124, 63, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 78, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, |
| 1156 | /* 727 */ 124, 159, 1, 62, 1, 65503, 34, 65503, 1, 29, 78, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, |
| 1157 | /* 747 */ 65504, 299, 1, 62, 1, 65503, 34, 65503, 1, 29, 0, |
| 1158 | /* 758 */ 7, 1, 30, 0, |
| 1159 | /* 762 */ 7, 1, 30, 46, 1, 30, 0, |
| 1160 | /* 769 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 78, 63, 1, 65503, 1, 30, 0, |
| 1161 | /* 787 */ 7, 31, 0, |
| 1162 | /* 790 */ 7, 31, 46, 31, 0, |
| 1163 | /* 795 */ 65504, 31, 97, 65504, 31, 141, 65504, 31, 0, |
| 1164 | /* 804 */ 65297, 77, 0, |
| 1165 | /* 807 */ 1, 82, 0, |
| 1166 | /* 810 */ 65008, 82, 0, |
| 1167 | /* 813 */ 65236, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 31, 96, 0, |
| 1168 | /* 830 */ 65236, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 63, 96, 0, |
| 1169 | /* 847 */ 65172, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 30, 96, 65504, 96, 76, 1, 65300, 96, 0, |
| 1170 | /* 877 */ 65172, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 76, 1, 65300, 96, 0, |
| 1171 | /* 907 */ 65172, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 62, 96, 65504, 96, 76, 65505, 65300, 96, 0, |
| 1172 | /* 937 */ 65204, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 76, 64, 65473, 64, 65441, 65331, 64, 32, 64, 65345, 96, 0, |
| 1173 | /* 983 */ 65204, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 76, 64, 65441, 64, 65473, 65299, 64, 32, 64, 65377, 96, 0, |
| 1174 | /* 1029 */ 65204, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 29, 96, 65472, 32, 64, 32, 76, 64, 65473, 64, 65473, 65299, 64, 32, 64, 65377, 96, 0, |
| 1175 | /* 1075 */ 65204, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65505, 65412, 65456, 112, 65456, 65472, 268, 65473, 65412, 65456, 112, 65456, 65472, 268, 61, 96, 65472, 32, 64, 32, 76, 64, 65473, 64, 65473, 65299, 64, 32, 64, 65377, 96, 0, |
| 1176 | /* 1121 */ 96, 140, 0, |
| 1177 | /* 1124 */ 213, 0, |
| 1178 | /* 1126 */ 65412, 65456, 112, 65456, 65472, 268, 0, |
| 1179 | /* 1133 */ 65252, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 299, 0, |
| 1180 | /* 1145 */ 65250, 65505, 65324, 213, 314, 0, |
| 1181 | /* 1151 */ 65234, 65505, 32, 65505, 315, 0, |
| 1182 | /* 1157 */ 65233, 65505, 32, 65505, 316, 0, |
| 1183 | /* 1163 */ 65232, 65505, 32, 65505, 317, 0, |
| 1184 | /* 1169 */ 65231, 65505, 32, 65505, 318, 0, |
| 1185 | /* 1175 */ 65230, 65505, 32, 65505, 319, 0, |
| 1186 | /* 1181 */ 65229, 65505, 32, 65505, 320, 0, |
| 1187 | /* 1187 */ 65228, 65505, 32, 65505, 321, 0, |
| 1188 | /* 1193 */ 65227, 65505, 32, 65505, 322, 0, |
| 1189 | /* 1199 */ 65226, 65505, 32, 65505, 323, 0, |
| 1190 | /* 1205 */ 65225, 65505, 32, 65505, 324, 0, |
| 1191 | /* 1211 */ 65224, 65505, 32, 65505, 325, 0, |
| 1192 | /* 1217 */ 65223, 65505, 32, 65505, 326, 0, |
| 1193 | /* 1223 */ 65222, 65505, 32, 65505, 327, 0, |
| 1194 | /* 1229 */ 65221, 65505, 32, 65505, 328, 0, |
| 1195 | /* 1235 */ 65252, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 331, 0, |
| 1196 | /* 1247 */ 65009, 213, 65329, 65535, 506, 0, |
| 1197 | /* 1253 */ 521, 0, |
| 1198 | /* 1255 */ 527, 0, |
| 1199 | /* 1257 */ 65322, 0, |
| 1200 | /* 1259 */ 65238, 65328, 0, |
| 1201 | /* 1262 */ 65342, 0, |
| 1202 | /* 1264 */ 65374, 0, |
| 1203 | /* 1266 */ 65389, 0, |
| 1204 | /* 1268 */ 65405, 0, |
| 1205 | /* 1270 */ 65421, 0, |
| 1206 | /* 1272 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 298, 64, 32, 1, 65440, 0, |
| 1207 | /* 1293 */ 65188, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 330, 64, 32, 1, 65440, 0, |
| 1208 | /* 1314 */ 65188, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 330, 64, 32, 65505, 65440, 0, |
| 1209 | /* 1335 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0, |
| 1210 | /* 1367 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65473, 64, 65441, 0, |
| 1211 | /* 1389 */ 65469, 0, |
| 1212 | /* 1391 */ 65268, 112, 65456, 65472, 1, 112, 65456, 65472, 0, |
| 1213 | /* 1400 */ 65268, 112, 65456, 65472, 33, 112, 65456, 65472, 0, |
| 1214 | /* 1409 */ 65456, 112, 65456, 65472, 0, |
| 1215 | /* 1414 */ 65220, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0, |
| 1216 | /* 1446 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 297, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, |
| 1217 | /* 1478 */ 65220, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 113, 65456, 112, 65456, 65472, 81, 65456, 112, 65456, 65472, 329, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0, |
| 1218 | /* 1510 */ 65236, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 329, 64, 65441, 64, 65473, 0, |
| 1219 | /* 1532 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 297, 64, 65473, 64, 65473, 0, |
| 1220 | /* 1554 */ 65236, 112, 65456, 65472, 33, 112, 65456, 65472, 33, 112, 65456, 65472, 1, 112, 65456, 65472, 329, 64, 65473, 64, 65473, 0, |
| 1221 | /* 1576 */ 65501, 0, |
| 1222 | /* 1578 */ 65204, 112, 65456, 65472, 1, 112, 65456, 65472, 33, 112, 65456, 65472, 330, 65505, 0, |
| 1223 | /* 1593 */ 31, 284, 2, 65507, 0, |
| 1224 | /* 1598 */ 65323, 527, 2, 65507, 0, |
| 1225 | /* 1603 */ 31, 297, 17, 65507, 0, |
| 1226 | /* 1608 */ 31, 298, 17, 65507, 0, |
| 1227 | /* 1613 */ 286, 65507, 0, |
| 1228 | /* 1616 */ 314, 65507, 0, |
| 1229 | /* 1619 */ 315, 65507, 0, |
| 1230 | /* 1622 */ 529, 65507, 0, |
| 1231 | /* 1625 */ 65526, 0, |
| 1232 | /* 1627 */ 65533, 0, |
| 1233 | /* 1629 */ 65534, 0, |
| 1234 | /* 1631 */ 65260, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 312, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1235 | /* 1656 */ 65259, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 313, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1236 | /* 1681 */ 65258, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 314, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1237 | /* 1706 */ 65257, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 315, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1238 | /* 1731 */ 65256, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 316, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1239 | /* 1756 */ 65255, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 317, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1240 | /* 1781 */ 65254, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 318, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1241 | /* 1806 */ 65253, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 319, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1242 | /* 1831 */ 65252, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 320, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1243 | /* 1856 */ 65251, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 321, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1244 | /* 1881 */ 65250, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 322, 17, 1, 1, 1, 65519, 65535, 65535, 0, |
| 1245 | /* 1906 */ 65273, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 32, 65505, 65324, 213, 311, 17, 1, 1, 65522, 65534, 65535, 65535, 0, |
| 1246 | }; |
| 1247 | |
| 1248 | extern const LaneBitmask AArch64LaneMaskLists[] = { |
| 1249 | /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(), |
| 1250 | /* 2 */ LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| 1251 | /* 5 */ LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| 1252 | /* 10 */ LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| 1253 | /* 14 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| 1254 | /* 17 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| 1255 | /* 22 */ LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| 1256 | /* 26 */ LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(), |
| 1257 | /* 29 */ LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask::getAll(), |
| 1258 | /* 32 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(), |
| 1259 | /* 35 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(), |
| 1260 | /* 38 */ LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(), |
| 1261 | /* 43 */ LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(), |
| 1262 | /* 52 */ LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(), |
| 1263 | /* 59 */ LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000080), LaneBitmask::getAll(), |
| 1264 | /* 64 */ LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000080), LaneBitmask::getAll(), |
| 1265 | /* 68 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000100), LaneBitmask::getAll(), |
| 1266 | /* 73 */ LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000200), LaneBitmask::getAll(), |
| 1267 | /* 78 */ LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(), |
| 1268 | /* 83 */ LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(), |
| 1269 | /* 87 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000000800), LaneBitmask::getAll(), |
| 1270 | /* 92 */ LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000400), LaneBitmask(0x0000000000001000), LaneBitmask::getAll(), |
| 1271 | /* 97 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000002000), LaneBitmask::getAll(), |
| 1272 | /* 106 */ LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000004000), LaneBitmask::getAll(), |
| 1273 | /* 115 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000100000), LaneBitmask::getAll(), |
| 1274 | /* 118 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000400000), LaneBitmask::getAll(), |
| 1275 | /* 123 */ LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000400000), LaneBitmask::getAll(), |
| 1276 | /* 132 */ LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000400000), LaneBitmask::getAll(), |
| 1277 | /* 139 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000001000000), LaneBitmask::getAll(), |
| 1278 | /* 148 */ LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000004000000), LaneBitmask::getAll(), |
| 1279 | /* 157 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000004000000), LaneBitmask::getAll(), |
| 1280 | }; |
| 1281 | |
| 1282 | extern const uint16_t AArch64SubRegIdxLists[] = { |
| 1283 | /* 0 */ 2, 14, 7, 1, 0, |
| 1284 | /* 5 */ 15, 0, |
| 1285 | /* 7 */ 16, 18, 0, |
| 1286 | /* 10 */ 28, 2, 14, 7, 1, 33, 0, |
| 1287 | /* 17 */ 3, 14, 7, 1, 4, 36, 35, 34, 0, |
| 1288 | /* 26 */ 3, 14, 7, 1, 4, 36, 35, 34, 5, 42, 41, 40, 81, 83, 0, |
| 1289 | /* 41 */ 3, 14, 7, 1, 4, 36, 35, 34, 5, 42, 41, 40, 6, 39, 38, 37, 81, 82, 83, 84, 85, 0, |
| 1290 | /* 63 */ 10, 2, 14, 7, 1, 11, 44, 46, 45, 43, 86, 0, |
| 1291 | /* 75 */ 10, 2, 14, 7, 1, 11, 44, 46, 45, 43, 12, 52, 54, 53, 51, 86, 88, 89, 91, 94, 0, |
| 1292 | /* 96 */ 10, 2, 14, 7, 1, 11, 44, 46, 45, 43, 12, 52, 54, 53, 51, 13, 48, 50, 49, 47, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 0, |
| 1293 | /* 128 */ 20, 15, 21, 61, 22, 60, 23, 59, 24, 58, 25, 57, 26, 56, 27, 55, 97, 98, 99, 100, 101, 102, 103, 104, 0, |
| 1294 | /* 153 */ 17, 15, 19, 62, 105, 0, |
| 1295 | /* 159 */ 29, 28, 2, 14, 7, 1, 33, 30, 67, 64, 66, 65, 63, 68, 106, 107, 0, |
| 1296 | /* 176 */ 29, 28, 2, 14, 7, 1, 33, 30, 67, 64, 66, 65, 63, 68, 31, 79, 76, 78, 77, 75, 80, 106, 107, 109, 111, 112, 114, 117, 119, 0, |
| 1297 | /* 206 */ 29, 28, 2, 14, 7, 1, 33, 30, 67, 64, 66, 65, 63, 68, 31, 79, 76, 78, 77, 75, 80, 32, 73, 70, 72, 71, 69, 74, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 0, |
| 1298 | }; |
| 1299 | |
| 1300 | extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = { |
| 1301 | { 65535, 65535 }, |
| 1302 | { 0, 8 }, // bsub |
| 1303 | { 0, 32 }, // dsub |
| 1304 | { 0, 64 }, // dsub0 |
| 1305 | { 0, 64 }, // dsub1 |
| 1306 | { 0, 64 }, // dsub2 |
| 1307 | { 0, 64 }, // dsub3 |
| 1308 | { 0, 16 }, // hsub |
| 1309 | { 0, 64 }, // qhisub |
| 1310 | { 0, 64 }, // qsub |
| 1311 | { 0, 128 }, // qsub0 |
| 1312 | { 0, 128 }, // qsub1 |
| 1313 | { 0, 128 }, // qsub2 |
| 1314 | { 0, 128 }, // qsub3 |
| 1315 | { 0, 32 }, // ssub |
| 1316 | { 0, 32 }, // sub_32 |
| 1317 | { 0, 32 }, // sube32 |
| 1318 | { 0, 64 }, // sube64 |
| 1319 | { 0, 32 }, // subo32 |
| 1320 | { 0, 64 }, // subo64 |
| 1321 | { 0, 64 }, // x8sub_0 |
| 1322 | { 64, 64 }, // x8sub_1 |
| 1323 | { 128, 64 }, // x8sub_2 |
| 1324 | { 192, 64 }, // x8sub_3 |
| 1325 | { 256, 64 }, // x8sub_4 |
| 1326 | { 320, 64 }, // x8sub_5 |
| 1327 | { 384, 64 }, // x8sub_6 |
| 1328 | { 448, 64 }, // x8sub_7 |
| 1329 | { 0, 128 }, // zsub |
| 1330 | { 65535, 128 }, // zsub0 |
| 1331 | { 65535, 128 }, // zsub1 |
| 1332 | { 65535, 128 }, // zsub2 |
| 1333 | { 65535, 128 }, // zsub3 |
| 1334 | { 0, 128 }, // zsub_hi |
| 1335 | { 0, 8 }, // dsub1_then_bsub |
| 1336 | { 0, 16 }, // dsub1_then_hsub |
| 1337 | { 0, 32 }, // dsub1_then_ssub |
| 1338 | { 0, 8 }, // dsub3_then_bsub |
| 1339 | { 0, 16 }, // dsub3_then_hsub |
| 1340 | { 0, 32 }, // dsub3_then_ssub |
| 1341 | { 0, 8 }, // dsub2_then_bsub |
| 1342 | { 0, 16 }, // dsub2_then_hsub |
| 1343 | { 0, 32 }, // dsub2_then_ssub |
| 1344 | { 0, 8 }, // qsub1_then_bsub |
| 1345 | { 0, 32 }, // qsub1_then_dsub |
| 1346 | { 0, 16 }, // qsub1_then_hsub |
| 1347 | { 0, 32 }, // qsub1_then_ssub |
| 1348 | { 0, 8 }, // qsub3_then_bsub |
| 1349 | { 0, 32 }, // qsub3_then_dsub |
| 1350 | { 0, 16 }, // qsub3_then_hsub |
| 1351 | { 0, 32 }, // qsub3_then_ssub |
| 1352 | { 0, 8 }, // qsub2_then_bsub |
| 1353 | { 0, 32 }, // qsub2_then_dsub |
| 1354 | { 0, 16 }, // qsub2_then_hsub |
| 1355 | { 0, 32 }, // qsub2_then_ssub |
| 1356 | { 448, 32 }, // x8sub_7_then_sub_32 |
| 1357 | { 384, 32 }, // x8sub_6_then_sub_32 |
| 1358 | { 320, 32 }, // x8sub_5_then_sub_32 |
| 1359 | { 256, 32 }, // x8sub_4_then_sub_32 |
| 1360 | { 192, 32 }, // x8sub_3_then_sub_32 |
| 1361 | { 128, 32 }, // x8sub_2_then_sub_32 |
| 1362 | { 64, 32 }, // x8sub_1_then_sub_32 |
| 1363 | { 0, 32 }, // subo64_then_sub_32 |
| 1364 | { 65535, 65535 }, // zsub1_then_bsub |
| 1365 | { 65535, 65535 }, // zsub1_then_dsub |
| 1366 | { 65535, 65535 }, // zsub1_then_hsub |
| 1367 | { 65535, 65535 }, // zsub1_then_ssub |
| 1368 | { 65535, 65535 }, // zsub1_then_zsub |
| 1369 | { 65535, 65535 }, // zsub1_then_zsub_hi |
| 1370 | { 65535, 65535 }, // zsub3_then_bsub |
| 1371 | { 65535, 65535 }, // zsub3_then_dsub |
| 1372 | { 65535, 65535 }, // zsub3_then_hsub |
| 1373 | { 65535, 65535 }, // zsub3_then_ssub |
| 1374 | { 65535, 65535 }, // zsub3_then_zsub |
| 1375 | { 65535, 65535 }, // zsub3_then_zsub_hi |
| 1376 | { 65535, 65535 }, // zsub2_then_bsub |
| 1377 | { 65535, 65535 }, // zsub2_then_dsub |
| 1378 | { 65535, 65535 }, // zsub2_then_hsub |
| 1379 | { 65535, 65535 }, // zsub2_then_ssub |
| 1380 | { 65535, 65535 }, // zsub2_then_zsub |
| 1381 | { 65535, 65535 }, // zsub2_then_zsub_hi |
| 1382 | { 65535, 128 }, // dsub0_dsub1 |
| 1383 | { 65535, 192 }, // dsub0_dsub1_dsub2 |
| 1384 | { 65535, 128 }, // dsub1_dsub2 |
| 1385 | { 65535, 192 }, // dsub1_dsub2_dsub3 |
| 1386 | { 65535, 128 }, // dsub2_dsub3 |
| 1387 | { 65535, 64 }, // dsub_qsub1_then_dsub |
| 1388 | { 65535, 128 }, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 1389 | { 65535, 96 }, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 1390 | { 65535, 256 }, // qsub0_qsub1 |
| 1391 | { 65535, 384 }, // qsub0_qsub1_qsub2 |
| 1392 | { 65535, 256 }, // qsub1_qsub2 |
| 1393 | { 65535, 384 }, // qsub1_qsub2_qsub3 |
| 1394 | { 65535, 256 }, // qsub2_qsub3 |
| 1395 | { 65535, 64 }, // qsub1_then_dsub_qsub2_then_dsub |
| 1396 | { 65535, 96 }, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 1397 | { 65535, 64 }, // qsub2_then_dsub_qsub3_then_dsub |
| 1398 | { 65535, 64 }, // sub_32_x8sub_1_then_sub_32 |
| 1399 | { 0, 128 }, // x8sub_0_x8sub_1 |
| 1400 | { 128, 128 }, // x8sub_2_x8sub_3 |
| 1401 | { 256, 128 }, // x8sub_4_x8sub_5 |
| 1402 | { 384, 128 }, // x8sub_6_x8sub_7 |
| 1403 | { 65535, 64 }, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 1404 | { 65535, 64 }, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 1405 | { 65535, 64 }, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 1406 | { 65535, 64 }, // sub_32_subo64_then_sub_32 |
| 1407 | { 65535, 31 }, // dsub_zsub1_then_dsub |
| 1408 | { 65535, 127 }, // zsub_zsub1_then_zsub |
| 1409 | { 65535, 29 }, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 1410 | { 65535, 30 }, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 1411 | { 65535, 125 }, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 1412 | { 65535, 126 }, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 1413 | { 65535, 256 }, // zsub0_zsub1 |
| 1414 | { 65535, 384 }, // zsub0_zsub1_zsub2 |
| 1415 | { 65535, 256 }, // zsub1_zsub2 |
| 1416 | { 65535, 384 }, // zsub1_zsub2_zsub3 |
| 1417 | { 65535, 256 }, // zsub2_zsub3 |
| 1418 | { 65535, 65534 }, // zsub1_then_dsub_zsub2_then_dsub |
| 1419 | { 65535, 65533 }, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 1420 | { 65535, 65534 }, // zsub1_then_zsub_zsub2_then_zsub |
| 1421 | { 65535, 65533 }, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 1422 | { 65535, 65534 }, // zsub2_then_dsub_zsub3_then_dsub |
| 1423 | { 65535, 65534 }, // zsub2_then_zsub_zsub3_then_zsub |
| 1424 | }; |
| 1425 | |
| 1426 | |
| 1427 | #ifdef __GNUC__ |
| 1428 | #pragma GCC diagnostic push |
| 1429 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 1430 | #endif |
| 1431 | extern const char AArch64RegStrings[] = { |
| 1432 | /* 0 */ "B10\0" |
| 1433 | /* 4 */ "D7_D8_D9_D10\0" |
| 1434 | /* 17 */ "H10\0" |
| 1435 | /* 21 */ "P10\0" |
| 1436 | /* 25 */ "Q7_Q8_Q9_Q10\0" |
| 1437 | /* 38 */ "S10\0" |
| 1438 | /* 42 */ "W10\0" |
| 1439 | /* 46 */ "X10\0" |
| 1440 | /* 50 */ "Z7_Z8_Z9_Z10\0" |
| 1441 | /* 63 */ "B20\0" |
| 1442 | /* 67 */ "D17_D18_D19_D20\0" |
| 1443 | /* 83 */ "H20\0" |
| 1444 | /* 87 */ "Q17_Q18_Q19_Q20\0" |
| 1445 | /* 103 */ "S20\0" |
| 1446 | /* 107 */ "W20\0" |
| 1447 | /* 111 */ "X20\0" |
| 1448 | /* 115 */ "Z17_Z18_Z19_Z20\0" |
| 1449 | /* 131 */ "B30\0" |
| 1450 | /* 135 */ "D27_D28_D29_D30\0" |
| 1451 | /* 151 */ "H30\0" |
| 1452 | /* 155 */ "Q27_Q28_Q29_Q30\0" |
| 1453 | /* 171 */ "S30\0" |
| 1454 | /* 175 */ "W30\0" |
| 1455 | /* 179 */ "Z27_Z28_Z29_Z30\0" |
| 1456 | /* 195 */ "B0\0" |
| 1457 | /* 198 */ "D29_D30_D31_D0\0" |
| 1458 | /* 213 */ "H0\0" |
| 1459 | /* 216 */ "P0\0" |
| 1460 | /* 219 */ "Q29_Q30_Q31_Q0\0" |
| 1461 | /* 234 */ "S0\0" |
| 1462 | /* 237 */ "W0\0" |
| 1463 | /* 240 */ "X0\0" |
| 1464 | /* 243 */ "Z29_Z30_Z31_Z0\0" |
| 1465 | /* 258 */ "B11\0" |
| 1466 | /* 262 */ "D8_D9_D10_D11\0" |
| 1467 | /* 276 */ "H11\0" |
| 1468 | /* 280 */ "P11\0" |
| 1469 | /* 284 */ "Q8_Q9_Q10_Q11\0" |
| 1470 | /* 298 */ "S11\0" |
| 1471 | /* 302 */ "W10_W11\0" |
| 1472 | /* 310 */ "X4_X5_X6_X7_X8_X9_X10_X11\0" |
| 1473 | /* 336 */ "Z8_Z9_Z10_Z11\0" |
| 1474 | /* 350 */ "B21\0" |
| 1475 | /* 354 */ "D18_D19_D20_D21\0" |
| 1476 | /* 370 */ "H21\0" |
| 1477 | /* 374 */ "Q18_Q19_Q20_Q21\0" |
| 1478 | /* 390 */ "S21\0" |
| 1479 | /* 394 */ "W20_W21\0" |
| 1480 | /* 402 */ "X14_X15_X16_X17_X18_X19_X20_X21\0" |
| 1481 | /* 434 */ "Z18_Z19_Z20_Z21\0" |
| 1482 | /* 450 */ "B31\0" |
| 1483 | /* 454 */ "D28_D29_D30_D31\0" |
| 1484 | /* 470 */ "H31\0" |
| 1485 | /* 474 */ "Q28_Q29_Q30_Q31\0" |
| 1486 | /* 490 */ "S31\0" |
| 1487 | /* 494 */ "Z28_Z29_Z30_Z31\0" |
| 1488 | /* 510 */ "B1\0" |
| 1489 | /* 513 */ "D30_D31_D0_D1\0" |
| 1490 | /* 527 */ "H1\0" |
| 1491 | /* 530 */ "P1\0" |
| 1492 | /* 533 */ "Q30_Q31_Q0_Q1\0" |
| 1493 | /* 547 */ "S1\0" |
| 1494 | /* 550 */ "W0_W1\0" |
| 1495 | /* 556 */ "X0_X1\0" |
| 1496 | /* 562 */ "Z30_Z31_Z0_Z1\0" |
| 1497 | /* 576 */ "B12\0" |
| 1498 | /* 580 */ "D9_D10_D11_D12\0" |
| 1499 | /* 595 */ "H12\0" |
| 1500 | /* 599 */ "P12\0" |
| 1501 | /* 603 */ "Q9_Q10_Q11_Q12\0" |
| 1502 | /* 618 */ "S12\0" |
| 1503 | /* 622 */ "W12\0" |
| 1504 | /* 626 */ "X12\0" |
| 1505 | /* 630 */ "Z9_Z10_Z11_Z12\0" |
| 1506 | /* 645 */ "B22\0" |
| 1507 | /* 649 */ "D19_D20_D21_D22\0" |
| 1508 | /* 665 */ "H22\0" |
| 1509 | /* 669 */ "Q19_Q20_Q21_Q22\0" |
| 1510 | /* 685 */ "S22\0" |
| 1511 | /* 689 */ "W22\0" |
| 1512 | /* 693 */ "X22\0" |
| 1513 | /* 697 */ "Z19_Z20_Z21_Z22\0" |
| 1514 | /* 713 */ "B2\0" |
| 1515 | /* 716 */ "D31_D0_D1_D2\0" |
| 1516 | /* 729 */ "H2\0" |
| 1517 | /* 732 */ "P2\0" |
| 1518 | /* 735 */ "Q31_Q0_Q1_Q2\0" |
| 1519 | /* 748 */ "S2\0" |
| 1520 | /* 751 */ "W2\0" |
| 1521 | /* 754 */ "X2\0" |
| 1522 | /* 757 */ "Z31_Z0_Z1_Z2\0" |
| 1523 | /* 770 */ "B13\0" |
| 1524 | /* 774 */ "D10_D11_D12_D13\0" |
| 1525 | /* 790 */ "H13\0" |
| 1526 | /* 794 */ "P13\0" |
| 1527 | /* 798 */ "Q10_Q11_Q12_Q13\0" |
| 1528 | /* 814 */ "S13\0" |
| 1529 | /* 818 */ "W12_W13\0" |
| 1530 | /* 826 */ "X6_X7_X8_X9_X10_X11_X12_X13\0" |
| 1531 | /* 854 */ "Z10_Z11_Z12_Z13\0" |
| 1532 | /* 870 */ "B23\0" |
| 1533 | /* 874 */ "D20_D21_D22_D23\0" |
| 1534 | /* 890 */ "H23\0" |
| 1535 | /* 894 */ "Q20_Q21_Q22_Q23\0" |
| 1536 | /* 910 */ "S23\0" |
| 1537 | /* 914 */ "W22_W23\0" |
| 1538 | /* 922 */ "X16_X17_X18_X19_X20_X21_X22_X23\0" |
| 1539 | /* 954 */ "Z20_Z21_Z22_Z23\0" |
| 1540 | /* 970 */ "B3\0" |
| 1541 | /* 973 */ "D0_D1_D2_D3\0" |
| 1542 | /* 985 */ "H3\0" |
| 1543 | /* 988 */ "P3\0" |
| 1544 | /* 991 */ "Q0_Q1_Q2_Q3\0" |
| 1545 | /* 1003 */ "S3\0" |
| 1546 | /* 1006 */ "W2_W3\0" |
| 1547 | /* 1012 */ "X2_X3\0" |
| 1548 | /* 1018 */ "Z0_Z1_Z2_Z3\0" |
| 1549 | /* 1030 */ "B14\0" |
| 1550 | /* 1034 */ "D11_D12_D13_D14\0" |
| 1551 | /* 1050 */ "H14\0" |
| 1552 | /* 1054 */ "P14\0" |
| 1553 | /* 1058 */ "Q11_Q12_Q13_Q14\0" |
| 1554 | /* 1074 */ "S14\0" |
| 1555 | /* 1078 */ "W14\0" |
| 1556 | /* 1082 */ "X14\0" |
| 1557 | /* 1086 */ "Z11_Z12_Z13_Z14\0" |
| 1558 | /* 1102 */ "B24\0" |
| 1559 | /* 1106 */ "D21_D22_D23_D24\0" |
| 1560 | /* 1122 */ "H24\0" |
| 1561 | /* 1126 */ "Q21_Q22_Q23_Q24\0" |
| 1562 | /* 1142 */ "S24\0" |
| 1563 | /* 1146 */ "W24\0" |
| 1564 | /* 1150 */ "X24\0" |
| 1565 | /* 1154 */ "Z21_Z22_Z23_Z24\0" |
| 1566 | /* 1170 */ "B4\0" |
| 1567 | /* 1173 */ "D1_D2_D3_D4\0" |
| 1568 | /* 1185 */ "H4\0" |
| 1569 | /* 1188 */ "P4\0" |
| 1570 | /* 1191 */ "Q1_Q2_Q3_Q4\0" |
| 1571 | /* 1203 */ "S4\0" |
| 1572 | /* 1206 */ "W4\0" |
| 1573 | /* 1209 */ "X4\0" |
| 1574 | /* 1212 */ "Z1_Z2_Z3_Z4\0" |
| 1575 | /* 1224 */ "B15\0" |
| 1576 | /* 1228 */ "D12_D13_D14_D15\0" |
| 1577 | /* 1244 */ "H15\0" |
| 1578 | /* 1248 */ "P15\0" |
| 1579 | /* 1252 */ "Q12_Q13_Q14_Q15\0" |
| 1580 | /* 1268 */ "S15\0" |
| 1581 | /* 1272 */ "W14_W15\0" |
| 1582 | /* 1280 */ "X8_X9_X10_X11_X12_X13_X14_X15\0" |
| 1583 | /* 1310 */ "Z12_Z13_Z14_Z15\0" |
| 1584 | /* 1326 */ "B25\0" |
| 1585 | /* 1330 */ "D22_D23_D24_D25\0" |
| 1586 | /* 1346 */ "H25\0" |
| 1587 | /* 1350 */ "Q22_Q23_Q24_Q25\0" |
| 1588 | /* 1366 */ "S25\0" |
| 1589 | /* 1370 */ "W24_W25\0" |
| 1590 | /* 1378 */ "X18_X19_X20_X21_X22_X23_X24_X25\0" |
| 1591 | /* 1410 */ "Z22_Z23_Z24_Z25\0" |
| 1592 | /* 1426 */ "B5\0" |
| 1593 | /* 1429 */ "D2_D3_D4_D5\0" |
| 1594 | /* 1441 */ "H5\0" |
| 1595 | /* 1444 */ "P5\0" |
| 1596 | /* 1447 */ "Q2_Q3_Q4_Q5\0" |
| 1597 | /* 1459 */ "S5\0" |
| 1598 | /* 1462 */ "W4_W5\0" |
| 1599 | /* 1468 */ "X4_X5\0" |
| 1600 | /* 1474 */ "Z2_Z3_Z4_Z5\0" |
| 1601 | /* 1486 */ "B16\0" |
| 1602 | /* 1490 */ "D13_D14_D15_D16\0" |
| 1603 | /* 1506 */ "H16\0" |
| 1604 | /* 1510 */ "Q13_Q14_Q15_Q16\0" |
| 1605 | /* 1526 */ "S16\0" |
| 1606 | /* 1530 */ "W16\0" |
| 1607 | /* 1534 */ "X16\0" |
| 1608 | /* 1538 */ "Z13_Z14_Z15_Z16\0" |
| 1609 | /* 1554 */ "B26\0" |
| 1610 | /* 1558 */ "D23_D24_D25_D26\0" |
| 1611 | /* 1574 */ "H26\0" |
| 1612 | /* 1578 */ "Q23_Q24_Q25_Q26\0" |
| 1613 | /* 1594 */ "S26\0" |
| 1614 | /* 1598 */ "W26\0" |
| 1615 | /* 1602 */ "X26\0" |
| 1616 | /* 1606 */ "Z23_Z24_Z25_Z26\0" |
| 1617 | /* 1622 */ "B6\0" |
| 1618 | /* 1625 */ "D3_D4_D5_D6\0" |
| 1619 | /* 1637 */ "H6\0" |
| 1620 | /* 1640 */ "P6\0" |
| 1621 | /* 1643 */ "Q3_Q4_Q5_Q6\0" |
| 1622 | /* 1655 */ "S6\0" |
| 1623 | /* 1658 */ "W6\0" |
| 1624 | /* 1661 */ "X6\0" |
| 1625 | /* 1664 */ "Z3_Z4_Z5_Z6\0" |
| 1626 | /* 1676 */ "B17\0" |
| 1627 | /* 1680 */ "D14_D15_D16_D17\0" |
| 1628 | /* 1696 */ "H17\0" |
| 1629 | /* 1700 */ "Q14_Q15_Q16_Q17\0" |
| 1630 | /* 1716 */ "S17\0" |
| 1631 | /* 1720 */ "W16_W17\0" |
| 1632 | /* 1728 */ "X10_X11_X12_X13_X14_X15_X16_X17\0" |
| 1633 | /* 1760 */ "Z14_Z15_Z16_Z17\0" |
| 1634 | /* 1776 */ "B27\0" |
| 1635 | /* 1780 */ "D24_D25_D26_D27\0" |
| 1636 | /* 1796 */ "H27\0" |
| 1637 | /* 1800 */ "Q24_Q25_Q26_Q27\0" |
| 1638 | /* 1816 */ "S27\0" |
| 1639 | /* 1820 */ "W26_W27\0" |
| 1640 | /* 1828 */ "X20_X21_X22_X23_X24_X25_X26_X27\0" |
| 1641 | /* 1860 */ "Z24_Z25_Z26_Z27\0" |
| 1642 | /* 1876 */ "B7\0" |
| 1643 | /* 1879 */ "D4_D5_D6_D7\0" |
| 1644 | /* 1891 */ "H7\0" |
| 1645 | /* 1894 */ "P7\0" |
| 1646 | /* 1897 */ "Q4_Q5_Q6_Q7\0" |
| 1647 | /* 1909 */ "S7\0" |
| 1648 | /* 1912 */ "W6_W7\0" |
| 1649 | /* 1918 */ "X0_X1_X2_X3_X4_X5_X6_X7\0" |
| 1650 | /* 1942 */ "Z4_Z5_Z6_Z7\0" |
| 1651 | /* 1954 */ "B18\0" |
| 1652 | /* 1958 */ "D15_D16_D17_D18\0" |
| 1653 | /* 1974 */ "H18\0" |
| 1654 | /* 1978 */ "Q15_Q16_Q17_Q18\0" |
| 1655 | /* 1994 */ "S18\0" |
| 1656 | /* 1998 */ "W18\0" |
| 1657 | /* 2002 */ "X18\0" |
| 1658 | /* 2006 */ "Z15_Z16_Z17_Z18\0" |
| 1659 | /* 2022 */ "B28\0" |
| 1660 | /* 2026 */ "D25_D26_D27_D28\0" |
| 1661 | /* 2042 */ "H28\0" |
| 1662 | /* 2046 */ "Q25_Q26_Q27_Q28\0" |
| 1663 | /* 2062 */ "S28\0" |
| 1664 | /* 2066 */ "W28\0" |
| 1665 | /* 2070 */ "X28\0" |
| 1666 | /* 2074 */ "Z25_Z26_Z27_Z28\0" |
| 1667 | /* 2090 */ "B8\0" |
| 1668 | /* 2093 */ "D5_D6_D7_D8\0" |
| 1669 | /* 2105 */ "H8\0" |
| 1670 | /* 2108 */ "P8\0" |
| 1671 | /* 2111 */ "Q5_Q6_Q7_Q8\0" |
| 1672 | /* 2123 */ "S8\0" |
| 1673 | /* 2126 */ "W8\0" |
| 1674 | /* 2129 */ "X8\0" |
| 1675 | /* 2132 */ "Z5_Z6_Z7_Z8\0" |
| 1676 | /* 2144 */ "B19\0" |
| 1677 | /* 2148 */ "D16_D17_D18_D19\0" |
| 1678 | /* 2164 */ "H19\0" |
| 1679 | /* 2168 */ "Q16_Q17_Q18_Q19\0" |
| 1680 | /* 2184 */ "S19\0" |
| 1681 | /* 2188 */ "W18_W19\0" |
| 1682 | /* 2196 */ "X12_X13_X14_X15_X16_X17_X18_X19\0" |
| 1683 | /* 2228 */ "Z16_Z17_Z18_Z19\0" |
| 1684 | /* 2244 */ "B29\0" |
| 1685 | /* 2248 */ "D26_D27_D28_D29\0" |
| 1686 | /* 2264 */ "H29\0" |
| 1687 | /* 2268 */ "Q26_Q27_Q28_Q29\0" |
| 1688 | /* 2284 */ "S29\0" |
| 1689 | /* 2288 */ "W28_W29\0" |
| 1690 | /* 2296 */ "Z26_Z27_Z28_Z29\0" |
| 1691 | /* 2312 */ "B9\0" |
| 1692 | /* 2315 */ "D6_D7_D8_D9\0" |
| 1693 | /* 2327 */ "H9\0" |
| 1694 | /* 2330 */ "P9\0" |
| 1695 | /* 2333 */ "Q6_Q7_Q8_Q9\0" |
| 1696 | /* 2345 */ "S9\0" |
| 1697 | /* 2348 */ "W8_W9\0" |
| 1698 | /* 2354 */ "X2_X3_X4_X5_X6_X7_X8_X9\0" |
| 1699 | /* 2378 */ "Z6_Z7_Z8_Z9\0" |
| 1700 | /* 2390 */ "VG\0" |
| 1701 | /* 2393 */ "Z10_HI\0" |
| 1702 | /* 2400 */ "Z20_HI\0" |
| 1703 | /* 2407 */ "Z30_HI\0" |
| 1704 | /* 2414 */ "Z0_HI\0" |
| 1705 | /* 2420 */ "Z11_HI\0" |
| 1706 | /* 2427 */ "Z21_HI\0" |
| 1707 | /* 2434 */ "Z31_HI\0" |
| 1708 | /* 2441 */ "Z1_HI\0" |
| 1709 | /* 2447 */ "Z12_HI\0" |
| 1710 | /* 2454 */ "Z22_HI\0" |
| 1711 | /* 2461 */ "Z2_HI\0" |
| 1712 | /* 2467 */ "Z13_HI\0" |
| 1713 | /* 2474 */ "Z23_HI\0" |
| 1714 | /* 2481 */ "Z3_HI\0" |
| 1715 | /* 2487 */ "Z14_HI\0" |
| 1716 | /* 2494 */ "Z24_HI\0" |
| 1717 | /* 2501 */ "Z4_HI\0" |
| 1718 | /* 2507 */ "Z15_HI\0" |
| 1719 | /* 2514 */ "Z25_HI\0" |
| 1720 | /* 2521 */ "Z5_HI\0" |
| 1721 | /* 2527 */ "Z16_HI\0" |
| 1722 | /* 2534 */ "Z26_HI\0" |
| 1723 | /* 2541 */ "Z6_HI\0" |
| 1724 | /* 2547 */ "Z17_HI\0" |
| 1725 | /* 2554 */ "Z27_HI\0" |
| 1726 | /* 2561 */ "Z7_HI\0" |
| 1727 | /* 2567 */ "Z18_HI\0" |
| 1728 | /* 2574 */ "Z28_HI\0" |
| 1729 | /* 2581 */ "Z8_HI\0" |
| 1730 | /* 2587 */ "Z19_HI\0" |
| 1731 | /* 2594 */ "Z29_HI\0" |
| 1732 | /* 2601 */ "Z9_HI\0" |
| 1733 | /* 2607 */ "X22_X23_X24_X25_X26_X27_X28_FP\0" |
| 1734 | /* 2638 */ "WSP\0" |
| 1735 | /* 2642 */ "FFR\0" |
| 1736 | /* 2646 */ "LR\0" |
| 1737 | /* 2649 */ "W30_WZR\0" |
| 1738 | /* 2657 */ "LR_XZR\0" |
| 1739 | /* 2664 */ "NZCV\0" |
| 1740 | }; |
| 1741 | #ifdef __GNUC__ |
| 1742 | #pragma GCC diagnostic pop |
| 1743 | #endif |
| 1744 | |
| 1745 | extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors |
| 1746 | { 3, 0, 0, 0, 0, 0 }, |
| 1747 | { 2642, 8, 8, 4, 26465, 0 }, |
| 1748 | { 2635, 1124, 1622, 5, 26465, 27 }, |
| 1749 | { 2646, 1124, 1255, 5, 26465, 27 }, |
| 1750 | { 2664, 8, 8, 4, 26465, 0 }, |
| 1751 | { 2639, 642, 8, 5, 26465, 27 }, |
| 1752 | { 2390, 8, 8, 4, 26465, 0 }, |
| 1753 | { 2638, 8, 1629, 4, 26002, 0 }, |
| 1754 | { 2653, 8, 672, 4, 10400, 0 }, |
| 1755 | { 2660, 1654, 1253, 5, 10400, 27 }, |
| 1756 | { 195, 8, 449, 4, 26033, 0 }, |
| 1757 | { 510, 8, 531, 4, 26033, 0 }, |
| 1758 | { 713, 8, 694, 4, 26033, 0 }, |
| 1759 | { 970, 8, 385, 4, 26033, 0 }, |
| 1760 | { 1170, 8, 385, 4, 26033, 0 }, |
| 1761 | { 1426, 8, 385, 4, 26033, 0 }, |
| 1762 | { 1622, 8, 385, 4, 26033, 0 }, |
| 1763 | { 1876, 8, 385, 4, 26033, 0 }, |
| 1764 | { 2090, 8, 385, 4, 26033, 0 }, |
| 1765 | { 2312, 8, 385, 4, 26033, 0 }, |
| 1766 | { 0, 8, 385, 4, 26033, 0 }, |
| 1767 | { 258, 8, 385, 4, 26033, 0 }, |
| 1768 | { 576, 8, 385, 4, 26033, 0 }, |
| 1769 | { 770, 8, 385, 4, 26033, 0 }, |
| 1770 | { 1030, 8, 385, 4, 26033, 0 }, |
| 1771 | { 1224, 8, 385, 4, 26033, 0 }, |
| 1772 | { 1486, 8, 385, 4, 26033, 0 }, |
| 1773 | { 1676, 8, 385, 4, 26033, 0 }, |
| 1774 | { 1954, 8, 385, 4, 26033, 0 }, |
| 1775 | { 2144, 8, 385, 4, 26033, 0 }, |
| 1776 | { 63, 8, 385, 4, 26033, 0 }, |
| 1777 | { 350, 8, 385, 4, 26033, 0 }, |
| 1778 | { 645, 8, 385, 4, 26033, 0 }, |
| 1779 | { 870, 8, 385, 4, 26033, 0 }, |
| 1780 | { 1102, 8, 385, 4, 26033, 0 }, |
| 1781 | { 1326, 8, 385, 4, 26033, 0 }, |
| 1782 | { 1554, 8, 385, 4, 26033, 0 }, |
| 1783 | { 1776, 8, 385, 4, 26033, 0 }, |
| 1784 | { 2022, 8, 385, 4, 26033, 0 }, |
| 1785 | { 2244, 8, 385, 4, 26033, 0 }, |
| 1786 | { 131, 8, 385, 4, 26033, 0 }, |
| 1787 | { 450, 8, 385, 4, 26033, 0 }, |
| 1788 | { 210, 1396, 452, 1, 25217, 3 }, |
| 1789 | { 524, 1396, 534, 1, 25217, 3 }, |
| 1790 | { 726, 1396, 697, 1, 25217, 3 }, |
| 1791 | { 982, 1396, 388, 1, 25217, 3 }, |
| 1792 | { 1182, 1396, 388, 1, 25217, 3 }, |
| 1793 | { 1438, 1396, 388, 1, 25217, 3 }, |
| 1794 | { 1634, 1396, 388, 1, 25217, 3 }, |
| 1795 | { 1888, 1396, 388, 1, 25217, 3 }, |
| 1796 | { 2102, 1396, 388, 1, 25217, 3 }, |
| 1797 | { 2324, 1396, 388, 1, 25217, 3 }, |
| 1798 | { 13, 1396, 388, 1, 25217, 3 }, |
| 1799 | { 272, 1396, 388, 1, 25217, 3 }, |
| 1800 | { 591, 1396, 388, 1, 25217, 3 }, |
| 1801 | { 786, 1396, 388, 1, 25217, 3 }, |
| 1802 | { 1046, 1396, 388, 1, 25217, 3 }, |
| 1803 | { 1240, 1396, 388, 1, 25217, 3 }, |
| 1804 | { 1502, 1396, 388, 1, 25217, 3 }, |
| 1805 | { 1692, 1396, 388, 1, 25217, 3 }, |
| 1806 | { 1970, 1396, 388, 1, 25217, 3 }, |
| 1807 | { 2160, 1396, 388, 1, 25217, 3 }, |
| 1808 | { 79, 1396, 388, 1, 25217, 3 }, |
| 1809 | { 366, 1396, 388, 1, 25217, 3 }, |
| 1810 | { 661, 1396, 388, 1, 25217, 3 }, |
| 1811 | { 886, 1396, 388, 1, 25217, 3 }, |
| 1812 | { 1118, 1396, 388, 1, 25217, 3 }, |
| 1813 | { 1342, 1396, 388, 1, 25217, 3 }, |
| 1814 | { 1570, 1396, 388, 1, 25217, 3 }, |
| 1815 | { 1792, 1396, 388, 1, 25217, 3 }, |
| 1816 | { 2038, 1396, 388, 1, 25217, 3 }, |
| 1817 | { 2260, 1396, 388, 1, 25217, 3 }, |
| 1818 | { 147, 1396, 388, 1, 25217, 3 }, |
| 1819 | { 466, 1396, 388, 1, 25217, 3 }, |
| 1820 | { 213, 1398, 450, 3, 22225, 3 }, |
| 1821 | { 527, 1398, 532, 3, 22225, 3 }, |
| 1822 | { 729, 1398, 695, 3, 22225, 3 }, |
| 1823 | { 985, 1398, 386, 3, 22225, 3 }, |
| 1824 | { 1185, 1398, 386, 3, 22225, 3 }, |
| 1825 | { 1441, 1398, 386, 3, 22225, 3 }, |
| 1826 | { 1637, 1398, 386, 3, 22225, 3 }, |
| 1827 | { 1891, 1398, 386, 3, 22225, 3 }, |
| 1828 | { 2105, 1398, 386, 3, 22225, 3 }, |
| 1829 | { 2327, 1398, 386, 3, 22225, 3 }, |
| 1830 | { 17, 1398, 386, 3, 22225, 3 }, |
| 1831 | { 276, 1398, 386, 3, 22225, 3 }, |
| 1832 | { 595, 1398, 386, 3, 22225, 3 }, |
| 1833 | { 790, 1398, 386, 3, 22225, 3 }, |
| 1834 | { 1050, 1398, 386, 3, 22225, 3 }, |
| 1835 | { 1244, 1398, 386, 3, 22225, 3 }, |
| 1836 | { 1506, 1398, 386, 3, 22225, 3 }, |
| 1837 | { 1696, 1398, 386, 3, 22225, 3 }, |
| 1838 | { 1974, 1398, 386, 3, 22225, 3 }, |
| 1839 | { 2164, 1398, 386, 3, 22225, 3 }, |
| 1840 | { 83, 1398, 386, 3, 22225, 3 }, |
| 1841 | { 370, 1398, 386, 3, 22225, 3 }, |
| 1842 | { 665, 1398, 386, 3, 22225, 3 }, |
| 1843 | { 890, 1398, 386, 3, 22225, 3 }, |
| 1844 | { 1122, 1398, 386, 3, 22225, 3 }, |
| 1845 | { 1346, 1398, 386, 3, 22225, 3 }, |
| 1846 | { 1574, 1398, 386, 3, 22225, 3 }, |
| 1847 | { 1796, 1398, 386, 3, 22225, 3 }, |
| 1848 | { 2042, 1398, 386, 3, 22225, 3 }, |
| 1849 | { 2264, 1398, 386, 3, 22225, 3 }, |
| 1850 | { 151, 1398, 386, 3, 22225, 3 }, |
| 1851 | { 470, 1398, 386, 3, 22225, 3 }, |
| 1852 | { 216, 8, 8, 4, 22225, 0 }, |
| 1853 | { 530, 8, 8, 4, 22225, 0 }, |
| 1854 | { 732, 8, 8, 4, 22225, 0 }, |
| 1855 | { 988, 8, 8, 4, 22225, 0 }, |
| 1856 | { 1188, 8, 8, 4, 22225, 0 }, |
| 1857 | { 1444, 8, 8, 4, 22225, 0 }, |
| 1858 | { 1640, 8, 8, 4, 22225, 0 }, |
| 1859 | { 1894, 8, 8, 4, 22225, 0 }, |
| 1860 | { 2108, 8, 8, 4, 22225, 0 }, |
| 1861 | { 2330, 8, 8, 4, 22225, 0 }, |
| 1862 | { 21, 8, 8, 4, 22225, 0 }, |
| 1863 | { 280, 8, 8, 4, 22225, 0 }, |
| 1864 | { 599, 8, 8, 4, 22225, 0 }, |
| 1865 | { 794, 8, 8, 4, 22225, 0 }, |
| 1866 | { 1054, 8, 8, 4, 22225, 0 }, |
| 1867 | { 1248, 8, 8, 4, 22225, 0 }, |
| 1868 | { 231, 1409, 482, 0, 20321, 3 }, |
| 1869 | { 544, 1409, 564, 0, 20321, 3 }, |
| 1870 | { 745, 1409, 727, 0, 20321, 3 }, |
| 1871 | { 1000, 1409, 418, 0, 20321, 3 }, |
| 1872 | { 1200, 1409, 418, 0, 20321, 3 }, |
| 1873 | { 1456, 1409, 418, 0, 20321, 3 }, |
| 1874 | { 1652, 1409, 418, 0, 20321, 3 }, |
| 1875 | { 1906, 1409, 418, 0, 20321, 3 }, |
| 1876 | { 2120, 1409, 418, 0, 20321, 3 }, |
| 1877 | { 2342, 1409, 418, 0, 20321, 3 }, |
| 1878 | { 34, 1409, 418, 0, 20321, 3 }, |
| 1879 | { 294, 1409, 418, 0, 20321, 3 }, |
| 1880 | { 614, 1409, 418, 0, 20321, 3 }, |
| 1881 | { 810, 1409, 418, 0, 20321, 3 }, |
| 1882 | { 1070, 1409, 418, 0, 20321, 3 }, |
| 1883 | { 1264, 1409, 418, 0, 20321, 3 }, |
| 1884 | { 1522, 1409, 418, 0, 20321, 3 }, |
| 1885 | { 1712, 1409, 418, 0, 20321, 3 }, |
| 1886 | { 1990, 1409, 418, 0, 20321, 3 }, |
| 1887 | { 2180, 1409, 418, 0, 20321, 3 }, |
| 1888 | { 99, 1409, 418, 0, 20321, 3 }, |
| 1889 | { 386, 1409, 418, 0, 20321, 3 }, |
| 1890 | { 681, 1409, 418, 0, 20321, 3 }, |
| 1891 | { 906, 1409, 418, 0, 20321, 3 }, |
| 1892 | { 1138, 1409, 418, 0, 20321, 3 }, |
| 1893 | { 1362, 1409, 418, 0, 20321, 3 }, |
| 1894 | { 1590, 1409, 418, 0, 20321, 3 }, |
| 1895 | { 1812, 1409, 418, 0, 20321, 3 }, |
| 1896 | { 2058, 1409, 418, 0, 20321, 3 }, |
| 1897 | { 2280, 1409, 418, 0, 20321, 3 }, |
| 1898 | { 167, 1409, 418, 0, 20321, 3 }, |
| 1899 | { 486, 1409, 418, 0, 20321, 3 }, |
| 1900 | { 234, 1397, 451, 2, 20257, 3 }, |
| 1901 | { 547, 1397, 533, 2, 20257, 3 }, |
| 1902 | { 748, 1397, 696, 2, 20257, 3 }, |
| 1903 | { 1003, 1397, 387, 2, 20257, 3 }, |
| 1904 | { 1203, 1397, 387, 2, 20257, 3 }, |
| 1905 | { 1459, 1397, 387, 2, 20257, 3 }, |
| 1906 | { 1655, 1397, 387, 2, 20257, 3 }, |
| 1907 | { 1909, 1397, 387, 2, 20257, 3 }, |
| 1908 | { 2123, 1397, 387, 2, 20257, 3 }, |
| 1909 | { 2345, 1397, 387, 2, 20257, 3 }, |
| 1910 | { 38, 1397, 387, 2, 20257, 3 }, |
| 1911 | { 298, 1397, 387, 2, 20257, 3 }, |
| 1912 | { 618, 1397, 387, 2, 20257, 3 }, |
| 1913 | { 814, 1397, 387, 2, 20257, 3 }, |
| 1914 | { 1074, 1397, 387, 2, 20257, 3 }, |
| 1915 | { 1268, 1397, 387, 2, 20257, 3 }, |
| 1916 | { 1526, 1397, 387, 2, 20257, 3 }, |
| 1917 | { 1716, 1397, 387, 2, 20257, 3 }, |
| 1918 | { 1994, 1397, 387, 2, 20257, 3 }, |
| 1919 | { 2184, 1397, 387, 2, 20257, 3 }, |
| 1920 | { 103, 1397, 387, 2, 20257, 3 }, |
| 1921 | { 390, 1397, 387, 2, 20257, 3 }, |
| 1922 | { 685, 1397, 387, 2, 20257, 3 }, |
| 1923 | { 910, 1397, 387, 2, 20257, 3 }, |
| 1924 | { 1142, 1397, 387, 2, 20257, 3 }, |
| 1925 | { 1366, 1397, 387, 2, 20257, 3 }, |
| 1926 | { 1594, 1397, 387, 2, 20257, 3 }, |
| 1927 | { 1816, 1397, 387, 2, 20257, 3 }, |
| 1928 | { 2062, 1397, 387, 2, 20257, 3 }, |
| 1929 | { 2284, 1397, 387, 2, 20257, 3 }, |
| 1930 | { 171, 1397, 387, 2, 20257, 3 }, |
| 1931 | { 490, 1397, 387, 2, 20257, 3 }, |
| 1932 | { 237, 8, 1608, 4, 20289, 0 }, |
| 1933 | { 553, 8, 1603, 4, 20289, 0 }, |
| 1934 | { 751, 8, 628, 4, 20289, 0 }, |
| 1935 | { 1009, 8, 622, 4, 20289, 0 }, |
| 1936 | { 1206, 8, 227, 4, 20289, 0 }, |
| 1937 | { 1465, 8, 220, 4, 20289, 0 }, |
| 1938 | { 1658, 8, 101, 4, 20289, 0 }, |
| 1939 | { 1915, 8, 93, 4, 20289, 0 }, |
| 1940 | { 2126, 8, 93, 4, 20289, 0 }, |
| 1941 | { 2351, 8, 85, 4, 20289, 0 }, |
| 1942 | { 42, 8, 85, 4, 20289, 0 }, |
| 1943 | { 306, 8, 77, 4, 20289, 0 }, |
| 1944 | { 622, 8, 77, 4, 20289, 0 }, |
| 1945 | { 822, 8, 69, 4, 20289, 0 }, |
| 1946 | { 1078, 8, 69, 4, 20289, 0 }, |
| 1947 | { 1276, 8, 61, 4, 20289, 0 }, |
| 1948 | { 1530, 8, 61, 4, 20289, 0 }, |
| 1949 | { 1724, 8, 53, 4, 20289, 0 }, |
| 1950 | { 1998, 8, 53, 4, 20289, 0 }, |
| 1951 | { 2192, 8, 45, 4, 20289, 0 }, |
| 1952 | { 107, 8, 45, 4, 20289, 0 }, |
| 1953 | { 398, 8, 37, 4, 20289, 0 }, |
| 1954 | { 689, 8, 171, 4, 20289, 0 }, |
| 1955 | { 918, 8, 163, 4, 20289, 0 }, |
| 1956 | { 1146, 8, 251, 4, 20289, 0 }, |
| 1957 | { 1374, 8, 244, 4, 20289, 0 }, |
| 1958 | { 1598, 8, 658, 4, 20289, 0 }, |
| 1959 | { 1824, 8, 652, 4, 20289, 0 }, |
| 1960 | { 2066, 8, 1593, 4, 20289, 0 }, |
| 1961 | { 2292, 8, 1598, 4, 20113, 0 }, |
| 1962 | { 175, 8, 676, 4, 20113, 0 }, |
| 1963 | { 240, 1591, 1619, 5, 20225, 27 }, |
| 1964 | { 559, 1591, 1616, 5, 20225, 27 }, |
| 1965 | { 754, 1591, 638, 5, 20225, 27 }, |
| 1966 | { 1015, 1591, 634, 5, 20225, 27 }, |
| 1967 | { 1209, 1591, 239, 5, 20225, 27 }, |
| 1968 | { 1471, 1591, 234, 5, 20225, 27 }, |
| 1969 | { 1661, 1591, 157, 5, 20225, 27 }, |
| 1970 | { 1939, 1591, 151, 5, 20225, 27 }, |
| 1971 | { 2129, 1591, 151, 5, 20225, 27 }, |
| 1972 | { 2375, 1591, 145, 5, 20225, 27 }, |
| 1973 | { 46, 1591, 145, 5, 20225, 27 }, |
| 1974 | { 332, 1591, 139, 5, 20225, 27 }, |
| 1975 | { 626, 1591, 139, 5, 20225, 27 }, |
| 1976 | { 850, 1591, 133, 5, 20225, 27 }, |
| 1977 | { 1082, 1591, 133, 5, 20225, 27 }, |
| 1978 | { 1306, 1591, 127, 5, 20225, 27 }, |
| 1979 | { 1534, 1591, 127, 5, 20225, 27 }, |
| 1980 | { 1756, 1591, 121, 5, 20225, 27 }, |
| 1981 | { 2002, 1591, 121, 5, 20225, 27 }, |
| 1982 | { 2224, 1591, 115, 5, 20225, 27 }, |
| 1983 | { 111, 1591, 115, 5, 20225, 27 }, |
| 1984 | { 430, 1591, 109, 5, 20225, 27 }, |
| 1985 | { 693, 1591, 185, 5, 20225, 27 }, |
| 1986 | { 950, 1591, 179, 5, 20225, 27 }, |
| 1987 | { 1150, 1591, 263, 5, 20225, 27 }, |
| 1988 | { 1406, 1591, 258, 5, 20225, 27 }, |
| 1989 | { 1602, 1591, 668, 5, 20225, 27 }, |
| 1990 | { 1856, 1591, 664, 5, 20225, 27 }, |
| 1991 | { 2070, 1591, 1613, 5, 20225, 27 }, |
| 1992 | { 255, 1126, 503, 10, 12865, 35 }, |
| 1993 | { 573, 1126, 585, 10, 12865, 35 }, |
| 1994 | { 767, 1126, 748, 10, 12865, 35 }, |
| 1995 | { 1027, 1126, 439, 10, 12865, 35 }, |
| 1996 | { 1221, 1126, 439, 10, 12865, 35 }, |
| 1997 | { 1483, 1126, 439, 10, 12865, 35 }, |
| 1998 | { 1673, 1126, 439, 10, 12865, 35 }, |
| 1999 | { 1951, 1126, 439, 10, 12865, 35 }, |
| 2000 | { 2141, 1126, 439, 10, 12865, 35 }, |
| 2001 | { 2387, 1126, 439, 10, 12865, 35 }, |
| 2002 | { 59, 1126, 439, 10, 12865, 35 }, |
| 2003 | { 346, 1126, 439, 10, 12865, 35 }, |
| 2004 | { 641, 1126, 439, 10, 12865, 35 }, |
| 2005 | { 866, 1126, 439, 10, 12865, 35 }, |
| 2006 | { 1098, 1126, 439, 10, 12865, 35 }, |
| 2007 | { 1322, 1126, 439, 10, 12865, 35 }, |
| 2008 | { 1550, 1126, 439, 10, 12865, 35 }, |
| 2009 | { 1772, 1126, 439, 10, 12865, 35 }, |
| 2010 | { 2018, 1126, 439, 10, 12865, 35 }, |
| 2011 | { 2240, 1126, 439, 10, 12865, 35 }, |
| 2012 | { 127, 1126, 439, 10, 12865, 35 }, |
| 2013 | { 446, 1126, 439, 10, 12865, 35 }, |
| 2014 | { 709, 1126, 439, 10, 12865, 35 }, |
| 2015 | { 966, 1126, 439, 10, 12865, 35 }, |
| 2016 | { 1166, 1126, 439, 10, 12865, 35 }, |
| 2017 | { 1422, 1126, 439, 10, 12865, 35 }, |
| 2018 | { 1618, 1126, 439, 10, 12865, 35 }, |
| 2019 | { 1872, 1126, 439, 10, 12865, 35 }, |
| 2020 | { 2086, 1126, 439, 10, 12865, 35 }, |
| 2021 | { 2308, 1126, 439, 10, 12865, 35 }, |
| 2022 | { 191, 1126, 439, 10, 12865, 35 }, |
| 2023 | { 506, 1126, 439, 10, 12865, 35 }, |
| 2024 | { 2414, 8, 502, 4, 20193, 0 }, |
| 2025 | { 2441, 8, 584, 4, 20193, 0 }, |
| 2026 | { 2461, 8, 747, 4, 20193, 0 }, |
| 2027 | { 2481, 8, 438, 4, 20193, 0 }, |
| 2028 | { 2501, 8, 438, 4, 20193, 0 }, |
| 2029 | { 2521, 8, 438, 4, 20193, 0 }, |
| 2030 | { 2541, 8, 438, 4, 20193, 0 }, |
| 2031 | { 2561, 8, 438, 4, 20193, 0 }, |
| 2032 | { 2581, 8, 438, 4, 20193, 0 }, |
| 2033 | { 2601, 8, 438, 4, 20193, 0 }, |
| 2034 | { 2393, 8, 438, 4, 20193, 0 }, |
| 2035 | { 2420, 8, 438, 4, 20193, 0 }, |
| 2036 | { 2447, 8, 438, 4, 20193, 0 }, |
| 2037 | { 2467, 8, 438, 4, 20193, 0 }, |
| 2038 | { 2487, 8, 438, 4, 20193, 0 }, |
| 2039 | { 2507, 8, 438, 4, 20193, 0 }, |
| 2040 | { 2527, 8, 438, 4, 20193, 0 }, |
| 2041 | { 2547, 8, 438, 4, 20193, 0 }, |
| 2042 | { 2567, 8, 438, 4, 20193, 0 }, |
| 2043 | { 2587, 8, 438, 4, 20193, 0 }, |
| 2044 | { 2400, 8, 438, 4, 20193, 0 }, |
| 2045 | { 2427, 8, 438, 4, 20193, 0 }, |
| 2046 | { 2454, 8, 438, 4, 20193, 0 }, |
| 2047 | { 2474, 8, 438, 4, 20193, 0 }, |
| 2048 | { 2494, 8, 438, 4, 20193, 0 }, |
| 2049 | { 2514, 8, 438, 4, 20193, 0 }, |
| 2050 | { 2534, 8, 438, 4, 20193, 0 }, |
| 2051 | { 2554, 8, 438, 4, 20193, 0 }, |
| 2052 | { 2574, 8, 438, 4, 20193, 0 }, |
| 2053 | { 2594, 8, 438, 4, 20193, 0 }, |
| 2054 | { 2407, 8, 438, 4, 20193, 0 }, |
| 2055 | { 2434, 8, 438, 4, 20193, 0 }, |
| 2056 | { 521, 1400, 595, 17, 6113, 61 }, |
| 2057 | { 723, 1400, 769, 17, 6113, 61 }, |
| 2058 | { 979, 1400, 513, 17, 6113, 61 }, |
| 2059 | { 1179, 1400, 513, 17, 6113, 61 }, |
| 2060 | { 1435, 1400, 513, 17, 6113, 61 }, |
| 2061 | { 1631, 1400, 513, 17, 6113, 61 }, |
| 2062 | { 1885, 1400, 513, 17, 6113, 61 }, |
| 2063 | { 2099, 1400, 513, 17, 6113, 61 }, |
| 2064 | { 2321, 1400, 513, 17, 6113, 61 }, |
| 2065 | { 10, 1400, 513, 17, 6113, 61 }, |
| 2066 | { 268, 1400, 513, 17, 6113, 61 }, |
| 2067 | { 587, 1400, 513, 17, 6113, 61 }, |
| 2068 | { 782, 1400, 513, 17, 6113, 61 }, |
| 2069 | { 1042, 1400, 513, 17, 6113, 61 }, |
| 2070 | { 1236, 1400, 513, 17, 6113, 61 }, |
| 2071 | { 1498, 1400, 513, 17, 6113, 61 }, |
| 2072 | { 1688, 1400, 513, 17, 6113, 61 }, |
| 2073 | { 1966, 1400, 513, 17, 6113, 61 }, |
| 2074 | { 2156, 1400, 513, 17, 6113, 61 }, |
| 2075 | { 75, 1400, 513, 17, 6113, 61 }, |
| 2076 | { 362, 1400, 513, 17, 6113, 61 }, |
| 2077 | { 657, 1400, 513, 17, 6113, 61 }, |
| 2078 | { 882, 1400, 513, 17, 6113, 61 }, |
| 2079 | { 1114, 1400, 513, 17, 6113, 61 }, |
| 2080 | { 1338, 1400, 513, 17, 6113, 61 }, |
| 2081 | { 1566, 1400, 513, 17, 6113, 61 }, |
| 2082 | { 1788, 1400, 513, 17, 6113, 61 }, |
| 2083 | { 2034, 1400, 513, 17, 6113, 61 }, |
| 2084 | { 2256, 1400, 513, 17, 6113, 61 }, |
| 2085 | { 143, 1400, 513, 17, 6113, 61 }, |
| 2086 | { 462, 1400, 513, 17, 6113, 61 }, |
| 2087 | { 206, 1391, 513, 17, 12592, 2 }, |
| 2088 | { 973, 1532, 1121, 41, 513, 68 }, |
| 2089 | { 1173, 1532, 1121, 41, 513, 68 }, |
| 2090 | { 1429, 1532, 1121, 41, 513, 68 }, |
| 2091 | { 1625, 1532, 1121, 41, 513, 68 }, |
| 2092 | { 1879, 1532, 1121, 41, 513, 68 }, |
| 2093 | { 2093, 1532, 1121, 41, 513, 68 }, |
| 2094 | { 2315, 1532, 1121, 41, 513, 68 }, |
| 2095 | { 4, 1532, 1121, 41, 513, 68 }, |
| 2096 | { 262, 1532, 1121, 41, 513, 68 }, |
| 2097 | { 580, 1532, 1121, 41, 513, 68 }, |
| 2098 | { 774, 1532, 1121, 41, 513, 68 }, |
| 2099 | { 1034, 1532, 1121, 41, 513, 68 }, |
| 2100 | { 1228, 1532, 1121, 41, 513, 68 }, |
| 2101 | { 1490, 1532, 1121, 41, 513, 68 }, |
| 2102 | { 1680, 1532, 1121, 41, 513, 68 }, |
| 2103 | { 1958, 1532, 1121, 41, 513, 68 }, |
| 2104 | { 2148, 1532, 1121, 41, 513, 68 }, |
| 2105 | { 67, 1532, 1121, 41, 513, 68 }, |
| 2106 | { 354, 1532, 1121, 41, 513, 68 }, |
| 2107 | { 649, 1532, 1121, 41, 513, 68 }, |
| 2108 | { 874, 1532, 1121, 41, 513, 68 }, |
| 2109 | { 1106, 1532, 1121, 41, 513, 68 }, |
| 2110 | { 1330, 1532, 1121, 41, 513, 68 }, |
| 2111 | { 1558, 1532, 1121, 41, 513, 68 }, |
| 2112 | { 1780, 1532, 1121, 41, 513, 68 }, |
| 2113 | { 2026, 1532, 1121, 41, 513, 68 }, |
| 2114 | { 2248, 1532, 1121, 41, 513, 68 }, |
| 2115 | { 135, 1532, 1121, 41, 513, 68 }, |
| 2116 | { 454, 1532, 1121, 41, 513, 68 }, |
| 2117 | { 198, 1554, 1121, 41, 3056, 73 }, |
| 2118 | { 513, 1367, 1121, 41, 4288, 59 }, |
| 2119 | { 716, 1510, 1121, 41, 10880, 5 }, |
| 2120 | { 720, 298, 795, 26, 3457, 74 }, |
| 2121 | { 976, 298, 613, 26, 3457, 74 }, |
| 2122 | { 1176, 298, 613, 26, 3457, 74 }, |
| 2123 | { 1432, 298, 613, 26, 3457, 74 }, |
| 2124 | { 1628, 298, 613, 26, 3457, 74 }, |
| 2125 | { 1882, 298, 613, 26, 3457, 74 }, |
| 2126 | { 2096, 298, 613, 26, 3457, 74 }, |
| 2127 | { 2318, 298, 613, 26, 3457, 74 }, |
| 2128 | { 7, 298, 613, 26, 3457, 74 }, |
| 2129 | { 265, 298, 613, 26, 3457, 74 }, |
| 2130 | { 583, 298, 613, 26, 3457, 74 }, |
| 2131 | { 778, 298, 613, 26, 3457, 74 }, |
| 2132 | { 1038, 298, 613, 26, 3457, 74 }, |
| 2133 | { 1232, 298, 613, 26, 3457, 74 }, |
| 2134 | { 1494, 298, 613, 26, 3457, 74 }, |
| 2135 | { 1684, 298, 613, 26, 3457, 74 }, |
| 2136 | { 1962, 298, 613, 26, 3457, 74 }, |
| 2137 | { 2152, 298, 613, 26, 3457, 74 }, |
| 2138 | { 71, 298, 613, 26, 3457, 74 }, |
| 2139 | { 358, 298, 613, 26, 3457, 74 }, |
| 2140 | { 653, 298, 613, 26, 3457, 74 }, |
| 2141 | { 878, 298, 613, 26, 3457, 74 }, |
| 2142 | { 1110, 298, 613, 26, 3457, 74 }, |
| 2143 | { 1334, 298, 613, 26, 3457, 74 }, |
| 2144 | { 1562, 298, 613, 26, 3457, 74 }, |
| 2145 | { 1784, 298, 613, 26, 3457, 74 }, |
| 2146 | { 2030, 298, 613, 26, 3457, 74 }, |
| 2147 | { 2252, 298, 613, 26, 3457, 74 }, |
| 2148 | { 139, 298, 613, 26, 3457, 74 }, |
| 2149 | { 458, 298, 613, 26, 3457, 74 }, |
| 2150 | { 202, 313, 613, 26, 4512, 64 }, |
| 2151 | { 517, 1578, 613, 26, 12128, 10 }, |
| 2152 | { 541, 1133, 601, 63, 5345, 80 }, |
| 2153 | { 742, 1133, 775, 63, 5345, 80 }, |
| 2154 | { 997, 1133, 519, 63, 5345, 80 }, |
| 2155 | { 1197, 1133, 519, 63, 5345, 80 }, |
| 2156 | { 1453, 1133, 519, 63, 5345, 80 }, |
| 2157 | { 1649, 1133, 519, 63, 5345, 80 }, |
| 2158 | { 1903, 1133, 519, 63, 5345, 80 }, |
| 2159 | { 2117, 1133, 519, 63, 5345, 80 }, |
| 2160 | { 2339, 1133, 519, 63, 5345, 80 }, |
| 2161 | { 31, 1133, 519, 63, 5345, 80 }, |
| 2162 | { 290, 1133, 519, 63, 5345, 80 }, |
| 2163 | { 610, 1133, 519, 63, 5345, 80 }, |
| 2164 | { 806, 1133, 519, 63, 5345, 80 }, |
| 2165 | { 1066, 1133, 519, 63, 5345, 80 }, |
| 2166 | { 1260, 1133, 519, 63, 5345, 80 }, |
| 2167 | { 1518, 1133, 519, 63, 5345, 80 }, |
| 2168 | { 1708, 1133, 519, 63, 5345, 80 }, |
| 2169 | { 1986, 1133, 519, 63, 5345, 80 }, |
| 2170 | { 2176, 1133, 519, 63, 5345, 80 }, |
| 2171 | { 95, 1133, 519, 63, 5345, 80 }, |
| 2172 | { 382, 1133, 519, 63, 5345, 80 }, |
| 2173 | { 677, 1133, 519, 63, 5345, 80 }, |
| 2174 | { 902, 1133, 519, 63, 5345, 80 }, |
| 2175 | { 1134, 1133, 519, 63, 5345, 80 }, |
| 2176 | { 1358, 1133, 519, 63, 5345, 80 }, |
| 2177 | { 1586, 1133, 519, 63, 5345, 80 }, |
| 2178 | { 1808, 1133, 519, 63, 5345, 80 }, |
| 2179 | { 2054, 1133, 519, 63, 5345, 80 }, |
| 2180 | { 2276, 1133, 519, 63, 5345, 80 }, |
| 2181 | { 163, 1133, 519, 63, 5345, 80 }, |
| 2182 | { 482, 1133, 519, 63, 5345, 80 }, |
| 2183 | { 227, 1235, 519, 63, 12592, 14 }, |
| 2184 | { 991, 1446, 1122, 96, 433, 87 }, |
| 2185 | { 1191, 1446, 1122, 96, 433, 87 }, |
| 2186 | { 1447, 1446, 1122, 96, 433, 87 }, |
| 2187 | { 1643, 1446, 1122, 96, 433, 87 }, |
| 2188 | { 1897, 1446, 1122, 96, 433, 87 }, |
| 2189 | { 2111, 1446, 1122, 96, 433, 87 }, |
| 2190 | { 2333, 1446, 1122, 96, 433, 87 }, |
| 2191 | { 25, 1446, 1122, 96, 433, 87 }, |
| 2192 | { 284, 1446, 1122, 96, 433, 87 }, |
| 2193 | { 603, 1446, 1122, 96, 433, 87 }, |
| 2194 | { 798, 1446, 1122, 96, 433, 87 }, |
| 2195 | { 1058, 1446, 1122, 96, 433, 87 }, |
| 2196 | { 1252, 1446, 1122, 96, 433, 87 }, |
| 2197 | { 1510, 1446, 1122, 96, 433, 87 }, |
| 2198 | { 1700, 1446, 1122, 96, 433, 87 }, |
| 2199 | { 1978, 1446, 1122, 96, 433, 87 }, |
| 2200 | { 2168, 1446, 1122, 96, 433, 87 }, |
| 2201 | { 87, 1446, 1122, 96, 433, 87 }, |
| 2202 | { 374, 1446, 1122, 96, 433, 87 }, |
| 2203 | { 669, 1446, 1122, 96, 433, 87 }, |
| 2204 | { 894, 1446, 1122, 96, 433, 87 }, |
| 2205 | { 1126, 1446, 1122, 96, 433, 87 }, |
| 2206 | { 1350, 1446, 1122, 96, 433, 87 }, |
| 2207 | { 1578, 1446, 1122, 96, 433, 87 }, |
| 2208 | { 1800, 1446, 1122, 96, 433, 87 }, |
| 2209 | { 2046, 1446, 1122, 96, 433, 87 }, |
| 2210 | { 2268, 1446, 1122, 96, 433, 87 }, |
| 2211 | { 155, 1446, 1122, 96, 433, 87 }, |
| 2212 | { 474, 1446, 1122, 96, 433, 87 }, |
| 2213 | { 219, 1478, 1122, 96, 3056, 92 }, |
| 2214 | { 533, 1335, 1122, 96, 4288, 78 }, |
| 2215 | { 735, 1414, 1122, 96, 10880, 17 }, |
| 2216 | { 739, 1272, 798, 75, 3393, 93 }, |
| 2217 | { 994, 1272, 616, 75, 3393, 93 }, |
| 2218 | { 1194, 1272, 616, 75, 3393, 93 }, |
| 2219 | { 1450, 1272, 616, 75, 3393, 93 }, |
| 2220 | { 1646, 1272, 616, 75, 3393, 93 }, |
| 2221 | { 1900, 1272, 616, 75, 3393, 93 }, |
| 2222 | { 2114, 1272, 616, 75, 3393, 93 }, |
| 2223 | { 2336, 1272, 616, 75, 3393, 93 }, |
| 2224 | { 28, 1272, 616, 75, 3393, 93 }, |
| 2225 | { 287, 1272, 616, 75, 3393, 93 }, |
| 2226 | { 606, 1272, 616, 75, 3393, 93 }, |
| 2227 | { 802, 1272, 616, 75, 3393, 93 }, |
| 2228 | { 1062, 1272, 616, 75, 3393, 93 }, |
| 2229 | { 1256, 1272, 616, 75, 3393, 93 }, |
| 2230 | { 1514, 1272, 616, 75, 3393, 93 }, |
| 2231 | { 1704, 1272, 616, 75, 3393, 93 }, |
| 2232 | { 1982, 1272, 616, 75, 3393, 93 }, |
| 2233 | { 2172, 1272, 616, 75, 3393, 93 }, |
| 2234 | { 91, 1272, 616, 75, 3393, 93 }, |
| 2235 | { 378, 1272, 616, 75, 3393, 93 }, |
| 2236 | { 673, 1272, 616, 75, 3393, 93 }, |
| 2237 | { 898, 1272, 616, 75, 3393, 93 }, |
| 2238 | { 1130, 1272, 616, 75, 3393, 93 }, |
| 2239 | { 1354, 1272, 616, 75, 3393, 93 }, |
| 2240 | { 1582, 1272, 616, 75, 3393, 93 }, |
| 2241 | { 1804, 1272, 616, 75, 3393, 93 }, |
| 2242 | { 2050, 1272, 616, 75, 3393, 93 }, |
| 2243 | { 2272, 1272, 616, 75, 3393, 93 }, |
| 2244 | { 159, 1272, 616, 75, 3393, 93 }, |
| 2245 | { 478, 1272, 616, 75, 3393, 93 }, |
| 2246 | { 223, 1293, 616, 75, 4512, 83 }, |
| 2247 | { 537, 1314, 616, 75, 12128, 22 }, |
| 2248 | { 2607, 1906, 8, 128, 144, 106 }, |
| 2249 | { 1918, 1881, 8, 128, 2, 97 }, |
| 2250 | { 2354, 1856, 8, 128, 2, 97 }, |
| 2251 | { 310, 1831, 8, 128, 2, 97 }, |
| 2252 | { 826, 1806, 8, 128, 2, 97 }, |
| 2253 | { 1280, 1781, 8, 128, 2, 97 }, |
| 2254 | { 1728, 1756, 8, 128, 2, 97 }, |
| 2255 | { 2196, 1731, 8, 128, 2, 97 }, |
| 2256 | { 402, 1706, 8, 128, 2, 97 }, |
| 2257 | { 922, 1681, 8, 128, 2, 97 }, |
| 2258 | { 1378, 1656, 8, 128, 2, 97 }, |
| 2259 | { 1828, 1631, 8, 128, 2, 97 }, |
| 2260 | { 2649, 1259, 674, 7, 10304, 32 }, |
| 2261 | { 550, 337, 1605, 7, 5298, 32 }, |
| 2262 | { 1006, 340, 624, 7, 5298, 32 }, |
| 2263 | { 1462, 343, 222, 7, 5298, 32 }, |
| 2264 | { 1912, 346, 39, 7, 5298, 32 }, |
| 2265 | { 2348, 349, 39, 7, 5298, 32 }, |
| 2266 | { 302, 352, 39, 7, 5298, 32 }, |
| 2267 | { 818, 355, 39, 7, 5298, 32 }, |
| 2268 | { 1272, 358, 39, 7, 5298, 32 }, |
| 2269 | { 1720, 361, 39, 7, 5298, 32 }, |
| 2270 | { 2188, 364, 39, 7, 5298, 32 }, |
| 2271 | { 394, 367, 39, 7, 5298, 32 }, |
| 2272 | { 914, 370, 165, 7, 5298, 32 }, |
| 2273 | { 1370, 373, 246, 7, 5298, 32 }, |
| 2274 | { 1820, 376, 654, 7, 5298, 32 }, |
| 2275 | { 2288, 379, 1595, 7, 12961, 29 }, |
| 2276 | { 2657, 1247, 8, 153, 10353, 115 }, |
| 2277 | { 2631, 1145, 1596, 153, 12912, 26 }, |
| 2278 | { 556, 1229, 1596, 153, 5250, 115 }, |
| 2279 | { 1012, 1223, 625, 153, 5250, 115 }, |
| 2280 | { 1468, 1217, 223, 153, 5250, 115 }, |
| 2281 | { 1936, 1211, 40, 153, 5250, 115 }, |
| 2282 | { 2372, 1205, 40, 153, 5250, 115 }, |
| 2283 | { 328, 1199, 40, 153, 5250, 115 }, |
| 2284 | { 846, 1193, 40, 153, 5250, 115 }, |
| 2285 | { 1302, 1187, 40, 153, 5250, 115 }, |
| 2286 | { 1752, 1181, 40, 153, 5250, 115 }, |
| 2287 | { 2220, 1175, 40, 153, 5250, 115 }, |
| 2288 | { 426, 1169, 40, 153, 5250, 115 }, |
| 2289 | { 946, 1163, 166, 153, 5250, 115 }, |
| 2290 | { 1402, 1157, 247, 153, 5250, 115 }, |
| 2291 | { 1852, 1151, 655, 153, 5250, 115 }, |
| 2292 | { 570, 813, 607, 159, 4689, 118 }, |
| 2293 | { 764, 813, 781, 159, 4689, 118 }, |
| 2294 | { 1024, 813, 525, 159, 4689, 118 }, |
| 2295 | { 1218, 813, 525, 159, 4689, 118 }, |
| 2296 | { 1480, 813, 525, 159, 4689, 118 }, |
| 2297 | { 1670, 813, 525, 159, 4689, 118 }, |
| 2298 | { 1948, 813, 525, 159, 4689, 118 }, |
| 2299 | { 2138, 813, 525, 159, 4689, 118 }, |
| 2300 | { 2384, 813, 525, 159, 4689, 118 }, |
| 2301 | { 56, 813, 525, 159, 4689, 118 }, |
| 2302 | { 342, 813, 525, 159, 4689, 118 }, |
| 2303 | { 637, 813, 525, 159, 4689, 118 }, |
| 2304 | { 862, 813, 525, 159, 4689, 118 }, |
| 2305 | { 1094, 813, 525, 159, 4689, 118 }, |
| 2306 | { 1318, 813, 525, 159, 4689, 118 }, |
| 2307 | { 1546, 813, 525, 159, 4689, 118 }, |
| 2308 | { 1768, 813, 525, 159, 4689, 118 }, |
| 2309 | { 2014, 813, 525, 159, 4689, 118 }, |
| 2310 | { 2236, 813, 525, 159, 4689, 118 }, |
| 2311 | { 123, 813, 525, 159, 4689, 118 }, |
| 2312 | { 442, 813, 525, 159, 4689, 118 }, |
| 2313 | { 705, 813, 525, 159, 4689, 118 }, |
| 2314 | { 962, 813, 525, 159, 4689, 118 }, |
| 2315 | { 1162, 813, 525, 159, 4689, 118 }, |
| 2316 | { 1418, 813, 525, 159, 4689, 118 }, |
| 2317 | { 1614, 813, 525, 159, 4689, 118 }, |
| 2318 | { 1868, 813, 525, 159, 4689, 118 }, |
| 2319 | { 2082, 813, 525, 159, 4689, 118 }, |
| 2320 | { 2304, 813, 525, 159, 4689, 118 }, |
| 2321 | { 187, 813, 525, 159, 4689, 118 }, |
| 2322 | { 502, 813, 525, 159, 4689, 118 }, |
| 2323 | { 251, 830, 525, 159, 12640, 38 }, |
| 2324 | { 1018, 1029, 8, 206, 289, 139 }, |
| 2325 | { 1212, 1029, 8, 206, 289, 139 }, |
| 2326 | { 1474, 1029, 8, 206, 289, 139 }, |
| 2327 | { 1664, 1029, 8, 206, 289, 139 }, |
| 2328 | { 1942, 1029, 8, 206, 289, 139 }, |
| 2329 | { 2132, 1029, 8, 206, 289, 139 }, |
| 2330 | { 2378, 1029, 8, 206, 289, 139 }, |
| 2331 | { 50, 1029, 8, 206, 289, 139 }, |
| 2332 | { 336, 1029, 8, 206, 289, 139 }, |
| 2333 | { 630, 1029, 8, 206, 289, 139 }, |
| 2334 | { 854, 1029, 8, 206, 289, 139 }, |
| 2335 | { 1086, 1029, 8, 206, 289, 139 }, |
| 2336 | { 1310, 1029, 8, 206, 289, 139 }, |
| 2337 | { 1538, 1029, 8, 206, 289, 139 }, |
| 2338 | { 1760, 1029, 8, 206, 289, 139 }, |
| 2339 | { 2006, 1029, 8, 206, 289, 139 }, |
| 2340 | { 2228, 1029, 8, 206, 289, 139 }, |
| 2341 | { 115, 1029, 8, 206, 289, 139 }, |
| 2342 | { 434, 1029, 8, 206, 289, 139 }, |
| 2343 | { 697, 1029, 8, 206, 289, 139 }, |
| 2344 | { 954, 1029, 8, 206, 289, 139 }, |
| 2345 | { 1154, 1029, 8, 206, 289, 139 }, |
| 2346 | { 1410, 1029, 8, 206, 289, 139 }, |
| 2347 | { 1606, 1029, 8, 206, 289, 139 }, |
| 2348 | { 1860, 1029, 8, 206, 289, 139 }, |
| 2349 | { 2074, 1029, 8, 206, 289, 139 }, |
| 2350 | { 2296, 1029, 8, 206, 289, 139 }, |
| 2351 | { 179, 1029, 8, 206, 289, 139 }, |
| 2352 | { 494, 1029, 8, 206, 289, 139 }, |
| 2353 | { 243, 1075, 8, 206, 3136, 148 }, |
| 2354 | { 562, 937, 8, 206, 4368, 123 }, |
| 2355 | { 757, 983, 8, 206, 10960, 43 }, |
| 2356 | { 761, 847, 801, 176, 3281, 157 }, |
| 2357 | { 1021, 847, 415, 176, 3281, 157 }, |
| 2358 | { 1215, 847, 415, 176, 3281, 157 }, |
| 2359 | { 1477, 847, 415, 176, 3281, 157 }, |
| 2360 | { 1667, 847, 415, 176, 3281, 157 }, |
| 2361 | { 1945, 847, 415, 176, 3281, 157 }, |
| 2362 | { 2135, 847, 415, 176, 3281, 157 }, |
| 2363 | { 2381, 847, 415, 176, 3281, 157 }, |
| 2364 | { 53, 847, 415, 176, 3281, 157 }, |
| 2365 | { 339, 847, 415, 176, 3281, 157 }, |
| 2366 | { 633, 847, 415, 176, 3281, 157 }, |
| 2367 | { 858, 847, 415, 176, 3281, 157 }, |
| 2368 | { 1090, 847, 415, 176, 3281, 157 }, |
| 2369 | { 1314, 847, 415, 176, 3281, 157 }, |
| 2370 | { 1542, 847, 415, 176, 3281, 157 }, |
| 2371 | { 1764, 847, 415, 176, 3281, 157 }, |
| 2372 | { 2010, 847, 415, 176, 3281, 157 }, |
| 2373 | { 2232, 847, 415, 176, 3281, 157 }, |
| 2374 | { 119, 847, 415, 176, 3281, 157 }, |
| 2375 | { 438, 847, 415, 176, 3281, 157 }, |
| 2376 | { 701, 847, 415, 176, 3281, 157 }, |
| 2377 | { 958, 847, 415, 176, 3281, 157 }, |
| 2378 | { 1158, 847, 415, 176, 3281, 157 }, |
| 2379 | { 1414, 847, 415, 176, 3281, 157 }, |
| 2380 | { 1610, 847, 415, 176, 3281, 157 }, |
| 2381 | { 1864, 847, 415, 176, 3281, 157 }, |
| 2382 | { 2078, 847, 415, 176, 3281, 157 }, |
| 2383 | { 2300, 847, 415, 176, 3281, 157 }, |
| 2384 | { 183, 847, 415, 176, 3281, 157 }, |
| 2385 | { 498, 847, 415, 176, 3281, 157 }, |
| 2386 | { 247, 877, 415, 176, 4576, 132 }, |
| 2387 | { 566, 907, 415, 176, 12192, 52 }, |
| 2388 | }; |
| 2389 | |
| 2390 | extern const MCPhysReg AArch64RegUnitRoots[][2] = { |
| 2391 | { AArch64::FFR }, |
| 2392 | { AArch64::W29 }, |
| 2393 | { AArch64::W30 }, |
| 2394 | { AArch64::NZCV }, |
| 2395 | { AArch64::WSP }, |
| 2396 | { AArch64::VG }, |
| 2397 | { AArch64::WZR }, |
| 2398 | { AArch64::B0 }, |
| 2399 | { AArch64::B1 }, |
| 2400 | { AArch64::B2 }, |
| 2401 | { AArch64::B3 }, |
| 2402 | { AArch64::B4 }, |
| 2403 | { AArch64::B5 }, |
| 2404 | { AArch64::B6 }, |
| 2405 | { AArch64::B7 }, |
| 2406 | { AArch64::B8 }, |
| 2407 | { AArch64::B9 }, |
| 2408 | { AArch64::B10 }, |
| 2409 | { AArch64::B11 }, |
| 2410 | { AArch64::B12 }, |
| 2411 | { AArch64::B13 }, |
| 2412 | { AArch64::B14 }, |
| 2413 | { AArch64::B15 }, |
| 2414 | { AArch64::B16 }, |
| 2415 | { AArch64::B17 }, |
| 2416 | { AArch64::B18 }, |
| 2417 | { AArch64::B19 }, |
| 2418 | { AArch64::B20 }, |
| 2419 | { AArch64::B21 }, |
| 2420 | { AArch64::B22 }, |
| 2421 | { AArch64::B23 }, |
| 2422 | { AArch64::B24 }, |
| 2423 | { AArch64::B25 }, |
| 2424 | { AArch64::B26 }, |
| 2425 | { AArch64::B27 }, |
| 2426 | { AArch64::B28 }, |
| 2427 | { AArch64::B29 }, |
| 2428 | { AArch64::B30 }, |
| 2429 | { AArch64::B31 }, |
| 2430 | { AArch64::P0 }, |
| 2431 | { AArch64::P1 }, |
| 2432 | { AArch64::P2 }, |
| 2433 | { AArch64::P3 }, |
| 2434 | { AArch64::P4 }, |
| 2435 | { AArch64::P5 }, |
| 2436 | { AArch64::P6 }, |
| 2437 | { AArch64::P7 }, |
| 2438 | { AArch64::P8 }, |
| 2439 | { AArch64::P9 }, |
| 2440 | { AArch64::P10 }, |
| 2441 | { AArch64::P11 }, |
| 2442 | { AArch64::P12 }, |
| 2443 | { AArch64::P13 }, |
| 2444 | { AArch64::P14 }, |
| 2445 | { AArch64::P15 }, |
| 2446 | { AArch64::W0 }, |
| 2447 | { AArch64::W1 }, |
| 2448 | { AArch64::W2 }, |
| 2449 | { AArch64::W3 }, |
| 2450 | { AArch64::W4 }, |
| 2451 | { AArch64::W5 }, |
| 2452 | { AArch64::W6 }, |
| 2453 | { AArch64::W7 }, |
| 2454 | { AArch64::W8 }, |
| 2455 | { AArch64::W9 }, |
| 2456 | { AArch64::W10 }, |
| 2457 | { AArch64::W11 }, |
| 2458 | { AArch64::W12 }, |
| 2459 | { AArch64::W13 }, |
| 2460 | { AArch64::W14 }, |
| 2461 | { AArch64::W15 }, |
| 2462 | { AArch64::W16 }, |
| 2463 | { AArch64::W17 }, |
| 2464 | { AArch64::W18 }, |
| 2465 | { AArch64::W19 }, |
| 2466 | { AArch64::W20 }, |
| 2467 | { AArch64::W21 }, |
| 2468 | { AArch64::W22 }, |
| 2469 | { AArch64::W23 }, |
| 2470 | { AArch64::W24 }, |
| 2471 | { AArch64::W25 }, |
| 2472 | { AArch64::W26 }, |
| 2473 | { AArch64::W27 }, |
| 2474 | { AArch64::W28 }, |
| 2475 | { AArch64::Z0_HI }, |
| 2476 | { AArch64::Z1_HI }, |
| 2477 | { AArch64::Z2_HI }, |
| 2478 | { AArch64::Z3_HI }, |
| 2479 | { AArch64::Z4_HI }, |
| 2480 | { AArch64::Z5_HI }, |
| 2481 | { AArch64::Z6_HI }, |
| 2482 | { AArch64::Z7_HI }, |
| 2483 | { AArch64::Z8_HI }, |
| 2484 | { AArch64::Z9_HI }, |
| 2485 | { AArch64::Z10_HI }, |
| 2486 | { AArch64::Z11_HI }, |
| 2487 | { AArch64::Z12_HI }, |
| 2488 | { AArch64::Z13_HI }, |
| 2489 | { AArch64::Z14_HI }, |
| 2490 | { AArch64::Z15_HI }, |
| 2491 | { AArch64::Z16_HI }, |
| 2492 | { AArch64::Z17_HI }, |
| 2493 | { AArch64::Z18_HI }, |
| 2494 | { AArch64::Z19_HI }, |
| 2495 | { AArch64::Z20_HI }, |
| 2496 | { AArch64::Z21_HI }, |
| 2497 | { AArch64::Z22_HI }, |
| 2498 | { AArch64::Z23_HI }, |
| 2499 | { AArch64::Z24_HI }, |
| 2500 | { AArch64::Z25_HI }, |
| 2501 | { AArch64::Z26_HI }, |
| 2502 | { AArch64::Z27_HI }, |
| 2503 | { AArch64::Z28_HI }, |
| 2504 | { AArch64::Z29_HI }, |
| 2505 | { AArch64::Z30_HI }, |
| 2506 | { AArch64::Z31_HI }, |
| 2507 | }; |
| 2508 | |
| 2509 | namespace { // Register classes... |
| 2510 | // FPR8 Register Class... |
| 2511 | const MCPhysReg FPR8[] = { |
| 2512 | AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, |
| 2513 | }; |
| 2514 | |
| 2515 | // FPR8 Bit set. |
| 2516 | const uint8_t FPR8Bits[] = { |
| 2517 | 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 2518 | }; |
| 2519 | |
| 2520 | // FPR16 Register Class... |
| 2521 | const MCPhysReg FPR16[] = { |
| 2522 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, |
| 2523 | }; |
| 2524 | |
| 2525 | // FPR16 Bit set. |
| 2526 | const uint8_t FPR16Bits[] = { |
| 2527 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 2528 | }; |
| 2529 | |
| 2530 | // FPR16_lo Register Class... |
| 2531 | const MCPhysReg FPR16_lo[] = { |
| 2532 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, |
| 2533 | }; |
| 2534 | |
| 2535 | // FPR16_lo Bit set. |
| 2536 | const uint8_t FPR16_loBits[] = { |
| 2537 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 2538 | }; |
| 2539 | |
| 2540 | // PPR Register Class... |
| 2541 | const MCPhysReg PPR[] = { |
| 2542 | AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, |
| 2543 | }; |
| 2544 | |
| 2545 | // PPR Bit set. |
| 2546 | const uint8_t PPRBits[] = { |
| 2547 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 2548 | }; |
| 2549 | |
| 2550 | // PPR_3b Register Class... |
| 2551 | const MCPhysReg PPR_3b[] = { |
| 2552 | AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, |
| 2553 | }; |
| 2554 | |
| 2555 | // PPR_3b Bit set. |
| 2556 | const uint8_t PPR_3bBits[] = { |
| 2557 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| 2558 | }; |
| 2559 | |
| 2560 | // GPR32all Register Class... |
| 2561 | const MCPhysReg GPR32all[] = { |
| 2562 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, |
| 2563 | }; |
| 2564 | |
| 2565 | // GPR32all Bit set. |
| 2566 | const uint8_t GPR32allBits[] = { |
| 2567 | 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x01, |
| 2568 | }; |
| 2569 | |
| 2570 | // FPR32 Register Class... |
| 2571 | const MCPhysReg FPR32[] = { |
| 2572 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, |
| 2573 | }; |
| 2574 | |
| 2575 | // FPR32 Bit set. |
| 2576 | const uint8_t FPR32Bits[] = { |
| 2577 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 2578 | }; |
| 2579 | |
| 2580 | // GPR32 Register Class... |
| 2581 | const MCPhysReg GPR32[] = { |
| 2582 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, |
| 2583 | }; |
| 2584 | |
| 2585 | // GPR32 Bit set. |
| 2586 | const uint8_t GPR32Bits[] = { |
| 2587 | 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x01, |
| 2588 | }; |
| 2589 | |
| 2590 | // GPR32sp Register Class... |
| 2591 | const MCPhysReg GPR32sp[] = { |
| 2592 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, |
| 2593 | }; |
| 2594 | |
| 2595 | // GPR32sp Bit set. |
| 2596 | const uint8_t GPR32spBits[] = { |
| 2597 | 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x01, |
| 2598 | }; |
| 2599 | |
| 2600 | // GPR32common Register Class... |
| 2601 | const MCPhysReg GPR32common[] = { |
| 2602 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, |
| 2603 | }; |
| 2604 | |
| 2605 | // GPR32common Bit set. |
| 2606 | const uint8_t GPR32commonBits[] = { |
| 2607 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x01, |
| 2608 | }; |
| 2609 | |
| 2610 | // FPR32_with_hsub_in_FPR16_lo Register Class... |
| 2611 | const MCPhysReg FPR32_with_hsub_in_FPR16_lo[] = { |
| 2612 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, |
| 2613 | }; |
| 2614 | |
| 2615 | // FPR32_with_hsub_in_FPR16_lo Bit set. |
| 2616 | const uint8_t FPR32_with_hsub_in_FPR16_loBits[] = { |
| 2617 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 2618 | }; |
| 2619 | |
| 2620 | // GPR32arg Register Class... |
| 2621 | const MCPhysReg GPR32arg[] = { |
| 2622 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, |
| 2623 | }; |
| 2624 | |
| 2625 | // GPR32arg Bit set. |
| 2626 | const uint8_t GPR32argBits[] = { |
| 2627 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| 2628 | }; |
| 2629 | |
| 2630 | // CCR Register Class... |
| 2631 | const MCPhysReg CCR[] = { |
| 2632 | AArch64::NZCV, |
| 2633 | }; |
| 2634 | |
| 2635 | // CCR Bit set. |
| 2636 | const uint8_t CCRBits[] = { |
| 2637 | 0x10, |
| 2638 | }; |
| 2639 | |
| 2640 | // GPR32sponly Register Class... |
| 2641 | const MCPhysReg GPR32sponly[] = { |
| 2642 | AArch64::WSP, |
| 2643 | }; |
| 2644 | |
| 2645 | // GPR32sponly Bit set. |
| 2646 | const uint8_t GPR32sponlyBits[] = { |
| 2647 | 0x80, |
| 2648 | }; |
| 2649 | |
| 2650 | // WSeqPairsClass Register Class... |
| 2651 | const MCPhysReg WSeqPairsClass[] = { |
| 2652 | AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29, AArch64::W30_WZR, |
| 2653 | }; |
| 2654 | |
| 2655 | // WSeqPairsClass Bit set. |
| 2656 | const uint8_t WSeqPairsClassBits[] = { |
| 2657 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 2658 | }; |
| 2659 | |
| 2660 | // WSeqPairsClass_with_subo32_in_GPR32common Register Class... |
| 2661 | const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = { |
| 2662 | AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, AArch64::W8_W9, AArch64::W10_W11, AArch64::W12_W13, AArch64::W14_W15, AArch64::W16_W17, AArch64::W18_W19, AArch64::W20_W21, AArch64::W22_W23, AArch64::W24_W25, AArch64::W26_W27, AArch64::W28_W29, |
| 2663 | }; |
| 2664 | |
| 2665 | // WSeqPairsClass_with_subo32_in_GPR32common Bit set. |
| 2666 | const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = { |
| 2667 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, |
| 2668 | }; |
| 2669 | |
| 2670 | // WSeqPairsClass_with_sube32_in_GPR32arg Register Class... |
| 2671 | const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32arg[] = { |
| 2672 | AArch64::W0_W1, AArch64::W2_W3, AArch64::W4_W5, AArch64::W6_W7, |
| 2673 | }; |
| 2674 | |
| 2675 | // WSeqPairsClass_with_sube32_in_GPR32arg Bit set. |
| 2676 | const uint8_t WSeqPairsClass_with_sube32_in_GPR32argBits[] = { |
| 2677 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, |
| 2678 | }; |
| 2679 | |
| 2680 | // GPR64all Register Class... |
| 2681 | const MCPhysReg GPR64all[] = { |
| 2682 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, |
| 2683 | }; |
| 2684 | |
| 2685 | // GPR64all Bit set. |
| 2686 | const uint8_t GPR64allBits[] = { |
| 2687 | 0x2c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x3f, |
| 2688 | }; |
| 2689 | |
| 2690 | // FPR64 Register Class... |
| 2691 | const MCPhysReg FPR64[] = { |
| 2692 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, |
| 2693 | }; |
| 2694 | |
| 2695 | // FPR64 Bit set. |
| 2696 | const uint8_t FPR64Bits[] = { |
| 2697 | 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 2698 | }; |
| 2699 | |
| 2700 | // GPR64 Register Class... |
| 2701 | const MCPhysReg GPR64[] = { |
| 2702 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, |
| 2703 | }; |
| 2704 | |
| 2705 | // GPR64 Bit set. |
| 2706 | const uint8_t GPR64Bits[] = { |
| 2707 | 0x0c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x3f, |
| 2708 | }; |
| 2709 | |
| 2710 | // GPR64sp Register Class... |
| 2711 | const MCPhysReg GPR64sp[] = { |
| 2712 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, |
| 2713 | }; |
| 2714 | |
| 2715 | // GPR64sp Bit set. |
| 2716 | const uint8_t GPR64spBits[] = { |
| 2717 | 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x3f, |
| 2718 | }; |
| 2719 | |
| 2720 | // GPR64common Register Class... |
| 2721 | const MCPhysReg GPR64common[] = { |
| 2722 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, |
| 2723 | }; |
| 2724 | |
| 2725 | // GPR64common Bit set. |
| 2726 | const uint8_t GPR64commonBits[] = { |
| 2727 | 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x3f, |
| 2728 | }; |
| 2729 | |
| 2730 | // GPR64noip Register Class... |
| 2731 | const MCPhysReg GPR64noip[] = { |
| 2732 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::XZR, |
| 2733 | }; |
| 2734 | |
| 2735 | // GPR64noip Bit set. |
| 2736 | const uint8_t GPR64noipBits[] = { |
| 2737 | 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xf9, 0x3f, |
| 2738 | }; |
| 2739 | |
| 2740 | // GPR64common_and_GPR64noip Register Class... |
| 2741 | const MCPhysReg GPR64common_and_GPR64noip[] = { |
| 2742 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, |
| 2743 | }; |
| 2744 | |
| 2745 | // GPR64common_and_GPR64noip Bit set. |
| 2746 | const uint8_t GPR64common_and_GPR64noipBits[] = { |
| 2747 | 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xf9, 0x3f, |
| 2748 | }; |
| 2749 | |
| 2750 | // tcGPR64 Register Class... |
| 2751 | const MCPhysReg tcGPR64[] = { |
| 2752 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, |
| 2753 | }; |
| 2754 | |
| 2755 | // tcGPR64 Bit set. |
| 2756 | const uint8_t tcGPR64Bits[] = { |
| 2757 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x0f, |
| 2758 | }; |
| 2759 | |
| 2760 | // GPR64noip_and_tcGPR64 Register Class... |
| 2761 | const MCPhysReg GPR64noip_and_tcGPR64[] = { |
| 2762 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, |
| 2763 | }; |
| 2764 | |
| 2765 | // GPR64noip_and_tcGPR64 Bit set. |
| 2766 | const uint8_t GPR64noip_and_tcGPR64Bits[] = { |
| 2767 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x09, |
| 2768 | }; |
| 2769 | |
| 2770 | // FPR64_lo Register Class... |
| 2771 | const MCPhysReg FPR64_lo[] = { |
| 2772 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, |
| 2773 | }; |
| 2774 | |
| 2775 | // FPR64_lo Bit set. |
| 2776 | const uint8_t FPR64_loBits[] = { |
| 2777 | 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 2778 | }; |
| 2779 | |
| 2780 | // GPR64x8Class Register Class... |
| 2781 | const MCPhysReg GPR64x8Class[] = { |
| 2782 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2783 | }; |
| 2784 | |
| 2785 | // GPR64x8Class Bit set. |
| 2786 | const uint8_t GPR64x8ClassBits[] = { |
| 2787 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x03, |
| 2788 | }; |
| 2789 | |
| 2790 | // GPR64x8Class_with_x8sub_0_in_GPR64noip Register Class... |
| 2791 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip[] = { |
| 2792 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2793 | }; |
| 2794 | |
| 2795 | // GPR64x8Class_with_x8sub_0_in_GPR64noip Bit set. |
| 2796 | const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noipBits[] = { |
| 2797 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x7f, 0x03, |
| 2798 | }; |
| 2799 | |
| 2800 | // GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class... |
| 2801 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip[] = { |
| 2802 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2803 | }; |
| 2804 | |
| 2805 | // GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set. |
| 2806 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = { |
| 2807 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0x03, |
| 2808 | }; |
| 2809 | |
| 2810 | // GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 2811 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 2812 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2813 | }; |
| 2814 | |
| 2815 | // GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 2816 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 2817 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xdf, 0x03, |
| 2818 | }; |
| 2819 | |
| 2820 | // GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2821 | const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2822 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2823 | }; |
| 2824 | |
| 2825 | // GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2826 | const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2827 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xef, 0x03, |
| 2828 | }; |
| 2829 | |
| 2830 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class... |
| 2831 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip[] = { |
| 2832 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2833 | }; |
| 2834 | |
| 2835 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set. |
| 2836 | const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = { |
| 2837 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 0x03, |
| 2838 | }; |
| 2839 | |
| 2840 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 2841 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 2842 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2843 | }; |
| 2844 | |
| 2845 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 2846 | const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 2847 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x5f, 0x03, |
| 2848 | }; |
| 2849 | |
| 2850 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2851 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2852 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2853 | }; |
| 2854 | |
| 2855 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2856 | const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2857 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x6f, 0x03, |
| 2858 | }; |
| 2859 | |
| 2860 | // GPR64x8Class_with_x8sub_0_in_tcGPR64 Register Class... |
| 2861 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64[] = { |
| 2862 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 2863 | }; |
| 2864 | |
| 2865 | // GPR64x8Class_with_x8sub_0_in_tcGPR64 Bit set. |
| 2866 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64Bits[] = { |
| 2867 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, |
| 2868 | }; |
| 2869 | |
| 2870 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 2871 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 2872 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2873 | }; |
| 2874 | |
| 2875 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 2876 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 2877 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x9f, 0x03, |
| 2878 | }; |
| 2879 | |
| 2880 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2881 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2882 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2883 | }; |
| 2884 | |
| 2885 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2886 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2887 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xaf, 0x03, |
| 2888 | }; |
| 2889 | |
| 2890 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2891 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2892 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2893 | }; |
| 2894 | |
| 2895 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2896 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2897 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xcf, 0x03, |
| 2898 | }; |
| 2899 | |
| 2900 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 Register Class... |
| 2901 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64[] = { |
| 2902 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 2903 | }; |
| 2904 | |
| 2905 | // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 Bit set. |
| 2906 | const uint8_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Bits[] = { |
| 2907 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, 0x01, |
| 2908 | }; |
| 2909 | |
| 2910 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class... |
| 2911 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip[] = { |
| 2912 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 2913 | }; |
| 2914 | |
| 2915 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set. |
| 2916 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = { |
| 2917 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, 0x01, |
| 2918 | }; |
| 2919 | |
| 2920 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 2921 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 2922 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 2923 | }; |
| 2924 | |
| 2925 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 2926 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 2927 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xdf, 0x01, |
| 2928 | }; |
| 2929 | |
| 2930 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2931 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2932 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 2933 | }; |
| 2934 | |
| 2935 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2936 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2937 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xef, 0x01, |
| 2938 | }; |
| 2939 | |
| 2940 | // GPR64x8Class_with_x8sub_1_in_tcGPR64 Register Class... |
| 2941 | const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64[] = { |
| 2942 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 2943 | }; |
| 2944 | |
| 2945 | // GPR64x8Class_with_x8sub_1_in_tcGPR64 Bit set. |
| 2946 | const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64Bits[] = { |
| 2947 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, |
| 2948 | }; |
| 2949 | |
| 2950 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 2951 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 2952 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2953 | }; |
| 2954 | |
| 2955 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 2956 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 2957 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x1f, 0x03, |
| 2958 | }; |
| 2959 | |
| 2960 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2961 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2962 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2963 | }; |
| 2964 | |
| 2965 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2966 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2967 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x2f, 0x03, |
| 2968 | }; |
| 2969 | |
| 2970 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2971 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2972 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2973 | }; |
| 2974 | |
| 2975 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2976 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2977 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x4f, 0x03, |
| 2978 | }; |
| 2979 | |
| 2980 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 2981 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 2982 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 2983 | }; |
| 2984 | |
| 2985 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 2986 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 2987 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x8f, 0x03, |
| 2988 | }; |
| 2989 | |
| 2990 | // GPR64arg Register Class... |
| 2991 | const MCPhysReg GPR64arg[] = { |
| 2992 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, |
| 2993 | }; |
| 2994 | |
| 2995 | // GPR64arg Bit set. |
| 2996 | const uint8_t GPR64argBits[] = { |
| 2997 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, |
| 2998 | }; |
| 2999 | |
| 3000 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Register Class... |
| 3001 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip[] = { |
| 3002 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3003 | }; |
| 3004 | |
| 3005 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip Bit set. |
| 3006 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits[] = { |
| 3007 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, 0x01, |
| 3008 | }; |
| 3009 | |
| 3010 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 3011 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 3012 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3013 | }; |
| 3014 | |
| 3015 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 3016 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 3017 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x5f, 0x01, |
| 3018 | }; |
| 3019 | |
| 3020 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3021 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3022 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3023 | }; |
| 3024 | |
| 3025 | // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3026 | const uint8_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3027 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x6f, 0x01, |
| 3028 | }; |
| 3029 | |
| 3030 | // GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 Register Class... |
| 3031 | const MCPhysReg GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64[] = { |
| 3032 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, |
| 3033 | }; |
| 3034 | |
| 3035 | // GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 Bit set. |
| 3036 | const uint8_t GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3037 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f, |
| 3038 | }; |
| 3039 | |
| 3040 | // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 3041 | const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 3042 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3043 | }; |
| 3044 | |
| 3045 | // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 3046 | const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 3047 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xdf, |
| 3048 | }; |
| 3049 | |
| 3050 | // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3051 | const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3052 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3053 | }; |
| 3054 | |
| 3055 | // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3056 | const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3057 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xef, |
| 3058 | }; |
| 3059 | |
| 3060 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 3061 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 3062 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3063 | }; |
| 3064 | |
| 3065 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 3066 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 3067 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, 0x01, |
| 3068 | }; |
| 3069 | |
| 3070 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3071 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3072 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3073 | }; |
| 3074 | |
| 3075 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3076 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3077 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaf, 0x01, |
| 3078 | }; |
| 3079 | |
| 3080 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 Register Class... |
| 3081 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64[] = { |
| 3082 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3083 | }; |
| 3084 | |
| 3085 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 Bit set. |
| 3086 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3087 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xbf, |
| 3088 | }; |
| 3089 | |
| 3090 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3091 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3092 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3093 | }; |
| 3094 | |
| 3095 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3096 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3097 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xcf, 0x01, |
| 3098 | }; |
| 3099 | |
| 3100 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3101 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3102 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, AArch64::X20_X21_X22_X23_X24_X25_X26_X27, AArch64::X22_X23_X24_X25_X26_X27_X28_FP, |
| 3103 | }; |
| 3104 | |
| 3105 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3106 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3107 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f, 0x03, |
| 3108 | }; |
| 3109 | |
| 3110 | // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3111 | const MCPhysReg GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3112 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, |
| 3113 | }; |
| 3114 | |
| 3115 | // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3116 | const uint8_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3117 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x6f, |
| 3118 | }; |
| 3119 | |
| 3120 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 3121 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 3122 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3123 | }; |
| 3124 | |
| 3125 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 3126 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 3127 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, 0x01, |
| 3128 | }; |
| 3129 | |
| 3130 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3131 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3132 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3133 | }; |
| 3134 | |
| 3135 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3136 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3137 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2f, 0x01, |
| 3138 | }; |
| 3139 | |
| 3140 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Register Class... |
| 3141 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip[] = { |
| 3142 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3143 | }; |
| 3144 | |
| 3145 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip Bit set. |
| 3146 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits[] = { |
| 3147 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x9f, |
| 3148 | }; |
| 3149 | |
| 3150 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3151 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3152 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3153 | }; |
| 3154 | |
| 3155 | // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3156 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3157 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaf, |
| 3158 | }; |
| 3159 | |
| 3160 | // GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 Register Class... |
| 3161 | const MCPhysReg GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64[] = { |
| 3162 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, |
| 3163 | }; |
| 3164 | |
| 3165 | // GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 Bit set. |
| 3166 | const uint8_t GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3167 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f, |
| 3168 | }; |
| 3169 | |
| 3170 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3171 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3172 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3173 | }; |
| 3174 | |
| 3175 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3176 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3177 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x4f, 0x01, |
| 3178 | }; |
| 3179 | |
| 3180 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3181 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3182 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3183 | }; |
| 3184 | |
| 3185 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3186 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3187 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xcf, |
| 3188 | }; |
| 3189 | |
| 3190 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3191 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3192 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3193 | }; |
| 3194 | |
| 3195 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3196 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3197 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x8f, 0x01, |
| 3198 | }; |
| 3199 | |
| 3200 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 Register Class... |
| 3201 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64[] = { |
| 3202 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, |
| 3203 | }; |
| 3204 | |
| 3205 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 Bit set. |
| 3206 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3207 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x5f, |
| 3208 | }; |
| 3209 | |
| 3210 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3211 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3212 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X14_X15_X16_X17_X18_X19_X20_X21, |
| 3213 | }; |
| 3214 | |
| 3215 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3216 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3217 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x4f, |
| 3218 | }; |
| 3219 | |
| 3220 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3221 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3222 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X18_X19_X20_X21_X22_X23_X24_X25, |
| 3223 | }; |
| 3224 | |
| 3225 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3226 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3227 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, 0x01, |
| 3228 | }; |
| 3229 | |
| 3230 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Register Class... |
| 3231 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip[] = { |
| 3232 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3233 | }; |
| 3234 | |
| 3235 | // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip Bit set. |
| 3236 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits[] = { |
| 3237 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x8f, |
| 3238 | }; |
| 3239 | |
| 3240 | // GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 Register Class... |
| 3241 | const MCPhysReg GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64[] = { |
| 3242 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X10_X11_X12_X13_X14_X15_X16_X17, |
| 3243 | }; |
| 3244 | |
| 3245 | // GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 Bit set. |
| 3246 | const uint8_t GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3247 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f, |
| 3248 | }; |
| 3249 | |
| 3250 | // GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 Register Class... |
| 3251 | const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64[] = { |
| 3252 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, AArch64::X12_X13_X14_X15_X16_X17_X18_X19, |
| 3253 | }; |
| 3254 | |
| 3255 | // GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 Bit set. |
| 3256 | const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3257 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2f, |
| 3258 | }; |
| 3259 | |
| 3260 | // GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 Register Class... |
| 3261 | const MCPhysReg GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64[] = { |
| 3262 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, AArch64::X8_X9_X10_X11_X12_X13_X14_X15, |
| 3263 | }; |
| 3264 | |
| 3265 | // GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 Bit set. |
| 3266 | const uint8_t GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3267 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, |
| 3268 | }; |
| 3269 | |
| 3270 | // GPR64x8Class_with_sub_32_in_GPR32arg Register Class... |
| 3271 | const MCPhysReg GPR64x8Class_with_sub_32_in_GPR32arg[] = { |
| 3272 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, AArch64::X6_X7_X8_X9_X10_X11_X12_X13, |
| 3273 | }; |
| 3274 | |
| 3275 | // GPR64x8Class_with_sub_32_in_GPR32arg Bit set. |
| 3276 | const uint8_t GPR64x8Class_with_sub_32_in_GPR32argBits[] = { |
| 3277 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x07, |
| 3278 | }; |
| 3279 | |
| 3280 | // GPR64x8Class_with_x8sub_2_in_GPR64arg Register Class... |
| 3281 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_GPR64arg[] = { |
| 3282 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, AArch64::X4_X5_X6_X7_X8_X9_X10_X11, |
| 3283 | }; |
| 3284 | |
| 3285 | // GPR64x8Class_with_x8sub_2_in_GPR64arg Bit set. |
| 3286 | const uint8_t GPR64x8Class_with_x8sub_2_in_GPR64argBits[] = { |
| 3287 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, |
| 3288 | }; |
| 3289 | |
| 3290 | // GPR64x8Class_with_x8sub_4_in_GPR64arg Register Class... |
| 3291 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_GPR64arg[] = { |
| 3292 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, AArch64::X2_X3_X4_X5_X6_X7_X8_X9, |
| 3293 | }; |
| 3294 | |
| 3295 | // GPR64x8Class_with_x8sub_4_in_GPR64arg Bit set. |
| 3296 | const uint8_t GPR64x8Class_with_x8sub_4_in_GPR64argBits[] = { |
| 3297 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, |
| 3298 | }; |
| 3299 | |
| 3300 | // rtcGPR64 Register Class... |
| 3301 | const MCPhysReg rtcGPR64[] = { |
| 3302 | AArch64::X16, AArch64::X17, |
| 3303 | }; |
| 3304 | |
| 3305 | // rtcGPR64 Bit set. |
| 3306 | const uint8_t rtcGPR64Bits[] = { |
| 3307 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, |
| 3308 | }; |
| 3309 | |
| 3310 | // GPR64sponly Register Class... |
| 3311 | const MCPhysReg GPR64sponly[] = { |
| 3312 | AArch64::SP, |
| 3313 | }; |
| 3314 | |
| 3315 | // GPR64sponly Bit set. |
| 3316 | const uint8_t GPR64sponlyBits[] = { |
| 3317 | 0x20, |
| 3318 | }; |
| 3319 | |
| 3320 | // GPR64x8Class_with_x8sub_0_in_rtcGPR64 Register Class... |
| 3321 | const MCPhysReg GPR64x8Class_with_x8sub_0_in_rtcGPR64[] = { |
| 3322 | AArch64::X16_X17_X18_X19_X20_X21_X22_X23, |
| 3323 | }; |
| 3324 | |
| 3325 | // GPR64x8Class_with_x8sub_0_in_rtcGPR64 Bit set. |
| 3326 | const uint8_t GPR64x8Class_with_x8sub_0_in_rtcGPR64Bits[] = { |
| 3327 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
| 3328 | }; |
| 3329 | |
| 3330 | // GPR64x8Class_with_x8sub_2_in_rtcGPR64 Register Class... |
| 3331 | const MCPhysReg GPR64x8Class_with_x8sub_2_in_rtcGPR64[] = { |
| 3332 | AArch64::X14_X15_X16_X17_X18_X19_X20_X21, |
| 3333 | }; |
| 3334 | |
| 3335 | // GPR64x8Class_with_x8sub_2_in_rtcGPR64 Bit set. |
| 3336 | const uint8_t GPR64x8Class_with_x8sub_2_in_rtcGPR64Bits[] = { |
| 3337 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| 3338 | }; |
| 3339 | |
| 3340 | // GPR64x8Class_with_x8sub_4_in_rtcGPR64 Register Class... |
| 3341 | const MCPhysReg GPR64x8Class_with_x8sub_4_in_rtcGPR64[] = { |
| 3342 | AArch64::X12_X13_X14_X15_X16_X17_X18_X19, |
| 3343 | }; |
| 3344 | |
| 3345 | // GPR64x8Class_with_x8sub_4_in_rtcGPR64 Bit set. |
| 3346 | const uint8_t GPR64x8Class_with_x8sub_4_in_rtcGPR64Bits[] = { |
| 3347 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| 3348 | }; |
| 3349 | |
| 3350 | // GPR64x8Class_with_x8sub_6_in_GPR64arg Register Class... |
| 3351 | const MCPhysReg GPR64x8Class_with_x8sub_6_in_GPR64arg[] = { |
| 3352 | AArch64::X0_X1_X2_X3_X4_X5_X6_X7, |
| 3353 | }; |
| 3354 | |
| 3355 | // GPR64x8Class_with_x8sub_6_in_GPR64arg Bit set. |
| 3356 | const uint8_t GPR64x8Class_with_x8sub_6_in_GPR64argBits[] = { |
| 3357 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, |
| 3358 | }; |
| 3359 | |
| 3360 | // GPR64x8Class_with_x8sub_6_in_rtcGPR64 Register Class... |
| 3361 | const MCPhysReg GPR64x8Class_with_x8sub_6_in_rtcGPR64[] = { |
| 3362 | AArch64::X10_X11_X12_X13_X14_X15_X16_X17, |
| 3363 | }; |
| 3364 | |
| 3365 | // GPR64x8Class_with_x8sub_6_in_rtcGPR64 Bit set. |
| 3366 | const uint8_t GPR64x8Class_with_x8sub_6_in_rtcGPR64Bits[] = { |
| 3367 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 3368 | }; |
| 3369 | |
| 3370 | // DD Register Class... |
| 3371 | const MCPhysReg DD[] = { |
| 3372 | AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, |
| 3373 | }; |
| 3374 | |
| 3375 | // DD Bit set. |
| 3376 | const uint8_t DDBits[] = { |
| 3377 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 3378 | }; |
| 3379 | |
| 3380 | // DD_with_dsub0_in_FPR64_lo Register Class... |
| 3381 | const MCPhysReg DD_with_dsub0_in_FPR64_lo[] = { |
| 3382 | AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, |
| 3383 | }; |
| 3384 | |
| 3385 | // DD_with_dsub0_in_FPR64_lo Bit set. |
| 3386 | const uint8_t DD_with_dsub0_in_FPR64_loBits[] = { |
| 3387 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 3388 | }; |
| 3389 | |
| 3390 | // DD_with_dsub1_in_FPR64_lo Register Class... |
| 3391 | const MCPhysReg DD_with_dsub1_in_FPR64_lo[] = { |
| 3392 | AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D31_D0, |
| 3393 | }; |
| 3394 | |
| 3395 | // DD_with_dsub1_in_FPR64_lo Bit set. |
| 3396 | const uint8_t DD_with_dsub1_in_FPR64_loBits[] = { |
| 3397 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, |
| 3398 | }; |
| 3399 | |
| 3400 | // XSeqPairsClass Register Class... |
| 3401 | const MCPhysReg XSeqPairsClass[] = { |
| 3402 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR, |
| 3403 | }; |
| 3404 | |
| 3405 | // XSeqPairsClass Bit set. |
| 3406 | const uint8_t XSeqPairsClassBits[] = { |
| 3407 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 3408 | }; |
| 3409 | |
| 3410 | // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo Register Class... |
| 3411 | const MCPhysReg DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo[] = { |
| 3412 | AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, |
| 3413 | }; |
| 3414 | |
| 3415 | // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo Bit set. |
| 3416 | const uint8_t DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits[] = { |
| 3417 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| 3418 | }; |
| 3419 | |
| 3420 | // XSeqPairsClass_with_subo64_in_GPR64common Register Class... |
| 3421 | const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = { |
| 3422 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, |
| 3423 | }; |
| 3424 | |
| 3425 | // XSeqPairsClass_with_subo64_in_GPR64common Bit set. |
| 3426 | const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = { |
| 3427 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03, |
| 3428 | }; |
| 3429 | |
| 3430 | // XSeqPairsClass_with_subo64_in_GPR64noip Register Class... |
| 3431 | const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip[] = { |
| 3432 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, AArch64::LR_XZR, |
| 3433 | }; |
| 3434 | |
| 3435 | // XSeqPairsClass_with_subo64_in_GPR64noip Bit set. |
| 3436 | const uint8_t XSeqPairsClass_with_subo64_in_GPR64noipBits[] = { |
| 3437 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xef, 0x03, |
| 3438 | }; |
| 3439 | |
| 3440 | // XSeqPairsClass_with_sube64_in_GPR64noip Register Class... |
| 3441 | const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip[] = { |
| 3442 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, AArch64::X20_X21, AArch64::X22_X23, AArch64::X24_X25, AArch64::X26_X27, AArch64::X28_FP, |
| 3443 | }; |
| 3444 | |
| 3445 | // XSeqPairsClass_with_sube64_in_GPR64noip Bit set. |
| 3446 | const uint8_t XSeqPairsClass_with_sube64_in_GPR64noipBits[] = { |
| 3447 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xef, 0x03, |
| 3448 | }; |
| 3449 | |
| 3450 | // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class... |
| 3451 | const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = { |
| 3452 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, AArch64::X18_X19, |
| 3453 | }; |
| 3454 | |
| 3455 | // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set. |
| 3456 | const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = { |
| 3457 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x3f, |
| 3458 | }; |
| 3459 | |
| 3460 | // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Register Class... |
| 3461 | const MCPhysReg XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64[] = { |
| 3462 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X18_X19, |
| 3463 | }; |
| 3464 | |
| 3465 | // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 Bit set. |
| 3466 | const uint8_t XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3467 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x2f, |
| 3468 | }; |
| 3469 | |
| 3470 | // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class... |
| 3471 | const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = { |
| 3472 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, AArch64::X16_X17, |
| 3473 | }; |
| 3474 | |
| 3475 | // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set. |
| 3476 | const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = { |
| 3477 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x1f, |
| 3478 | }; |
| 3479 | |
| 3480 | // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Register Class... |
| 3481 | const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64[] = { |
| 3482 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, AArch64::X8_X9, AArch64::X10_X11, AArch64::X12_X13, AArch64::X14_X15, |
| 3483 | }; |
| 3484 | |
| 3485 | // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 Bit set. |
| 3486 | const uint8_t XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits[] = { |
| 3487 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, |
| 3488 | }; |
| 3489 | |
| 3490 | // XSeqPairsClass_with_sub_32_in_GPR32arg Register Class... |
| 3491 | const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32arg[] = { |
| 3492 | AArch64::X0_X1, AArch64::X2_X3, AArch64::X4_X5, AArch64::X6_X7, |
| 3493 | }; |
| 3494 | |
| 3495 | // XSeqPairsClass_with_sub_32_in_GPR32arg Bit set. |
| 3496 | const uint8_t XSeqPairsClass_with_sub_32_in_GPR32argBits[] = { |
| 3497 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, |
| 3498 | }; |
| 3499 | |
| 3500 | // XSeqPairsClass_with_sube64_in_rtcGPR64 Register Class... |
| 3501 | const MCPhysReg XSeqPairsClass_with_sube64_in_rtcGPR64[] = { |
| 3502 | AArch64::X16_X17, |
| 3503 | }; |
| 3504 | |
| 3505 | // XSeqPairsClass_with_sube64_in_rtcGPR64 Bit set. |
| 3506 | const uint8_t XSeqPairsClass_with_sube64_in_rtcGPR64Bits[] = { |
| 3507 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| 3508 | }; |
| 3509 | |
| 3510 | // FPR128 Register Class... |
| 3511 | const MCPhysReg FPR128[] = { |
| 3512 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, |
| 3513 | }; |
| 3514 | |
| 3515 | // FPR128 Bit set. |
| 3516 | const uint8_t FPR128Bits[] = { |
| 3517 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 3518 | }; |
| 3519 | |
| 3520 | // ZPR Register Class... |
| 3521 | const MCPhysReg ZPR[] = { |
| 3522 | AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::Z24, AArch64::Z25, AArch64::Z26, AArch64::Z27, AArch64::Z28, AArch64::Z29, AArch64::Z30, AArch64::Z31, |
| 3523 | }; |
| 3524 | |
| 3525 | // ZPR Bit set. |
| 3526 | const uint8_t ZPRBits[] = { |
| 3527 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 3528 | }; |
| 3529 | |
| 3530 | // FPR128_lo Register Class... |
| 3531 | const MCPhysReg FPR128_lo[] = { |
| 3532 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, |
| 3533 | }; |
| 3534 | |
| 3535 | // FPR128_lo Bit set. |
| 3536 | const uint8_t FPR128_loBits[] = { |
| 3537 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 3538 | }; |
| 3539 | |
| 3540 | // ZPR_4b Register Class... |
| 3541 | const MCPhysReg ZPR_4b[] = { |
| 3542 | AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, |
| 3543 | }; |
| 3544 | |
| 3545 | // ZPR_4b Bit set. |
| 3546 | const uint8_t ZPR_4bBits[] = { |
| 3547 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 3548 | }; |
| 3549 | |
| 3550 | // ZPR_3b Register Class... |
| 3551 | const MCPhysReg ZPR_3b[] = { |
| 3552 | AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7, |
| 3553 | }; |
| 3554 | |
| 3555 | // ZPR_3b Bit set. |
| 3556 | const uint8_t ZPR_3bBits[] = { |
| 3557 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, |
| 3558 | }; |
| 3559 | |
| 3560 | // DDD Register Class... |
| 3561 | const MCPhysReg DDD[] = { |
| 3562 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, |
| 3563 | }; |
| 3564 | |
| 3565 | // DDD Bit set. |
| 3566 | const uint8_t DDDBits[] = { |
| 3567 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 3568 | }; |
| 3569 | |
| 3570 | // DDD_with_dsub0_in_FPR64_lo Register Class... |
| 3571 | const MCPhysReg DDD_with_dsub0_in_FPR64_lo[] = { |
| 3572 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, |
| 3573 | }; |
| 3574 | |
| 3575 | // DDD_with_dsub0_in_FPR64_lo Bit set. |
| 3576 | const uint8_t DDD_with_dsub0_in_FPR64_loBits[] = { |
| 3577 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 3578 | }; |
| 3579 | |
| 3580 | // DDD_with_dsub1_in_FPR64_lo Register Class... |
| 3581 | const MCPhysReg DDD_with_dsub1_in_FPR64_lo[] = { |
| 3582 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D31_D0_D1, |
| 3583 | }; |
| 3584 | |
| 3585 | // DDD_with_dsub1_in_FPR64_lo Bit set. |
| 3586 | const uint8_t DDD_with_dsub1_in_FPR64_loBits[] = { |
| 3587 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, |
| 3588 | }; |
| 3589 | |
| 3590 | // DDD_with_dsub2_in_FPR64_lo Register Class... |
| 3591 | const MCPhysReg DDD_with_dsub2_in_FPR64_lo[] = { |
| 3592 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D30_D31_D0, AArch64::D31_D0_D1, |
| 3593 | }; |
| 3594 | |
| 3595 | // DDD_with_dsub2_in_FPR64_lo Bit set. |
| 3596 | const uint8_t DDD_with_dsub2_in_FPR64_loBits[] = { |
| 3597 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, |
| 3598 | }; |
| 3599 | |
| 3600 | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo Register Class... |
| 3601 | const MCPhysReg DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo[] = { |
| 3602 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, |
| 3603 | }; |
| 3604 | |
| 3605 | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo Bit set. |
| 3606 | const uint8_t DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits[] = { |
| 3607 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| 3608 | }; |
| 3609 | |
| 3610 | // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Register Class... |
| 3611 | const MCPhysReg DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo[] = { |
| 3612 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D31_D0_D1, |
| 3613 | }; |
| 3614 | |
| 3615 | // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Bit set. |
| 3616 | const uint8_t DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits[] = { |
| 3617 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, |
| 3618 | }; |
| 3619 | |
| 3620 | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Register Class... |
| 3621 | const MCPhysReg DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo[] = { |
| 3622 | AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, |
| 3623 | }; |
| 3624 | |
| 3625 | // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo Bit set. |
| 3626 | const uint8_t DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits[] = { |
| 3627 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, |
| 3628 | }; |
| 3629 | |
| 3630 | // DDDD Register Class... |
| 3631 | const MCPhysReg DDDD[] = { |
| 3632 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, |
| 3633 | }; |
| 3634 | |
| 3635 | // DDDD Bit set. |
| 3636 | const uint8_t DDDDBits[] = { |
| 3637 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 3638 | }; |
| 3639 | |
| 3640 | // DDDD_with_dsub0_in_FPR64_lo Register Class... |
| 3641 | const MCPhysReg DDDD_with_dsub0_in_FPR64_lo[] = { |
| 3642 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, |
| 3643 | }; |
| 3644 | |
| 3645 | // DDDD_with_dsub0_in_FPR64_lo Bit set. |
| 3646 | const uint8_t DDDD_with_dsub0_in_FPR64_loBits[] = { |
| 3647 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 3648 | }; |
| 3649 | |
| 3650 | // DDDD_with_dsub1_in_FPR64_lo Register Class... |
| 3651 | const MCPhysReg DDDD_with_dsub1_in_FPR64_lo[] = { |
| 3652 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D31_D0_D1_D2, |
| 3653 | }; |
| 3654 | |
| 3655 | // DDDD_with_dsub1_in_FPR64_lo Bit set. |
| 3656 | const uint8_t DDDD_with_dsub1_in_FPR64_loBits[] = { |
| 3657 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, |
| 3658 | }; |
| 3659 | |
| 3660 | // DDDD_with_dsub2_in_FPR64_lo Register Class... |
| 3661 | const MCPhysReg DDDD_with_dsub2_in_FPR64_lo[] = { |
| 3662 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, |
| 3663 | }; |
| 3664 | |
| 3665 | // DDDD_with_dsub2_in_FPR64_lo Bit set. |
| 3666 | const uint8_t DDDD_with_dsub2_in_FPR64_loBits[] = { |
| 3667 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, |
| 3668 | }; |
| 3669 | |
| 3670 | // DDDD_with_dsub3_in_FPR64_lo Register Class... |
| 3671 | const MCPhysReg DDDD_with_dsub3_in_FPR64_lo[] = { |
| 3672 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, |
| 3673 | }; |
| 3674 | |
| 3675 | // DDDD_with_dsub3_in_FPR64_lo Bit set. |
| 3676 | const uint8_t DDDD_with_dsub3_in_FPR64_loBits[] = { |
| 3677 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x38, |
| 3678 | }; |
| 3679 | |
| 3680 | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo Register Class... |
| 3681 | const MCPhysReg DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo[] = { |
| 3682 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, |
| 3683 | }; |
| 3684 | |
| 3685 | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo Bit set. |
| 3686 | const uint8_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits[] = { |
| 3687 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| 3688 | }; |
| 3689 | |
| 3690 | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Register Class... |
| 3691 | const MCPhysReg DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo[] = { |
| 3692 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D31_D0_D1_D2, |
| 3693 | }; |
| 3694 | |
| 3695 | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Bit set. |
| 3696 | const uint8_t DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits[] = { |
| 3697 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, |
| 3698 | }; |
| 3699 | |
| 3700 | // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class... |
| 3701 | const MCPhysReg DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = { |
| 3702 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, |
| 3703 | }; |
| 3704 | |
| 3705 | // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set. |
| 3706 | const uint8_t DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = { |
| 3707 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x30, |
| 3708 | }; |
| 3709 | |
| 3710 | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Register Class... |
| 3711 | const MCPhysReg DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo[] = { |
| 3712 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, |
| 3713 | }; |
| 3714 | |
| 3715 | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo Bit set. |
| 3716 | const uint8_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits[] = { |
| 3717 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, |
| 3718 | }; |
| 3719 | |
| 3720 | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class... |
| 3721 | const MCPhysReg DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = { |
| 3722 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D31_D0_D1_D2, |
| 3723 | }; |
| 3724 | |
| 3725 | // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set. |
| 3726 | const uint8_t DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = { |
| 3727 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x20, |
| 3728 | }; |
| 3729 | |
| 3730 | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Register Class... |
| 3731 | const MCPhysReg DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo[] = { |
| 3732 | AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, |
| 3733 | }; |
| 3734 | |
| 3735 | // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo Bit set. |
| 3736 | const uint8_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits[] = { |
| 3737 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, |
| 3738 | }; |
| 3739 | |
| 3740 | // QQ Register Class... |
| 3741 | const MCPhysReg QQ[] = { |
| 3742 | AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, |
| 3743 | }; |
| 3744 | |
| 3745 | // QQ Bit set. |
| 3746 | const uint8_t QQBits[] = { |
| 3747 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 3748 | }; |
| 3749 | |
| 3750 | // ZPR2 Register Class... |
| 3751 | const MCPhysReg ZPR2[] = { |
| 3752 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, AArch64::Z16_Z17, AArch64::Z17_Z18, AArch64::Z18_Z19, AArch64::Z19_Z20, AArch64::Z20_Z21, AArch64::Z21_Z22, AArch64::Z22_Z23, AArch64::Z23_Z24, AArch64::Z24_Z25, AArch64::Z25_Z26, AArch64::Z26_Z27, AArch64::Z27_Z28, AArch64::Z28_Z29, AArch64::Z29_Z30, AArch64::Z30_Z31, AArch64::Z31_Z0, |
| 3753 | }; |
| 3754 | |
| 3755 | // ZPR2 Bit set. |
| 3756 | const uint8_t ZPR2Bits[] = { |
| 3757 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 3758 | }; |
| 3759 | |
| 3760 | // QQ_with_dsub_in_FPR64_lo Register Class... |
| 3761 | const MCPhysReg QQ_with_dsub_in_FPR64_lo[] = { |
| 3762 | AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, |
| 3763 | }; |
| 3764 | |
| 3765 | // QQ_with_dsub_in_FPR64_lo Bit set. |
| 3766 | const uint8_t QQ_with_dsub_in_FPR64_loBits[] = { |
| 3767 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 3768 | }; |
| 3769 | |
| 3770 | // QQ_with_qsub1_in_FPR128_lo Register Class... |
| 3771 | const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = { |
| 3772 | AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, |
| 3773 | }; |
| 3774 | |
| 3775 | // QQ_with_qsub1_in_FPR128_lo Bit set. |
| 3776 | const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = { |
| 3777 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, |
| 3778 | }; |
| 3779 | |
| 3780 | // ZPR2_with_dsub_in_FPR64_lo Register Class... |
| 3781 | const MCPhysReg ZPR2_with_dsub_in_FPR64_lo[] = { |
| 3782 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z15_Z16, |
| 3783 | }; |
| 3784 | |
| 3785 | // ZPR2_with_dsub_in_FPR64_lo Bit set. |
| 3786 | const uint8_t ZPR2_with_dsub_in_FPR64_loBits[] = { |
| 3787 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 3788 | }; |
| 3789 | |
| 3790 | // ZPR2_with_zsub1_in_ZPR_4b Register Class... |
| 3791 | const MCPhysReg ZPR2_with_zsub1_in_ZPR_4b[] = { |
| 3792 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, AArch64::Z31_Z0, |
| 3793 | }; |
| 3794 | |
| 3795 | // ZPR2_with_zsub1_in_ZPR_4b Bit set. |
| 3796 | const uint8_t ZPR2_with_zsub1_in_ZPR_4bBits[] = { |
| 3797 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 0x00, 0x02, |
| 3798 | }; |
| 3799 | |
| 3800 | // QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class... |
| 3801 | const MCPhysReg QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo[] = { |
| 3802 | AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, |
| 3803 | }; |
| 3804 | |
| 3805 | // QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set. |
| 3806 | const uint8_t QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = { |
| 3807 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| 3808 | }; |
| 3809 | |
| 3810 | // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b Register Class... |
| 3811 | const MCPhysReg ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b[] = { |
| 3812 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, AArch64::Z8_Z9, AArch64::Z9_Z10, AArch64::Z10_Z11, AArch64::Z11_Z12, AArch64::Z12_Z13, AArch64::Z13_Z14, AArch64::Z14_Z15, |
| 3813 | }; |
| 3814 | |
| 3815 | // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b Bit set. |
| 3816 | const uint8_t ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits[] = { |
| 3817 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, |
| 3818 | }; |
| 3819 | |
| 3820 | // ZPR2_with_zsub0_in_ZPR_3b Register Class... |
| 3821 | const MCPhysReg ZPR2_with_zsub0_in_ZPR_3b[] = { |
| 3822 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z7_Z8, |
| 3823 | }; |
| 3824 | |
| 3825 | // ZPR2_with_zsub0_in_ZPR_3b Bit set. |
| 3826 | const uint8_t ZPR2_with_zsub0_in_ZPR_3bBits[] = { |
| 3827 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| 3828 | }; |
| 3829 | |
| 3830 | // ZPR2_with_zsub1_in_ZPR_3b Register Class... |
| 3831 | const MCPhysReg ZPR2_with_zsub1_in_ZPR_3b[] = { |
| 3832 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, AArch64::Z31_Z0, |
| 3833 | }; |
| 3834 | |
| 3835 | // ZPR2_with_zsub1_in_ZPR_3b Bit set. |
| 3836 | const uint8_t ZPR2_with_zsub1_in_ZPR_3bBits[] = { |
| 3837 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x02, |
| 3838 | }; |
| 3839 | |
| 3840 | // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b Register Class... |
| 3841 | const MCPhysReg ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b[] = { |
| 3842 | AArch64::Z0_Z1, AArch64::Z1_Z2, AArch64::Z2_Z3, AArch64::Z3_Z4, AArch64::Z4_Z5, AArch64::Z5_Z6, AArch64::Z6_Z7, |
| 3843 | }; |
| 3844 | |
| 3845 | // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b Bit set. |
| 3846 | const uint8_t ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits[] = { |
| 3847 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, |
| 3848 | }; |
| 3849 | |
| 3850 | // QQQ Register Class... |
| 3851 | const MCPhysReg QQQ[] = { |
| 3852 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, |
| 3853 | }; |
| 3854 | |
| 3855 | // QQQ Bit set. |
| 3856 | const uint8_t QQQBits[] = { |
| 3857 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 3858 | }; |
| 3859 | |
| 3860 | // ZPR3 Register Class... |
| 3861 | const MCPhysReg ZPR3[] = { |
| 3862 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, AArch64::Z16_Z17_Z18, AArch64::Z17_Z18_Z19, AArch64::Z18_Z19_Z20, AArch64::Z19_Z20_Z21, AArch64::Z20_Z21_Z22, AArch64::Z21_Z22_Z23, AArch64::Z22_Z23_Z24, AArch64::Z23_Z24_Z25, AArch64::Z24_Z25_Z26, AArch64::Z25_Z26_Z27, AArch64::Z26_Z27_Z28, AArch64::Z27_Z28_Z29, AArch64::Z28_Z29_Z30, AArch64::Z29_Z30_Z31, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, |
| 3863 | }; |
| 3864 | |
| 3865 | // ZPR3 Bit set. |
| 3866 | const uint8_t ZPR3Bits[] = { |
| 3867 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 3868 | }; |
| 3869 | |
| 3870 | // QQQ_with_dsub_in_FPR64_lo Register Class... |
| 3871 | const MCPhysReg QQQ_with_dsub_in_FPR64_lo[] = { |
| 3872 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, |
| 3873 | }; |
| 3874 | |
| 3875 | // QQQ_with_dsub_in_FPR64_lo Bit set. |
| 3876 | const uint8_t QQQ_with_dsub_in_FPR64_loBits[] = { |
| 3877 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 3878 | }; |
| 3879 | |
| 3880 | // QQQ_with_qsub1_in_FPR128_lo Register Class... |
| 3881 | const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = { |
| 3882 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, |
| 3883 | }; |
| 3884 | |
| 3885 | // QQQ_with_qsub1_in_FPR128_lo Bit set. |
| 3886 | const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = { |
| 3887 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, |
| 3888 | }; |
| 3889 | |
| 3890 | // QQQ_with_qsub2_in_FPR128_lo Register Class... |
| 3891 | const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = { |
| 3892 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, |
| 3893 | }; |
| 3894 | |
| 3895 | // QQQ_with_qsub2_in_FPR128_lo Bit set. |
| 3896 | const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = { |
| 3897 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, |
| 3898 | }; |
| 3899 | |
| 3900 | // ZPR3_with_dsub_in_FPR64_lo Register Class... |
| 3901 | const MCPhysReg ZPR3_with_dsub_in_FPR64_lo[] = { |
| 3902 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z15_Z16_Z17, |
| 3903 | }; |
| 3904 | |
| 3905 | // ZPR3_with_dsub_in_FPR64_lo Bit set. |
| 3906 | const uint8_t ZPR3_with_dsub_in_FPR64_loBits[] = { |
| 3907 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 3908 | }; |
| 3909 | |
| 3910 | // ZPR3_with_zsub1_in_ZPR_4b Register Class... |
| 3911 | const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b[] = { |
| 3912 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, AArch64::Z31_Z0_Z1, |
| 3913 | }; |
| 3914 | |
| 3915 | // ZPR3_with_zsub1_in_ZPR_4b Bit set. |
| 3916 | const uint8_t ZPR3_with_zsub1_in_ZPR_4bBits[] = { |
| 3917 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 0x00, 0x02, |
| 3918 | }; |
| 3919 | |
| 3920 | // ZPR3_with_zsub2_in_ZPR_4b Register Class... |
| 3921 | const MCPhysReg ZPR3_with_zsub2_in_ZPR_4b[] = { |
| 3922 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, |
| 3923 | }; |
| 3924 | |
| 3925 | // ZPR3_with_zsub2_in_ZPR_4b Bit set. |
| 3926 | const uint8_t ZPR3_with_zsub2_in_ZPR_4bBits[] = { |
| 3927 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x03, |
| 3928 | }; |
| 3929 | |
| 3930 | // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class... |
| 3931 | const MCPhysReg QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = { |
| 3932 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, |
| 3933 | }; |
| 3934 | |
| 3935 | // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set. |
| 3936 | const uint8_t QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = { |
| 3937 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| 3938 | }; |
| 3939 | |
| 3940 | // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... |
| 3941 | const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { |
| 3942 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, |
| 3943 | }; |
| 3944 | |
| 3945 | // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. |
| 3946 | const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { |
| 3947 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, |
| 3948 | }; |
| 3949 | |
| 3950 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b Register Class... |
| 3951 | const MCPhysReg ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b[] = { |
| 3952 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z14_Z15_Z16, |
| 3953 | }; |
| 3954 | |
| 3955 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b Bit set. |
| 3956 | const uint8_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits[] = { |
| 3957 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, |
| 3958 | }; |
| 3959 | |
| 3960 | // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... |
| 3961 | const MCPhysReg ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b[] = { |
| 3962 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, AArch64::Z31_Z0_Z1, |
| 3963 | }; |
| 3964 | |
| 3965 | // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. |
| 3966 | const uint8_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { |
| 3967 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x02, |
| 3968 | }; |
| 3969 | |
| 3970 | // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class... |
| 3971 | const MCPhysReg QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = { |
| 3972 | AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, |
| 3973 | }; |
| 3974 | |
| 3975 | // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set. |
| 3976 | const uint8_t QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = { |
| 3977 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, |
| 3978 | }; |
| 3979 | |
| 3980 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b Register Class... |
| 3981 | const MCPhysReg ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b[] = { |
| 3982 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, AArch64::Z8_Z9_Z10, AArch64::Z9_Z10_Z11, AArch64::Z10_Z11_Z12, AArch64::Z11_Z12_Z13, AArch64::Z12_Z13_Z14, AArch64::Z13_Z14_Z15, |
| 3983 | }; |
| 3984 | |
| 3985 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b Bit set. |
| 3986 | const uint8_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits[] = { |
| 3987 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, |
| 3988 | }; |
| 3989 | |
| 3990 | // ZPR3_with_zsub0_in_ZPR_3b Register Class... |
| 3991 | const MCPhysReg ZPR3_with_zsub0_in_ZPR_3b[] = { |
| 3992 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z7_Z8_Z9, |
| 3993 | }; |
| 3994 | |
| 3995 | // ZPR3_with_zsub0_in_ZPR_3b Bit set. |
| 3996 | const uint8_t ZPR3_with_zsub0_in_ZPR_3bBits[] = { |
| 3997 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| 3998 | }; |
| 3999 | |
| 4000 | // ZPR3_with_zsub1_in_ZPR_3b Register Class... |
| 4001 | const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b[] = { |
| 4002 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, AArch64::Z31_Z0_Z1, |
| 4003 | }; |
| 4004 | |
| 4005 | // ZPR3_with_zsub1_in_ZPR_3b Bit set. |
| 4006 | const uint8_t ZPR3_with_zsub1_in_ZPR_3bBits[] = { |
| 4007 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x02, |
| 4008 | }; |
| 4009 | |
| 4010 | // ZPR3_with_zsub2_in_ZPR_3b Register Class... |
| 4011 | const MCPhysReg ZPR3_with_zsub2_in_ZPR_3b[] = { |
| 4012 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z30_Z31_Z0, AArch64::Z31_Z0_Z1, |
| 4013 | }; |
| 4014 | |
| 4015 | // ZPR3_with_zsub2_in_ZPR_3b Bit set. |
| 4016 | const uint8_t ZPR3_with_zsub2_in_ZPR_3bBits[] = { |
| 4017 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x03, |
| 4018 | }; |
| 4019 | |
| 4020 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b Register Class... |
| 4021 | const MCPhysReg ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b[] = { |
| 4022 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z6_Z7_Z8, |
| 4023 | }; |
| 4024 | |
| 4025 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b Bit set. |
| 4026 | const uint8_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits[] = { |
| 4027 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, |
| 4028 | }; |
| 4029 | |
| 4030 | // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... |
| 4031 | const MCPhysReg ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b[] = { |
| 4032 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, AArch64::Z31_Z0_Z1, |
| 4033 | }; |
| 4034 | |
| 4035 | // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. |
| 4036 | const uint8_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { |
| 4037 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x02, |
| 4038 | }; |
| 4039 | |
| 4040 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b Register Class... |
| 4041 | const MCPhysReg ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b[] = { |
| 4042 | AArch64::Z0_Z1_Z2, AArch64::Z1_Z2_Z3, AArch64::Z2_Z3_Z4, AArch64::Z3_Z4_Z5, AArch64::Z4_Z5_Z6, AArch64::Z5_Z6_Z7, |
| 4043 | }; |
| 4044 | |
| 4045 | // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b Bit set. |
| 4046 | const uint8_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits[] = { |
| 4047 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, |
| 4048 | }; |
| 4049 | |
| 4050 | // QQQQ Register Class... |
| 4051 | const MCPhysReg QQQQ[] = { |
| 4052 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, |
| 4053 | }; |
| 4054 | |
| 4055 | // QQQQ Bit set. |
| 4056 | const uint8_t QQQQBits[] = { |
| 4057 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, |
| 4058 | }; |
| 4059 | |
| 4060 | // ZPR4 Register Class... |
| 4061 | const MCPhysReg ZPR4[] = { |
| 4062 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, AArch64::Z16_Z17_Z18_Z19, AArch64::Z17_Z18_Z19_Z20, AArch64::Z18_Z19_Z20_Z21, AArch64::Z19_Z20_Z21_Z22, AArch64::Z20_Z21_Z22_Z23, AArch64::Z21_Z22_Z23_Z24, AArch64::Z22_Z23_Z24_Z25, AArch64::Z23_Z24_Z25_Z26, AArch64::Z24_Z25_Z26_Z27, AArch64::Z25_Z26_Z27_Z28, AArch64::Z26_Z27_Z28_Z29, AArch64::Z27_Z28_Z29_Z30, AArch64::Z28_Z29_Z30_Z31, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4063 | }; |
| 4064 | |
| 4065 | // ZPR4 Bit set. |
| 4066 | const uint8_t ZPR4Bits[] = { |
| 4067 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, |
| 4068 | }; |
| 4069 | |
| 4070 | // QQQQ_with_dsub_in_FPR64_lo Register Class... |
| 4071 | const MCPhysReg QQQQ_with_dsub_in_FPR64_lo[] = { |
| 4072 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, |
| 4073 | }; |
| 4074 | |
| 4075 | // QQQQ_with_dsub_in_FPR64_lo Bit set. |
| 4076 | const uint8_t QQQQ_with_dsub_in_FPR64_loBits[] = { |
| 4077 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, |
| 4078 | }; |
| 4079 | |
| 4080 | // QQQQ_with_qsub1_in_FPR128_lo Register Class... |
| 4081 | const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = { |
| 4082 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, |
| 4083 | }; |
| 4084 | |
| 4085 | // QQQQ_with_qsub1_in_FPR128_lo Bit set. |
| 4086 | const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = { |
| 4087 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, 0x00, 0x20, |
| 4088 | }; |
| 4089 | |
| 4090 | // QQQQ_with_qsub2_in_FPR128_lo Register Class... |
| 4091 | const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = { |
| 4092 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, |
| 4093 | }; |
| 4094 | |
| 4095 | // QQQQ_with_qsub2_in_FPR128_lo Bit set. |
| 4096 | const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = { |
| 4097 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x30, |
| 4098 | }; |
| 4099 | |
| 4100 | // QQQQ_with_qsub3_in_FPR128_lo Register Class... |
| 4101 | const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = { |
| 4102 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, |
| 4103 | }; |
| 4104 | |
| 4105 | // QQQQ_with_qsub3_in_FPR128_lo Bit set. |
| 4106 | const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = { |
| 4107 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x38, |
| 4108 | }; |
| 4109 | |
| 4110 | // ZPR4_with_dsub_in_FPR64_lo Register Class... |
| 4111 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo[] = { |
| 4112 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z15_Z16_Z17_Z18, |
| 4113 | }; |
| 4114 | |
| 4115 | // ZPR4_with_dsub_in_FPR64_lo Bit set. |
| 4116 | const uint8_t ZPR4_with_dsub_in_FPR64_loBits[] = { |
| 4117 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, |
| 4118 | }; |
| 4119 | |
| 4120 | // ZPR4_with_zsub1_in_ZPR_4b Register Class... |
| 4121 | const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b[] = { |
| 4122 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, AArch64::Z31_Z0_Z1_Z2, |
| 4123 | }; |
| 4124 | |
| 4125 | // ZPR4_with_zsub1_in_ZPR_4b Bit set. |
| 4126 | const uint8_t ZPR4_with_zsub1_in_ZPR_4bBits[] = { |
| 4127 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, 0x00, 0x02, |
| 4128 | }; |
| 4129 | |
| 4130 | // ZPR4_with_zsub2_in_ZPR_4b Register Class... |
| 4131 | const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b[] = { |
| 4132 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4133 | }; |
| 4134 | |
| 4135 | // ZPR4_with_zsub2_in_ZPR_4b Bit set. |
| 4136 | const uint8_t ZPR4_with_zsub2_in_ZPR_4bBits[] = { |
| 4137 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x03, |
| 4138 | }; |
| 4139 | |
| 4140 | // ZPR4_with_zsub3_in_ZPR_4b Register Class... |
| 4141 | const MCPhysReg ZPR4_with_zsub3_in_ZPR_4b[] = { |
| 4142 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4143 | }; |
| 4144 | |
| 4145 | // ZPR4_with_zsub3_in_ZPR_4b Bit set. |
| 4146 | const uint8_t ZPR4_with_zsub3_in_ZPR_4bBits[] = { |
| 4147 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 0x00, 0x80, 0x03, |
| 4148 | }; |
| 4149 | |
| 4150 | // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class... |
| 4151 | const MCPhysReg QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = { |
| 4152 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, |
| 4153 | }; |
| 4154 | |
| 4155 | // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set. |
| 4156 | const uint8_t QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = { |
| 4157 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x1f, |
| 4158 | }; |
| 4159 | |
| 4160 | // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... |
| 4161 | const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { |
| 4162 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, |
| 4163 | }; |
| 4164 | |
| 4165 | // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. |
| 4166 | const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { |
| 4167 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, 0x00, 0x20, |
| 4168 | }; |
| 4169 | |
| 4170 | // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... |
| 4171 | const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { |
| 4172 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, |
| 4173 | }; |
| 4174 | |
| 4175 | // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. |
| 4176 | const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { |
| 4177 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x30, |
| 4178 | }; |
| 4179 | |
| 4180 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b Register Class... |
| 4181 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b[] = { |
| 4182 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z14_Z15_Z16_Z17, |
| 4183 | }; |
| 4184 | |
| 4185 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b Bit set. |
| 4186 | const uint8_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits[] = { |
| 4187 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x01, |
| 4188 | }; |
| 4189 | |
| 4190 | // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... |
| 4191 | const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b[] = { |
| 4192 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, AArch64::Z31_Z0_Z1_Z2, |
| 4193 | }; |
| 4194 | |
| 4195 | // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. |
| 4196 | const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { |
| 4197 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x00, 0x00, 0x02, |
| 4198 | }; |
| 4199 | |
| 4200 | // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... |
| 4201 | const MCPhysReg ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { |
| 4202 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4203 | }; |
| 4204 | |
| 4205 | // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. |
| 4206 | const uint8_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { |
| 4207 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 0x00, 0x00, 0x03, |
| 4208 | }; |
| 4209 | |
| 4210 | // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class... |
| 4211 | const MCPhysReg QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = { |
| 4212 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, |
| 4213 | }; |
| 4214 | |
| 4215 | // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set. |
| 4216 | const uint8_t QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = { |
| 4217 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f, |
| 4218 | }; |
| 4219 | |
| 4220 | // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... |
| 4221 | const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { |
| 4222 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, |
| 4223 | }; |
| 4224 | |
| 4225 | // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. |
| 4226 | const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { |
| 4227 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, 0x00, 0x20, |
| 4228 | }; |
| 4229 | |
| 4230 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b Register Class... |
| 4231 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b[] = { |
| 4232 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z13_Z14_Z15_Z16, |
| 4233 | }; |
| 4234 | |
| 4235 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b Bit set. |
| 4236 | const uint8_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits[] = { |
| 4237 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, |
| 4238 | }; |
| 4239 | |
| 4240 | // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... |
| 4241 | const MCPhysReg ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b[] = { |
| 4242 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, AArch64::Z31_Z0_Z1_Z2, |
| 4243 | }; |
| 4244 | |
| 4245 | // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. |
| 4246 | const uint8_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { |
| 4247 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, 0x00, 0x00, 0x02, |
| 4248 | }; |
| 4249 | |
| 4250 | // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class... |
| 4251 | const MCPhysReg QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = { |
| 4252 | AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, |
| 4253 | }; |
| 4254 | |
| 4255 | // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set. |
| 4256 | const uint8_t QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = { |
| 4257 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x07, |
| 4258 | }; |
| 4259 | |
| 4260 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b Register Class... |
| 4261 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b[] = { |
| 4262 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, AArch64::Z8_Z9_Z10_Z11, AArch64::Z9_Z10_Z11_Z12, AArch64::Z10_Z11_Z12_Z13, AArch64::Z11_Z12_Z13_Z14, AArch64::Z12_Z13_Z14_Z15, |
| 4263 | }; |
| 4264 | |
| 4265 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b Bit set. |
| 4266 | const uint8_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits[] = { |
| 4267 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x7f, |
| 4268 | }; |
| 4269 | |
| 4270 | // ZPR4_with_zsub0_in_ZPR_3b Register Class... |
| 4271 | const MCPhysReg ZPR4_with_zsub0_in_ZPR_3b[] = { |
| 4272 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z7_Z8_Z9_Z10, |
| 4273 | }; |
| 4274 | |
| 4275 | // ZPR4_with_zsub0_in_ZPR_3b Bit set. |
| 4276 | const uint8_t ZPR4_with_zsub0_in_ZPR_3bBits[] = { |
| 4277 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, |
| 4278 | }; |
| 4279 | |
| 4280 | // ZPR4_with_zsub1_in_ZPR_3b Register Class... |
| 4281 | const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b[] = { |
| 4282 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, AArch64::Z31_Z0_Z1_Z2, |
| 4283 | }; |
| 4284 | |
| 4285 | // ZPR4_with_zsub1_in_ZPR_3b Bit set. |
| 4286 | const uint8_t ZPR4_with_zsub1_in_ZPR_3bBits[] = { |
| 4287 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, 0x02, |
| 4288 | }; |
| 4289 | |
| 4290 | // ZPR4_with_zsub2_in_ZPR_3b Register Class... |
| 4291 | const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b[] = { |
| 4292 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4293 | }; |
| 4294 | |
| 4295 | // ZPR4_with_zsub2_in_ZPR_3b Bit set. |
| 4296 | const uint8_t ZPR4_with_zsub2_in_ZPR_3bBits[] = { |
| 4297 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x03, |
| 4298 | }; |
| 4299 | |
| 4300 | // ZPR4_with_zsub3_in_ZPR_3b Register Class... |
| 4301 | const MCPhysReg ZPR4_with_zsub3_in_ZPR_3b[] = { |
| 4302 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z29_Z30_Z31_Z0, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4303 | }; |
| 4304 | |
| 4305 | // ZPR4_with_zsub3_in_ZPR_3b Bit set. |
| 4306 | const uint8_t ZPR4_with_zsub3_in_ZPR_3bBits[] = { |
| 4307 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x80, 0x03, |
| 4308 | }; |
| 4309 | |
| 4310 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b Register Class... |
| 4311 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b[] = { |
| 4312 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z6_Z7_Z8_Z9, |
| 4313 | }; |
| 4314 | |
| 4315 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b Bit set. |
| 4316 | const uint8_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits[] = { |
| 4317 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, |
| 4318 | }; |
| 4319 | |
| 4320 | // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... |
| 4321 | const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b[] = { |
| 4322 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, AArch64::Z31_Z0_Z1_Z2, |
| 4323 | }; |
| 4324 | |
| 4325 | // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. |
| 4326 | const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { |
| 4327 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x00, 0x00, 0x02, |
| 4328 | }; |
| 4329 | |
| 4330 | // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... |
| 4331 | const MCPhysReg ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { |
| 4332 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z30_Z31_Z0_Z1, AArch64::Z31_Z0_Z1_Z2, |
| 4333 | }; |
| 4334 | |
| 4335 | // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. |
| 4336 | const uint8_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { |
| 4337 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x03, |
| 4338 | }; |
| 4339 | |
| 4340 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b Register Class... |
| 4341 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b[] = { |
| 4342 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z5_Z6_Z7_Z8, |
| 4343 | }; |
| 4344 | |
| 4345 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b Bit set. |
| 4346 | const uint8_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits[] = { |
| 4347 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, |
| 4348 | }; |
| 4349 | |
| 4350 | // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... |
| 4351 | const MCPhysReg ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b[] = { |
| 4352 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, AArch64::Z31_Z0_Z1_Z2, |
| 4353 | }; |
| 4354 | |
| 4355 | // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. |
| 4356 | const uint8_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { |
| 4357 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x02, |
| 4358 | }; |
| 4359 | |
| 4360 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b Register Class... |
| 4361 | const MCPhysReg ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b[] = { |
| 4362 | AArch64::Z0_Z1_Z2_Z3, AArch64::Z1_Z2_Z3_Z4, AArch64::Z2_Z3_Z4_Z5, AArch64::Z3_Z4_Z5_Z6, AArch64::Z4_Z5_Z6_Z7, |
| 4363 | }; |
| 4364 | |
| 4365 | // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b Bit set. |
| 4366 | const uint8_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits[] = { |
| 4367 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, |
| 4368 | }; |
| 4369 | |
| 4370 | } // end anonymous namespace |
| 4371 | |
| 4372 | |
| 4373 | #ifdef __GNUC__ |
| 4374 | #pragma GCC diagnostic push |
| 4375 | #pragma GCC diagnostic ignored "-Woverlength-strings" |
| 4376 | #endif |
| 4377 | extern const char AArch64RegClassStrings[] = { |
| 4378 | /* 0 */ "FPR32\0" |
| 4379 | /* 6 */ "GPR32\0" |
| 4380 | /* 12 */ "ZPR2\0" |
| 4381 | /* 17 */ "ZPR3\0" |
| 4382 | /* 22 */ "FPR64\0" |
| 4383 | /* 28 */ "GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64\0" |
| 4384 | /* 79 */ "GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64\0" |
| 4385 | /* 130 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64\0" |
| 4386 | /* 181 */ "GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64\0" |
| 4387 | /* 232 */ "XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64\0" |
| 4388 | /* 284 */ "XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64\0" |
| 4389 | /* 336 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64\0" |
| 4390 | /* 387 */ "GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64\0" |
| 4391 | /* 438 */ "GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64\0" |
| 4392 | /* 489 */ "GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64\0" |
| 4393 | /* 540 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64\0" |
| 4394 | /* 577 */ "GPR64x8Class_with_x8sub_1_in_tcGPR64\0" |
| 4395 | /* 614 */ "XSeqPairsClass_with_sube64_in_tcGPR64\0" |
| 4396 | /* 652 */ "XSeqPairsClass_with_subo64_in_tcGPR64\0" |
| 4397 | /* 690 */ "GPR64x8Class_with_x8sub_0_in_rtcGPR64\0" |
| 4398 | /* 728 */ "GPR64x8Class_with_x8sub_2_in_rtcGPR64\0" |
| 4399 | /* 766 */ "XSeqPairsClass_with_sube64_in_rtcGPR64\0" |
| 4400 | /* 805 */ "GPR64x8Class_with_x8sub_4_in_rtcGPR64\0" |
| 4401 | /* 843 */ "GPR64x8Class_with_x8sub_6_in_rtcGPR64\0" |
| 4402 | /* 881 */ "ZPR4\0" |
| 4403 | /* 886 */ "FPR16\0" |
| 4404 | /* 892 */ "FPR128\0" |
| 4405 | /* 899 */ "FPR8\0" |
| 4406 | /* 904 */ "DDDD\0" |
| 4407 | /* 909 */ "QQQQ\0" |
| 4408 | /* 914 */ "CCR\0" |
| 4409 | /* 918 */ "PPR\0" |
| 4410 | /* 922 */ "ZPR\0" |
| 4411 | /* 926 */ "PPR_3b\0" |
| 4412 | /* 933 */ "ZPR2_with_zsub0_in_ZPR_3b\0" |
| 4413 | /* 959 */ "ZPR3_with_zsub0_in_ZPR_3b\0" |
| 4414 | /* 985 */ "ZPR4_with_zsub0_in_ZPR_3b\0" |
| 4415 | /* 1011 */ "ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b\0" |
| 4416 | /* 1068 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b\0" |
| 4417 | /* 1125 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b\0" |
| 4418 | /* 1182 */ "ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b\0" |
| 4419 | /* 1238 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b\0" |
| 4420 | /* 1295 */ "ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b\0" |
| 4421 | /* 1351 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b\0" |
| 4422 | /* 1408 */ "ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b\0" |
| 4423 | /* 1464 */ "ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b\0" |
| 4424 | /* 1520 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b\0" |
| 4425 | /* 1577 */ "ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b\0" |
| 4426 | /* 1634 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b\0" |
| 4427 | /* 1691 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b\0" |
| 4428 | /* 1748 */ "ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b\0" |
| 4429 | /* 1804 */ "ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b\0" |
| 4430 | /* 1861 */ "ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b\0" |
| 4431 | /* 1917 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b\0" |
| 4432 | /* 1974 */ "ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b\0" |
| 4433 | /* 2030 */ "ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b\0" |
| 4434 | /* 2086 */ "ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b\0" |
| 4435 | /* 2143 */ "GPR64x8Class_with_sub_32_in_GPR32arg\0" |
| 4436 | /* 2180 */ "XSeqPairsClass_with_sub_32_in_GPR32arg\0" |
| 4437 | /* 2219 */ "WSeqPairsClass_with_sube32_in_GPR32arg\0" |
| 4438 | /* 2258 */ "GPR64x8Class_with_x8sub_2_in_GPR64arg\0" |
| 4439 | /* 2296 */ "GPR64x8Class_with_x8sub_4_in_GPR64arg\0" |
| 4440 | /* 2334 */ "GPR64x8Class_with_x8sub_6_in_GPR64arg\0" |
| 4441 | /* 2372 */ "GPR32all\0" |
| 4442 | /* 2381 */ "GPR64all\0" |
| 4443 | /* 2390 */ "WSeqPairsClass_with_subo32_in_GPR32common\0" |
| 4444 | /* 2432 */ "XSeqPairsClass_with_subo64_in_GPR64common\0" |
| 4445 | /* 2474 */ "DDDD_with_dsub0_in_FPR64_lo\0" |
| 4446 | /* 2502 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo\0" |
| 4447 | /* 2562 */ "DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo\0" |
| 4448 | /* 2620 */ "DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo\0" |
| 4449 | /* 2676 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo\0" |
| 4450 | /* 2736 */ "DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo\0" |
| 4451 | /* 2796 */ "DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo\0" |
| 4452 | /* 2854 */ "DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo\0" |
| 4453 | /* 2912 */ "DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\0" |
| 4454 | /* 2972 */ "DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\0" |
| 4455 | /* 3032 */ "DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo\0" |
| 4456 | /* 3092 */ "ZPR2_with_dsub_in_FPR64_lo\0" |
| 4457 | /* 3119 */ "ZPR3_with_dsub_in_FPR64_lo\0" |
| 4458 | /* 3146 */ "ZPR4_with_dsub_in_FPR64_lo\0" |
| 4459 | /* 3173 */ "QQQQ_with_dsub_in_FPR64_lo\0" |
| 4460 | /* 3200 */ "FPR32_with_hsub_in_FPR16_lo\0" |
| 4461 | /* 3228 */ "QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo\0" |
| 4462 | /* 3288 */ "QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo\0" |
| 4463 | /* 3346 */ "QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo\0" |
| 4464 | /* 3402 */ "QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo\0" |
| 4465 | /* 3462 */ "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo\0" |
| 4466 | /* 3524 */ "QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo\0" |
| 4467 | /* 3582 */ "QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo\0" |
| 4468 | /* 3642 */ "QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo\0" |
| 4469 | /* 3702 */ "QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo\0" |
| 4470 | /* 3764 */ "QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo\0" |
| 4471 | /* 3826 */ "GPR64common_and_GPR64noip\0" |
| 4472 | /* 3852 */ "GPR64x8Class_with_x8sub_0_in_GPR64noip\0" |
| 4473 | /* 3891 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip\0" |
| 4474 | /* 3971 */ "GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip\0" |
| 4475 | /* 4094 */ "XSeqPairsClass_with_sube64_in_GPR64noip\0" |
| 4476 | /* 4134 */ "XSeqPairsClass_with_subo64_in_GPR64noip\0" |
| 4477 | /* 4174 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" |
| 4478 | /* 4297 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" |
| 4479 | /* 4420 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" |
| 4480 | /* 4586 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" |
| 4481 | /* 4711 */ "GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip\0" |
| 4482 | /* 4793 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4483 | /* 4959 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4484 | /* 5082 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4485 | /* 5248 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4486 | /* 5371 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4487 | /* 5580 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4488 | /* 5746 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4489 | /* 5912 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4490 | /* 6080 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4491 | /* 6205 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4492 | /* 6330 */ "GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip\0" |
| 4493 | /* 6412 */ "GPR32sp\0" |
| 4494 | /* 6420 */ "GPR64sp\0" |
| 4495 | /* 6428 */ "GPR64x8Class\0" |
| 4496 | /* 6441 */ "WSeqPairsClass\0" |
| 4497 | /* 6456 */ "XSeqPairsClass\0" |
| 4498 | /* 6471 */ "GPR32sponly\0" |
| 4499 | /* 6483 */ "GPR64sponly\0" |
| 4500 | }; |
| 4501 | #ifdef __GNUC__ |
| 4502 | #pragma GCC diagnostic pop |
| 4503 | #endif |
| 4504 | |
| 4505 | extern const MCRegisterClass AArch64MCRegisterClasses[] = { |
| 4506 | { FPR8, FPR8Bits, 899, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, true }, |
| 4507 | { FPR16, FPR16Bits, 886, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 1, true }, |
| 4508 | { FPR16_lo, FPR16_loBits, 3219, 16, sizeof(FPR16_loBits), AArch64::FPR16_loRegClassID, 1, true }, |
| 4509 | { PPR, PPRBits, 918, 16, sizeof(PPRBits), AArch64::PPRRegClassID, 1, true }, |
| 4510 | { PPR_3b, PPR_3bBits, 926, 8, sizeof(PPR_3bBits), AArch64::PPR_3bRegClassID, 1, true }, |
| 4511 | { GPR32all, GPR32allBits, 2372, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 1, true }, |
| 4512 | { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 1, true }, |
| 4513 | { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 1, true }, |
| 4514 | { GPR32sp, GPR32spBits, 6412, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 1, true }, |
| 4515 | { GPR32common, GPR32commonBits, 2420, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 1, true }, |
| 4516 | { FPR32_with_hsub_in_FPR16_lo, FPR32_with_hsub_in_FPR16_loBits, 3200, 16, sizeof(FPR32_with_hsub_in_FPR16_loBits), AArch64::FPR32_with_hsub_in_FPR16_loRegClassID, 1, true }, |
| 4517 | { GPR32arg, GPR32argBits, 2171, 8, sizeof(GPR32argBits), AArch64::GPR32argRegClassID, 1, true }, |
| 4518 | { CCR, CCRBits, 914, 1, sizeof(CCRBits), AArch64::CCRRegClassID, -1, false }, |
| 4519 | { GPR32sponly, GPR32sponlyBits, 6471, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 1, true }, |
| 4520 | { WSeqPairsClass, WSeqPairsClassBits, 6441, 16, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 1, true }, |
| 4521 | { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 2390, 15, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 1, true }, |
| 4522 | { WSeqPairsClass_with_sube32_in_GPR32arg, WSeqPairsClass_with_sube32_in_GPR32argBits, 2219, 4, sizeof(WSeqPairsClass_with_sube32_in_GPR32argBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClassID, 1, true }, |
| 4523 | { GPR64all, GPR64allBits, 2381, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 1, true }, |
| 4524 | { FPR64, FPR64Bits, 22, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 1, true }, |
| 4525 | { GPR64, GPR64Bits, 73, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 1, true }, |
| 4526 | { GPR64sp, GPR64spBits, 6420, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 1, true }, |
| 4527 | { GPR64common, GPR64commonBits, 2462, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 1, true }, |
| 4528 | { GPR64noip, GPR64noipBits, 3842, 29, sizeof(GPR64noipBits), AArch64::GPR64noipRegClassID, 1, true }, |
| 4529 | { GPR64common_and_GPR64noip, GPR64common_and_GPR64noipBits, 3826, 28, sizeof(GPR64common_and_GPR64noipBits), AArch64::GPR64common_and_GPR64noipRegClassID, 1, true }, |
| 4530 | { tcGPR64, tcGPR64Bits, 71, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 1, true }, |
| 4531 | { GPR64noip_and_tcGPR64, GPR64noip_and_tcGPR64Bits, 57, 17, sizeof(GPR64noip_and_tcGPR64Bits), AArch64::GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4532 | { FPR64_lo, FPR64_loBits, 2493, 16, sizeof(FPR64_loBits), AArch64::FPR64_loRegClassID, 1, true }, |
| 4533 | { GPR64x8Class, GPR64x8ClassBits, 6428, 12, sizeof(GPR64x8ClassBits), AArch64::GPR64x8ClassRegClassID, 1, true }, |
| 4534 | { GPR64x8Class_with_x8sub_0_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_GPR64noipBits, 3852, 11, sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClassID, 1, true }, |
| 4535 | { GPR64x8Class_with_x8sub_2_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noipBits, 3932, 11, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, 1, true }, |
| 4536 | { GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4258, 11, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4537 | { GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 4920, 11, sizeof(GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4538 | { GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, 4012, 10, sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, 1, true }, |
| 4539 | { GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4504, 10, sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4540 | { GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5498, 10, sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4541 | { GPR64x8Class_with_x8sub_0_in_tcGPR64, GPR64x8Class_with_x8sub_0_in_tcGPR64Bits, 540, 10, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClassID, 1, true }, |
| 4542 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4711, 10, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4543 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 6248, 10, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4544 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 6330, 10, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4545 | { GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Bits, 28, 9, sizeof(GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4546 | { GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, 3891, 9, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, 1, true }, |
| 4547 | { GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4217, 9, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4548 | { GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 4879, 9, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4549 | { GPR64x8Class_with_x8sub_1_in_tcGPR64, GPR64x8Class_with_x8sub_1_in_tcGPR64Bits, 577, 9, sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClassID, 1, true }, |
| 4550 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4586, 9, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4551 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5955, 9, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4552 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 6080, 9, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4553 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 6205, 9, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4554 | { GPR64arg, GPR64argBits, 2287, 8, sizeof(GPR64argBits), AArch64::GPR64argRegClassID, 1, true }, |
| 4555 | { GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits, 3971, 8, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID, 1, true }, |
| 4556 | { GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4463, 8, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4557 | { GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5457, 8, sizeof(GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4558 | { GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Bits, 79, 8, sizeof(GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4559 | { GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4340, 8, sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4560 | { GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5168, 8, sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4561 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4174, 8, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4562 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 4836, 8, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4563 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Bits, 130, 8, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4564 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 4959, 8, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4565 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5912, 8, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4566 | { GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5789, 7, sizeof(GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4567 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4420, 7, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4568 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5414, 7, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4569 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits, 4297, 7, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID, 1, true }, |
| 4570 | { GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5125, 7, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4571 | { GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Bits, 181, 7, sizeof(GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4572 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5580, 7, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4573 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5248, 7, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4574 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 4793, 7, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4575 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Bits, 336, 7, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4576 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5746, 6, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4577 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5371, 6, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4578 | { GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip, GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits, 5082, 6, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID, 1, true }, |
| 4579 | { GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Bits, 387, 6, sizeof(GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4580 | { GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Bits, 438, 6, sizeof(GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4581 | { GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64, GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Bits, 489, 5, sizeof(GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4582 | { GPR64x8Class_with_sub_32_in_GPR32arg, GPR64x8Class_with_sub_32_in_GPR32argBits, 2143, 4, sizeof(GPR64x8Class_with_sub_32_in_GPR32argBits), AArch64::GPR64x8Class_with_sub_32_in_GPR32argRegClassID, 1, true }, |
| 4583 | { GPR64x8Class_with_x8sub_2_in_GPR64arg, GPR64x8Class_with_x8sub_2_in_GPR64argBits, 2258, 3, sizeof(GPR64x8Class_with_x8sub_2_in_GPR64argBits), AArch64::GPR64x8Class_with_x8sub_2_in_GPR64argRegClassID, 1, true }, |
| 4584 | { GPR64x8Class_with_x8sub_4_in_GPR64arg, GPR64x8Class_with_x8sub_4_in_GPR64argBits, 2296, 2, sizeof(GPR64x8Class_with_x8sub_4_in_GPR64argBits), AArch64::GPR64x8Class_with_x8sub_4_in_GPR64argRegClassID, 1, true }, |
| 4585 | { rtcGPR64, rtcGPR64Bits, 719, 2, sizeof(rtcGPR64Bits), AArch64::rtcGPR64RegClassID, 1, true }, |
| 4586 | { GPR64sponly, GPR64sponlyBits, 6483, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 1, true }, |
| 4587 | { GPR64x8Class_with_x8sub_0_in_rtcGPR64, GPR64x8Class_with_x8sub_0_in_rtcGPR64Bits, 690, 1, sizeof(GPR64x8Class_with_x8sub_0_in_rtcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClassID, 1, true }, |
| 4588 | { GPR64x8Class_with_x8sub_2_in_rtcGPR64, GPR64x8Class_with_x8sub_2_in_rtcGPR64Bits, 728, 1, sizeof(GPR64x8Class_with_x8sub_2_in_rtcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClassID, 1, true }, |
| 4589 | { GPR64x8Class_with_x8sub_4_in_rtcGPR64, GPR64x8Class_with_x8sub_4_in_rtcGPR64Bits, 805, 1, sizeof(GPR64x8Class_with_x8sub_4_in_rtcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClassID, 1, true }, |
| 4590 | { GPR64x8Class_with_x8sub_6_in_GPR64arg, GPR64x8Class_with_x8sub_6_in_GPR64argBits, 2334, 1, sizeof(GPR64x8Class_with_x8sub_6_in_GPR64argBits), AArch64::GPR64x8Class_with_x8sub_6_in_GPR64argRegClassID, 1, true }, |
| 4591 | { GPR64x8Class_with_x8sub_6_in_rtcGPR64, GPR64x8Class_with_x8sub_6_in_rtcGPR64Bits, 843, 1, sizeof(GPR64x8Class_with_x8sub_6_in_rtcGPR64Bits), AArch64::GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClassID, 1, true }, |
| 4592 | { DD, DDBits, 906, 32, sizeof(DDBits), AArch64::DDRegClassID, 1, true }, |
| 4593 | { DD_with_dsub0_in_FPR64_lo, DD_with_dsub0_in_FPR64_loBits, 2476, 16, sizeof(DD_with_dsub0_in_FPR64_loBits), AArch64::DD_with_dsub0_in_FPR64_loRegClassID, 1, true }, |
| 4594 | { DD_with_dsub1_in_FPR64_lo, DD_with_dsub1_in_FPR64_loBits, 2536, 16, sizeof(DD_with_dsub1_in_FPR64_loBits), AArch64::DD_with_dsub1_in_FPR64_loRegClassID, 1, true }, |
| 4595 | { XSeqPairsClass, XSeqPairsClassBits, 6456, 16, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 1, true }, |
| 4596 | { DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo, DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits, 2620, 15, sizeof(DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loBits), AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID, 1, true }, |
| 4597 | { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 2432, 15, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 1, true }, |
| 4598 | { XSeqPairsClass_with_subo64_in_GPR64noip, XSeqPairsClass_with_subo64_in_GPR64noipBits, 4134, 15, sizeof(XSeqPairsClass_with_subo64_in_GPR64noipBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClassID, 1, true }, |
| 4599 | { XSeqPairsClass_with_sube64_in_GPR64noip, XSeqPairsClass_with_sube64_in_GPR64noipBits, 4094, 14, sizeof(XSeqPairsClass_with_sube64_in_GPR64noipBits), AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClassID, 1, true }, |
| 4600 | { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 614, 10, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 1, true }, |
| 4601 | { XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64, XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits, 232, 9, sizeof(XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4602 | { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 652, 9, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 1, true }, |
| 4603 | { XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64, XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits, 284, 8, sizeof(XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID, 1, true }, |
| 4604 | { XSeqPairsClass_with_sub_32_in_GPR32arg, XSeqPairsClass_with_sub_32_in_GPR32argBits, 2180, 4, sizeof(XSeqPairsClass_with_sub_32_in_GPR32argBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClassID, 1, true }, |
| 4605 | { XSeqPairsClass_with_sube64_in_rtcGPR64, XSeqPairsClass_with_sube64_in_rtcGPR64Bits, 766, 1, sizeof(XSeqPairsClass_with_sube64_in_rtcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID, 1, true }, |
| 4606 | { FPR128, FPR128Bits, 892, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 1, true }, |
| 4607 | { ZPR, ZPRBits, 922, 32, sizeof(ZPRBits), AArch64::ZPRRegClassID, 1, true }, |
| 4608 | { FPR128_lo, FPR128_loBits, 3278, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 1, true }, |
| 4609 | { ZPR_4b, ZPR_4bBits, 1627, 16, sizeof(ZPR_4bBits), AArch64::ZPR_4bRegClassID, 1, true }, |
| 4610 | { ZPR_3b, ZPR_3bBits, 952, 8, sizeof(ZPR_3bBits), AArch64::ZPR_3bRegClassID, 1, true }, |
| 4611 | { DDD, DDDBits, 905, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 1, true }, |
| 4612 | { DDD_with_dsub0_in_FPR64_lo, DDD_with_dsub0_in_FPR64_loBits, 2475, 16, sizeof(DDD_with_dsub0_in_FPR64_loBits), AArch64::DDD_with_dsub0_in_FPR64_loRegClassID, 1, true }, |
| 4613 | { DDD_with_dsub1_in_FPR64_lo, DDD_with_dsub1_in_FPR64_loBits, 2535, 16, sizeof(DDD_with_dsub1_in_FPR64_loBits), AArch64::DDD_with_dsub1_in_FPR64_loRegClassID, 1, true }, |
| 4614 | { DDD_with_dsub2_in_FPR64_lo, DDD_with_dsub2_in_FPR64_loBits, 2709, 16, sizeof(DDD_with_dsub2_in_FPR64_loBits), AArch64::DDD_with_dsub2_in_FPR64_loRegClassID, 1, true }, |
| 4615 | { DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo, DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits, 2562, 15, sizeof(DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loBits), AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID, 1, true }, |
| 4616 | { DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo, DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits, 2854, 15, sizeof(DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits), AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID, 1, true }, |
| 4617 | { DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo, DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits, 2796, 14, sizeof(DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loBits), AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID, 1, true }, |
| 4618 | { DDDD, DDDDBits, 904, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 1, true }, |
| 4619 | { DDDD_with_dsub0_in_FPR64_lo, DDDD_with_dsub0_in_FPR64_loBits, 2474, 16, sizeof(DDDD_with_dsub0_in_FPR64_loBits), AArch64::DDDD_with_dsub0_in_FPR64_loRegClassID, 1, true }, |
| 4620 | { DDDD_with_dsub1_in_FPR64_lo, DDDD_with_dsub1_in_FPR64_loBits, 2534, 16, sizeof(DDDD_with_dsub1_in_FPR64_loBits), AArch64::DDDD_with_dsub1_in_FPR64_loRegClassID, 1, true }, |
| 4621 | { DDDD_with_dsub2_in_FPR64_lo, DDDD_with_dsub2_in_FPR64_loBits, 2708, 16, sizeof(DDDD_with_dsub2_in_FPR64_loBits), AArch64::DDDD_with_dsub2_in_FPR64_loRegClassID, 1, true }, |
| 4622 | { DDDD_with_dsub3_in_FPR64_lo, DDDD_with_dsub3_in_FPR64_loBits, 2944, 16, sizeof(DDDD_with_dsub3_in_FPR64_loBits), AArch64::DDDD_with_dsub3_in_FPR64_loRegClassID, 1, true }, |
| 4623 | { DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo, DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits, 2502, 15, sizeof(DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loBits), AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID, 1, true }, |
| 4624 | { DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo, DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits, 2736, 15, sizeof(DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits), AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID, 1, true }, |
| 4625 | { DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, 3032, 15, sizeof(DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits), AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID, 1, true }, |
| 4626 | { DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo, DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits, 2676, 14, sizeof(DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loBits), AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID, 1, true }, |
| 4627 | { DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, 2972, 14, sizeof(DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits), AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID, 1, true }, |
| 4628 | { DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo, DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits, 2912, 13, sizeof(DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loBits), AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID, 1, true }, |
| 4629 | { QQ, QQBits, 911, 32, sizeof(QQBits), AArch64::QQRegClassID, 1, true }, |
| 4630 | { ZPR2, ZPR2Bits, 12, 32, sizeof(ZPR2Bits), AArch64::ZPR2RegClassID, 1, true }, |
| 4631 | { QQ_with_dsub_in_FPR64_lo, QQ_with_dsub_in_FPR64_loBits, 3175, 16, sizeof(QQ_with_dsub_in_FPR64_loBits), AArch64::QQ_with_dsub_in_FPR64_loRegClassID, 1, true }, |
| 4632 | { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 3261, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 1, true }, |
| 4633 | { ZPR2_with_dsub_in_FPR64_lo, ZPR2_with_dsub_in_FPR64_loBits, 3092, 16, sizeof(ZPR2_with_dsub_in_FPR64_loBits), AArch64::ZPR2_with_dsub_in_FPR64_loRegClassID, 1, true }, |
| 4634 | { ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_zsub1_in_ZPR_4bBits, 1608, 16, sizeof(ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true }, |
| 4635 | { QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loBits, 3346, 15, sizeof(QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 1, true }, |
| 4636 | { ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b, ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits, 1577, 15, sizeof(ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bBits), AArch64::ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID, 1, true }, |
| 4637 | { ZPR2_with_zsub0_in_ZPR_3b, ZPR2_with_zsub0_in_ZPR_3bBits, 933, 8, sizeof(ZPR2_with_zsub0_in_ZPR_3bBits), AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClassID, 1, true }, |
| 4638 | { ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_zsub1_in_ZPR_3bBits, 1042, 8, sizeof(ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true }, |
| 4639 | { ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b, ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits, 1011, 7, sizeof(ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bBits), AArch64::ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID, 1, true }, |
| 4640 | { QQQ, QQQBits, 910, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 1, true }, |
| 4641 | { ZPR3, ZPR3Bits, 17, 32, sizeof(ZPR3Bits), AArch64::ZPR3RegClassID, 1, true }, |
| 4642 | { QQQ_with_dsub_in_FPR64_lo, QQQ_with_dsub_in_FPR64_loBits, 3174, 16, sizeof(QQQ_with_dsub_in_FPR64_loBits), AArch64::QQQ_with_dsub_in_FPR64_loRegClassID, 1, true }, |
| 4643 | { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 3260, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true }, |
| 4644 | { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 3434, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true }, |
| 4645 | { ZPR3_with_dsub_in_FPR64_lo, ZPR3_with_dsub_in_FPR64_loBits, 3119, 16, sizeof(ZPR3_with_dsub_in_FPR64_loBits), AArch64::ZPR3_with_dsub_in_FPR64_loRegClassID, 1, true }, |
| 4646 | { ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4bBits, 1665, 16, sizeof(ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true }, |
| 4647 | { ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub2_in_ZPR_4bBits, 1778, 16, sizeof(ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true }, |
| 4648 | { QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 3288, 15, sizeof(QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 1, true }, |
| 4649 | { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 3582, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true }, |
| 4650 | { ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b, ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits, 1634, 15, sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bBits), AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID, 1, true }, |
| 4651 | { ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1748, 15, sizeof(ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true }, |
| 4652 | { QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 3524, 14, sizeof(QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 1, true }, |
| 4653 | { ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b, ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits, 1804, 14, sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bBits), AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID, 1, true }, |
| 4654 | { ZPR3_with_zsub0_in_ZPR_3b, ZPR3_with_zsub0_in_ZPR_3bBits, 959, 8, sizeof(ZPR3_with_zsub0_in_ZPR_3bBits), AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClassID, 1, true }, |
| 4655 | { ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3bBits, 1099, 8, sizeof(ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true }, |
| 4656 | { ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub2_in_ZPR_3bBits, 1212, 8, sizeof(ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true }, |
| 4657 | { ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b, ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits, 1068, 7, sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bBits), AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID, 1, true }, |
| 4658 | { ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits, 1182, 7, sizeof(ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true }, |
| 4659 | { ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b, ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits, 1238, 6, sizeof(ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bBits), AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID, 1, true }, |
| 4660 | { QQQQ, QQQQBits, 909, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 1, true }, |
| 4661 | { ZPR4, ZPR4Bits, 881, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true }, |
| 4662 | { QQQQ_with_dsub_in_FPR64_lo, QQQQ_with_dsub_in_FPR64_loBits, 3173, 16, sizeof(QQQQ_with_dsub_in_FPR64_loBits), AArch64::QQQQ_with_dsub_in_FPR64_loRegClassID, 1, true }, |
| 4663 | { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 3259, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true }, |
| 4664 | { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 3433, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true }, |
| 4665 | { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 3673, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true }, |
| 4666 | { ZPR4_with_dsub_in_FPR64_lo, ZPR4_with_dsub_in_FPR64_loBits, 3146, 16, sizeof(ZPR4_with_dsub_in_FPR64_loBits), AArch64::ZPR4_with_dsub_in_FPR64_loRegClassID, 1, true }, |
| 4667 | { ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4bBits, 1722, 16, sizeof(ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true }, |
| 4668 | { ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4bBits, 1891, 16, sizeof(ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true }, |
| 4669 | { ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub3_in_ZPR_4bBits, 2004, 16, sizeof(ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true }, |
| 4670 | { QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 3228, 15, sizeof(QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 1, true }, |
| 4671 | { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 3462, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true }, |
| 4672 | { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 3764, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true }, |
| 4673 | { ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b, ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits, 1691, 15, sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bBits), AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID, 1, true }, |
| 4674 | { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1861, 15, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true }, |
| 4675 | { ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 2030, 15, sizeof(ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true }, |
| 4676 | { QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 3402, 14, sizeof(QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 1, true }, |
| 4677 | { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 3702, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true }, |
| 4678 | { ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b, ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits, 1917, 14, sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bBits), AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID, 1, true }, |
| 4679 | { ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits, 1974, 14, sizeof(ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true }, |
| 4680 | { QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 3642, 13, sizeof(QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 1, true }, |
| 4681 | { ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b, ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits, 2086, 13, sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bBits), AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID, 1, true }, |
| 4682 | { ZPR4_with_zsub0_in_ZPR_3b, ZPR4_with_zsub0_in_ZPR_3bBits, 985, 8, sizeof(ZPR4_with_zsub0_in_ZPR_3bBits), AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClassID, 1, true }, |
| 4683 | { ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3bBits, 1156, 8, sizeof(ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true }, |
| 4684 | { ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3bBits, 1325, 8, sizeof(ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true }, |
| 4685 | { ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub3_in_ZPR_3bBits, 1438, 8, sizeof(ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true }, |
| 4686 | { ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b, ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits, 1125, 7, sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bBits), AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID, 1, true }, |
| 4687 | { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits, 1295, 7, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true }, |
| 4688 | { ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 1464, 7, sizeof(ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true }, |
| 4689 | { ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b, ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits, 1351, 6, sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bBits), AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID, 1, true }, |
| 4690 | { ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits, 1408, 6, sizeof(ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true }, |
| 4691 | { ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b, ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits, 1520, 5, sizeof(ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bBits), AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID, 1, true }, |
| 4692 | }; |
| 4693 | |
| 4694 | // AArch64 Dwarf<->LLVM register mappings. |
| 4695 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = { |
| 4696 | { 0U, AArch64::W0 }, |
| 4697 | { 1U, AArch64::W1 }, |
| 4698 | { 2U, AArch64::W2 }, |
| 4699 | { 3U, AArch64::W3 }, |
| 4700 | { 4U, AArch64::W4 }, |
| 4701 | { 5U, AArch64::W5 }, |
| 4702 | { 6U, AArch64::W6 }, |
| 4703 | { 7U, AArch64::W7 }, |
| 4704 | { 8U, AArch64::W8 }, |
| 4705 | { 9U, AArch64::W9 }, |
| 4706 | { 10U, AArch64::W10 }, |
| 4707 | { 11U, AArch64::W11 }, |
| 4708 | { 12U, AArch64::W12 }, |
| 4709 | { 13U, AArch64::W13 }, |
| 4710 | { 14U, AArch64::W14 }, |
| 4711 | { 15U, AArch64::W15 }, |
| 4712 | { 16U, AArch64::W16 }, |
| 4713 | { 17U, AArch64::W17 }, |
| 4714 | { 18U, AArch64::W18 }, |
| 4715 | { 19U, AArch64::W19 }, |
| 4716 | { 20U, AArch64::W20 }, |
| 4717 | { 21U, AArch64::W21 }, |
| 4718 | { 22U, AArch64::W22 }, |
| 4719 | { 23U, AArch64::W23 }, |
| 4720 | { 24U, AArch64::W24 }, |
| 4721 | { 25U, AArch64::W25 }, |
| 4722 | { 26U, AArch64::W26 }, |
| 4723 | { 27U, AArch64::W27 }, |
| 4724 | { 28U, AArch64::W28 }, |
| 4725 | { 29U, AArch64::W29 }, |
| 4726 | { 30U, AArch64::W30 }, |
| 4727 | { 31U, AArch64::WSP }, |
| 4728 | { 46U, AArch64::VG }, |
| 4729 | { 47U, AArch64::FFR }, |
| 4730 | { 48U, AArch64::P0 }, |
| 4731 | { 49U, AArch64::P1 }, |
| 4732 | { 50U, AArch64::P2 }, |
| 4733 | { 51U, AArch64::P3 }, |
| 4734 | { 52U, AArch64::P4 }, |
| 4735 | { 53U, AArch64::P5 }, |
| 4736 | { 54U, AArch64::P6 }, |
| 4737 | { 55U, AArch64::P7 }, |
| 4738 | { 56U, AArch64::P8 }, |
| 4739 | { 57U, AArch64::P9 }, |
| 4740 | { 58U, AArch64::P10 }, |
| 4741 | { 59U, AArch64::P11 }, |
| 4742 | { 60U, AArch64::P12 }, |
| 4743 | { 61U, AArch64::P13 }, |
| 4744 | { 62U, AArch64::P14 }, |
| 4745 | { 63U, AArch64::P15 }, |
| 4746 | { 64U, AArch64::B0 }, |
| 4747 | { 65U, AArch64::B1 }, |
| 4748 | { 66U, AArch64::B2 }, |
| 4749 | { 67U, AArch64::B3 }, |
| 4750 | { 68U, AArch64::B4 }, |
| 4751 | { 69U, AArch64::B5 }, |
| 4752 | { 70U, AArch64::B6 }, |
| 4753 | { 71U, AArch64::B7 }, |
| 4754 | { 72U, AArch64::B8 }, |
| 4755 | { 73U, AArch64::B9 }, |
| 4756 | { 74U, AArch64::B10 }, |
| 4757 | { 75U, AArch64::B11 }, |
| 4758 | { 76U, AArch64::B12 }, |
| 4759 | { 77U, AArch64::B13 }, |
| 4760 | { 78U, AArch64::B14 }, |
| 4761 | { 79U, AArch64::B15 }, |
| 4762 | { 80U, AArch64::B16 }, |
| 4763 | { 81U, AArch64::B17 }, |
| 4764 | { 82U, AArch64::B18 }, |
| 4765 | { 83U, AArch64::B19 }, |
| 4766 | { 84U, AArch64::B20 }, |
| 4767 | { 85U, AArch64::B21 }, |
| 4768 | { 86U, AArch64::B22 }, |
| 4769 | { 87U, AArch64::B23 }, |
| 4770 | { 88U, AArch64::B24 }, |
| 4771 | { 89U, AArch64::B25 }, |
| 4772 | { 90U, AArch64::B26 }, |
| 4773 | { 91U, AArch64::B27 }, |
| 4774 | { 92U, AArch64::B28 }, |
| 4775 | { 93U, AArch64::B29 }, |
| 4776 | { 94U, AArch64::B30 }, |
| 4777 | { 95U, AArch64::B31 }, |
| 4778 | { 96U, AArch64::Z0 }, |
| 4779 | { 97U, AArch64::Z1 }, |
| 4780 | { 98U, AArch64::Z2 }, |
| 4781 | { 99U, AArch64::Z3 }, |
| 4782 | { 100U, AArch64::Z4 }, |
| 4783 | { 101U, AArch64::Z5 }, |
| 4784 | { 102U, AArch64::Z6 }, |
| 4785 | { 103U, AArch64::Z7 }, |
| 4786 | { 104U, AArch64::Z8 }, |
| 4787 | { 105U, AArch64::Z9 }, |
| 4788 | { 106U, AArch64::Z10 }, |
| 4789 | { 107U, AArch64::Z11 }, |
| 4790 | { 108U, AArch64::Z12 }, |
| 4791 | { 109U, AArch64::Z13 }, |
| 4792 | { 110U, AArch64::Z14 }, |
| 4793 | { 111U, AArch64::Z15 }, |
| 4794 | { 112U, AArch64::Z16 }, |
| 4795 | { 113U, AArch64::Z17 }, |
| 4796 | { 114U, AArch64::Z18 }, |
| 4797 | { 115U, AArch64::Z19 }, |
| 4798 | { 116U, AArch64::Z20 }, |
| 4799 | { 117U, AArch64::Z21 }, |
| 4800 | { 118U, AArch64::Z22 }, |
| 4801 | { 119U, AArch64::Z23 }, |
| 4802 | { 120U, AArch64::Z24 }, |
| 4803 | { 121U, AArch64::Z25 }, |
| 4804 | { 122U, AArch64::Z26 }, |
| 4805 | { 123U, AArch64::Z27 }, |
| 4806 | { 124U, AArch64::Z28 }, |
| 4807 | { 125U, AArch64::Z29 }, |
| 4808 | { 126U, AArch64::Z30 }, |
| 4809 | { 127U, AArch64::Z31 }, |
| 4810 | }; |
| 4811 | extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L); |
| 4812 | |
| 4813 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = { |
| 4814 | { 0U, AArch64::W0 }, |
| 4815 | { 1U, AArch64::W1 }, |
| 4816 | { 2U, AArch64::W2 }, |
| 4817 | { 3U, AArch64::W3 }, |
| 4818 | { 4U, AArch64::W4 }, |
| 4819 | { 5U, AArch64::W5 }, |
| 4820 | { 6U, AArch64::W6 }, |
| 4821 | { 7U, AArch64::W7 }, |
| 4822 | { 8U, AArch64::W8 }, |
| 4823 | { 9U, AArch64::W9 }, |
| 4824 | { 10U, AArch64::W10 }, |
| 4825 | { 11U, AArch64::W11 }, |
| 4826 | { 12U, AArch64::W12 }, |
| 4827 | { 13U, AArch64::W13 }, |
| 4828 | { 14U, AArch64::W14 }, |
| 4829 | { 15U, AArch64::W15 }, |
| 4830 | { 16U, AArch64::W16 }, |
| 4831 | { 17U, AArch64::W17 }, |
| 4832 | { 18U, AArch64::W18 }, |
| 4833 | { 19U, AArch64::W19 }, |
| 4834 | { 20U, AArch64::W20 }, |
| 4835 | { 21U, AArch64::W21 }, |
| 4836 | { 22U, AArch64::W22 }, |
| 4837 | { 23U, AArch64::W23 }, |
| 4838 | { 24U, AArch64::W24 }, |
| 4839 | { 25U, AArch64::W25 }, |
| 4840 | { 26U, AArch64::W26 }, |
| 4841 | { 27U, AArch64::W27 }, |
| 4842 | { 28U, AArch64::W28 }, |
| 4843 | { 29U, AArch64::W29 }, |
| 4844 | { 30U, AArch64::W30 }, |
| 4845 | { 31U, AArch64::WSP }, |
| 4846 | { 46U, AArch64::VG }, |
| 4847 | { 47U, AArch64::FFR }, |
| 4848 | { 48U, AArch64::P0 }, |
| 4849 | { 49U, AArch64::P1 }, |
| 4850 | { 50U, AArch64::P2 }, |
| 4851 | { 51U, AArch64::P3 }, |
| 4852 | { 52U, AArch64::P4 }, |
| 4853 | { 53U, AArch64::P5 }, |
| 4854 | { 54U, AArch64::P6 }, |
| 4855 | { 55U, AArch64::P7 }, |
| 4856 | { 56U, AArch64::P8 }, |
| 4857 | { 57U, AArch64::P9 }, |
| 4858 | { 58U, AArch64::P10 }, |
| 4859 | { 59U, AArch64::P11 }, |
| 4860 | { 60U, AArch64::P12 }, |
| 4861 | { 61U, AArch64::P13 }, |
| 4862 | { 62U, AArch64::P14 }, |
| 4863 | { 63U, AArch64::P15 }, |
| 4864 | { 64U, AArch64::B0 }, |
| 4865 | { 65U, AArch64::B1 }, |
| 4866 | { 66U, AArch64::B2 }, |
| 4867 | { 67U, AArch64::B3 }, |
| 4868 | { 68U, AArch64::B4 }, |
| 4869 | { 69U, AArch64::B5 }, |
| 4870 | { 70U, AArch64::B6 }, |
| 4871 | { 71U, AArch64::B7 }, |
| 4872 | { 72U, AArch64::B8 }, |
| 4873 | { 73U, AArch64::B9 }, |
| 4874 | { 74U, AArch64::B10 }, |
| 4875 | { 75U, AArch64::B11 }, |
| 4876 | { 76U, AArch64::B12 }, |
| 4877 | { 77U, AArch64::B13 }, |
| 4878 | { 78U, AArch64::B14 }, |
| 4879 | { 79U, AArch64::B15 }, |
| 4880 | { 80U, AArch64::B16 }, |
| 4881 | { 81U, AArch64::B17 }, |
| 4882 | { 82U, AArch64::B18 }, |
| 4883 | { 83U, AArch64::B19 }, |
| 4884 | { 84U, AArch64::B20 }, |
| 4885 | { 85U, AArch64::B21 }, |
| 4886 | { 86U, AArch64::B22 }, |
| 4887 | { 87U, AArch64::B23 }, |
| 4888 | { 88U, AArch64::B24 }, |
| 4889 | { 89U, AArch64::B25 }, |
| 4890 | { 90U, AArch64::B26 }, |
| 4891 | { 91U, AArch64::B27 }, |
| 4892 | { 92U, AArch64::B28 }, |
| 4893 | { 93U, AArch64::B29 }, |
| 4894 | { 94U, AArch64::B30 }, |
| 4895 | { 95U, AArch64::B31 }, |
| 4896 | { 96U, AArch64::Z0 }, |
| 4897 | { 97U, AArch64::Z1 }, |
| 4898 | { 98U, AArch64::Z2 }, |
| 4899 | { 99U, AArch64::Z3 }, |
| 4900 | { 100U, AArch64::Z4 }, |
| 4901 | { 101U, AArch64::Z5 }, |
| 4902 | { 102U, AArch64::Z6 }, |
| 4903 | { 103U, AArch64::Z7 }, |
| 4904 | { 104U, AArch64::Z8 }, |
| 4905 | { 105U, AArch64::Z9 }, |
| 4906 | { 106U, AArch64::Z10 }, |
| 4907 | { 107U, AArch64::Z11 }, |
| 4908 | { 108U, AArch64::Z12 }, |
| 4909 | { 109U, AArch64::Z13 }, |
| 4910 | { 110U, AArch64::Z14 }, |
| 4911 | { 111U, AArch64::Z15 }, |
| 4912 | { 112U, AArch64::Z16 }, |
| 4913 | { 113U, AArch64::Z17 }, |
| 4914 | { 114U, AArch64::Z18 }, |
| 4915 | { 115U, AArch64::Z19 }, |
| 4916 | { 116U, AArch64::Z20 }, |
| 4917 | { 117U, AArch64::Z21 }, |
| 4918 | { 118U, AArch64::Z22 }, |
| 4919 | { 119U, AArch64::Z23 }, |
| 4920 | { 120U, AArch64::Z24 }, |
| 4921 | { 121U, AArch64::Z25 }, |
| 4922 | { 122U, AArch64::Z26 }, |
| 4923 | { 123U, AArch64::Z27 }, |
| 4924 | { 124U, AArch64::Z28 }, |
| 4925 | { 125U, AArch64::Z29 }, |
| 4926 | { 126U, AArch64::Z30 }, |
| 4927 | { 127U, AArch64::Z31 }, |
| 4928 | }; |
| 4929 | extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L); |
| 4930 | |
| 4931 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = { |
| 4932 | { AArch64::FFR, 47U }, |
| 4933 | { AArch64::FP, 29U }, |
| 4934 | { AArch64::LR, 30U }, |
| 4935 | { AArch64::SP, 31U }, |
| 4936 | { AArch64::VG, 46U }, |
| 4937 | { AArch64::WSP, 31U }, |
| 4938 | { AArch64::WZR, 31U }, |
| 4939 | { AArch64::XZR, 31U }, |
| 4940 | { AArch64::B0, 64U }, |
| 4941 | { AArch64::B1, 65U }, |
| 4942 | { AArch64::B2, 66U }, |
| 4943 | { AArch64::B3, 67U }, |
| 4944 | { AArch64::B4, 68U }, |
| 4945 | { AArch64::B5, 69U }, |
| 4946 | { AArch64::B6, 70U }, |
| 4947 | { AArch64::B7, 71U }, |
| 4948 | { AArch64::B8, 72U }, |
| 4949 | { AArch64::B9, 73U }, |
| 4950 | { AArch64::B10, 74U }, |
| 4951 | { AArch64::B11, 75U }, |
| 4952 | { AArch64::B12, 76U }, |
| 4953 | { AArch64::B13, 77U }, |
| 4954 | { AArch64::B14, 78U }, |
| 4955 | { AArch64::B15, 79U }, |
| 4956 | { AArch64::B16, 80U }, |
| 4957 | { AArch64::B17, 81U }, |
| 4958 | { AArch64::B18, 82U }, |
| 4959 | { AArch64::B19, 83U }, |
| 4960 | { AArch64::B20, 84U }, |
| 4961 | { AArch64::B21, 85U }, |
| 4962 | { AArch64::B22, 86U }, |
| 4963 | { AArch64::B23, 87U }, |
| 4964 | { AArch64::B24, 88U }, |
| 4965 | { AArch64::B25, 89U }, |
| 4966 | { AArch64::B26, 90U }, |
| 4967 | { AArch64::B27, 91U }, |
| 4968 | { AArch64::B28, 92U }, |
| 4969 | { AArch64::B29, 93U }, |
| 4970 | { AArch64::B30, 94U }, |
| 4971 | { AArch64::B31, 95U }, |
| 4972 | { AArch64::D0, 64U }, |
| 4973 | { AArch64::D1, 65U }, |
| 4974 | { AArch64::D2, 66U }, |
| 4975 | { AArch64::D3, 67U }, |
| 4976 | { AArch64::D4, 68U }, |
| 4977 | { AArch64::D5, 69U }, |
| 4978 | { AArch64::D6, 70U }, |
| 4979 | { AArch64::D7, 71U }, |
| 4980 | { AArch64::D8, 72U }, |
| 4981 | { AArch64::D9, 73U }, |
| 4982 | { AArch64::D10, 74U }, |
| 4983 | { AArch64::D11, 75U }, |
| 4984 | { AArch64::D12, 76U }, |
| 4985 | { AArch64::D13, 77U }, |
| 4986 | { AArch64::D14, 78U }, |
| 4987 | { AArch64::D15, 79U }, |
| 4988 | { AArch64::D16, 80U }, |
| 4989 | { AArch64::D17, 81U }, |
| 4990 | { AArch64::D18, 82U }, |
| 4991 | { AArch64::D19, 83U }, |
| 4992 | { AArch64::D20, 84U }, |
| 4993 | { AArch64::D21, 85U }, |
| 4994 | { AArch64::D22, 86U }, |
| 4995 | { AArch64::D23, 87U }, |
| 4996 | { AArch64::D24, 88U }, |
| 4997 | { AArch64::D25, 89U }, |
| 4998 | { AArch64::D26, 90U }, |
| 4999 | { AArch64::D27, 91U }, |
| 5000 | { AArch64::D28, 92U }, |
| 5001 | { AArch64::D29, 93U }, |
| 5002 | { AArch64::D30, 94U }, |
| 5003 | { AArch64::D31, 95U }, |
| 5004 | { AArch64::H0, 64U }, |
| 5005 | { AArch64::H1, 65U }, |
| 5006 | { AArch64::H2, 66U }, |
| 5007 | { AArch64::H3, 67U }, |
| 5008 | { AArch64::H4, 68U }, |
| 5009 | { AArch64::H5, 69U }, |
| 5010 | { AArch64::H6, 70U }, |
| 5011 | { AArch64::H7, 71U }, |
| 5012 | { AArch64::H8, 72U }, |
| 5013 | { AArch64::H9, 73U }, |
| 5014 | { AArch64::H10, 74U }, |
| 5015 | { AArch64::H11, 75U }, |
| 5016 | { AArch64::H12, 76U }, |
| 5017 | { AArch64::H13, 77U }, |
| 5018 | { AArch64::H14, 78U }, |
| 5019 | { AArch64::H15, 79U }, |
| 5020 | { AArch64::H16, 80U }, |
| 5021 | { AArch64::H17, 81U }, |
| 5022 | { AArch64::H18, 82U }, |
| 5023 | { AArch64::H19, 83U }, |
| 5024 | { AArch64::H20, 84U }, |
| 5025 | { AArch64::H21, 85U }, |
| 5026 | { AArch64::H22, 86U }, |
| 5027 | { AArch64::H23, 87U }, |
| 5028 | { AArch64::H24, 88U }, |
| 5029 | { AArch64::H25, 89U }, |
| 5030 | { AArch64::H26, 90U }, |
| 5031 | { AArch64::H27, 91U }, |
| 5032 | { AArch64::H28, 92U }, |
| 5033 | { AArch64::H29, 93U }, |
| 5034 | { AArch64::H30, 94U }, |
| 5035 | { AArch64::H31, 95U }, |
| 5036 | { AArch64::P0, 48U }, |
| 5037 | { AArch64::P1, 49U }, |
| 5038 | { AArch64::P2, 50U }, |
| 5039 | { AArch64::P3, 51U }, |
| 5040 | { AArch64::P4, 52U }, |
| 5041 | { AArch64::P5, 53U }, |
| 5042 | { AArch64::P6, 54U }, |
| 5043 | { AArch64::P7, 55U }, |
| 5044 | { AArch64::P8, 56U }, |
| 5045 | { AArch64::P9, 57U }, |
| 5046 | { AArch64::P10, 58U }, |
| 5047 | { AArch64::P11, 59U }, |
| 5048 | { AArch64::P12, 60U }, |
| 5049 | { AArch64::P13, 61U }, |
| 5050 | { AArch64::P14, 62U }, |
| 5051 | { AArch64::P15, 63U }, |
| 5052 | { AArch64::Q0, 64U }, |
| 5053 | { AArch64::Q1, 65U }, |
| 5054 | { AArch64::Q2, 66U }, |
| 5055 | { AArch64::Q3, 67U }, |
| 5056 | { AArch64::Q4, 68U }, |
| 5057 | { AArch64::Q5, 69U }, |
| 5058 | { AArch64::Q6, 70U }, |
| 5059 | { AArch64::Q7, 71U }, |
| 5060 | { AArch64::Q8, 72U }, |
| 5061 | { AArch64::Q9, 73U }, |
| 5062 | { AArch64::Q10, 74U }, |
| 5063 | { AArch64::Q11, 75U }, |
| 5064 | { AArch64::Q12, 76U }, |
| 5065 | { AArch64::Q13, 77U }, |
| 5066 | { AArch64::Q14, 78U }, |
| 5067 | { AArch64::Q15, 79U }, |
| 5068 | { AArch64::Q16, 80U }, |
| 5069 | { AArch64::Q17, 81U }, |
| 5070 | { AArch64::Q18, 82U }, |
| 5071 | { AArch64::Q19, 83U }, |
| 5072 | { AArch64::Q20, 84U }, |
| 5073 | { AArch64::Q21, 85U }, |
| 5074 | { AArch64::Q22, 86U }, |
| 5075 | { AArch64::Q23, 87U }, |
| 5076 | { AArch64::Q24, 88U }, |
| 5077 | { AArch64::Q25, 89U }, |
| 5078 | { AArch64::Q26, 90U }, |
| 5079 | { AArch64::Q27, 91U }, |
| 5080 | { AArch64::Q28, 92U }, |
| 5081 | { AArch64::Q29, 93U }, |
| 5082 | { AArch64::Q30, 94U }, |
| 5083 | { AArch64::Q31, 95U }, |
| 5084 | { AArch64::S0, 64U }, |
| 5085 | { AArch64::S1, 65U }, |
| 5086 | { AArch64::S2, 66U }, |
| 5087 | { AArch64::S3, 67U }, |
| 5088 | { AArch64::S4, 68U }, |
| 5089 | { AArch64::S5, 69U }, |
| 5090 | { AArch64::S6, 70U }, |
| 5091 | { AArch64::S7, 71U }, |
| 5092 | { AArch64::S8, 72U }, |
| 5093 | { AArch64::S9, 73U }, |
| 5094 | { AArch64::S10, 74U }, |
| 5095 | { AArch64::S11, 75U }, |
| 5096 | { AArch64::S12, 76U }, |
| 5097 | { AArch64::S13, 77U }, |
| 5098 | { AArch64::S14, 78U }, |
| 5099 | { AArch64::S15, 79U }, |
| 5100 | { AArch64::S16, 80U }, |
| 5101 | { AArch64::S17, 81U }, |
| 5102 | { AArch64::S18, 82U }, |
| 5103 | { AArch64::S19, 83U }, |
| 5104 | { AArch64::S20, 84U }, |
| 5105 | { AArch64::S21, 85U }, |
| 5106 | { AArch64::S22, 86U }, |
| 5107 | { AArch64::S23, 87U }, |
| 5108 | { AArch64::S24, 88U }, |
| 5109 | { AArch64::S25, 89U }, |
| 5110 | { AArch64::S26, 90U }, |
| 5111 | { AArch64::S27, 91U }, |
| 5112 | { AArch64::S28, 92U }, |
| 5113 | { AArch64::S29, 93U }, |
| 5114 | { AArch64::S30, 94U }, |
| 5115 | { AArch64::S31, 95U }, |
| 5116 | { AArch64::W0, 0U }, |
| 5117 | { AArch64::W1, 1U }, |
| 5118 | { AArch64::W2, 2U }, |
| 5119 | { AArch64::W3, 3U }, |
| 5120 | { AArch64::W4, 4U }, |
| 5121 | { AArch64::W5, 5U }, |
| 5122 | { AArch64::W6, 6U }, |
| 5123 | { AArch64::W7, 7U }, |
| 5124 | { AArch64::W8, 8U }, |
| 5125 | { AArch64::W9, 9U }, |
| 5126 | { AArch64::W10, 10U }, |
| 5127 | { AArch64::W11, 11U }, |
| 5128 | { AArch64::W12, 12U }, |
| 5129 | { AArch64::W13, 13U }, |
| 5130 | { AArch64::W14, 14U }, |
| 5131 | { AArch64::W15, 15U }, |
| 5132 | { AArch64::W16, 16U }, |
| 5133 | { AArch64::W17, 17U }, |
| 5134 | { AArch64::W18, 18U }, |
| 5135 | { AArch64::W19, 19U }, |
| 5136 | { AArch64::W20, 20U }, |
| 5137 | { AArch64::W21, 21U }, |
| 5138 | { AArch64::W22, 22U }, |
| 5139 | { AArch64::W23, 23U }, |
| 5140 | { AArch64::W24, 24U }, |
| 5141 | { AArch64::W25, 25U }, |
| 5142 | { AArch64::W26, 26U }, |
| 5143 | { AArch64::W27, 27U }, |
| 5144 | { AArch64::W28, 28U }, |
| 5145 | { AArch64::W29, 29U }, |
| 5146 | { AArch64::W30, 30U }, |
| 5147 | { AArch64::X0, 0U }, |
| 5148 | { AArch64::X1, 1U }, |
| 5149 | { AArch64::X2, 2U }, |
| 5150 | { AArch64::X3, 3U }, |
| 5151 | { AArch64::X4, 4U }, |
| 5152 | { AArch64::X5, 5U }, |
| 5153 | { AArch64::X6, 6U }, |
| 5154 | { AArch64::X7, 7U }, |
| 5155 | { AArch64::X8, 8U }, |
| 5156 | { AArch64::X9, 9U }, |
| 5157 | { AArch64::X10, 10U }, |
| 5158 | { AArch64::X11, 11U }, |
| 5159 | { AArch64::X12, 12U }, |
| 5160 | { AArch64::X13, 13U }, |
| 5161 | { AArch64::X14, 14U }, |
| 5162 | { AArch64::X15, 15U }, |
| 5163 | { AArch64::X16, 16U }, |
| 5164 | { AArch64::X17, 17U }, |
| 5165 | { AArch64::X18, 18U }, |
| 5166 | { AArch64::X19, 19U }, |
| 5167 | { AArch64::X20, 20U }, |
| 5168 | { AArch64::X21, 21U }, |
| 5169 | { AArch64::X22, 22U }, |
| 5170 | { AArch64::X23, 23U }, |
| 5171 | { AArch64::X24, 24U }, |
| 5172 | { AArch64::X25, 25U }, |
| 5173 | { AArch64::X26, 26U }, |
| 5174 | { AArch64::X27, 27U }, |
| 5175 | { AArch64::X28, 28U }, |
| 5176 | { AArch64::Z0, 96U }, |
| 5177 | { AArch64::Z1, 97U }, |
| 5178 | { AArch64::Z2, 98U }, |
| 5179 | { AArch64::Z3, 99U }, |
| 5180 | { AArch64::Z4, 100U }, |
| 5181 | { AArch64::Z5, 101U }, |
| 5182 | { AArch64::Z6, 102U }, |
| 5183 | { AArch64::Z7, 103U }, |
| 5184 | { AArch64::Z8, 104U }, |
| 5185 | { AArch64::Z9, 105U }, |
| 5186 | { AArch64::Z10, 106U }, |
| 5187 | { AArch64::Z11, 107U }, |
| 5188 | { AArch64::Z12, 108U }, |
| 5189 | { AArch64::Z13, 109U }, |
| 5190 | { AArch64::Z14, 110U }, |
| 5191 | { AArch64::Z15, 111U }, |
| 5192 | { AArch64::Z16, 112U }, |
| 5193 | { AArch64::Z17, 113U }, |
| 5194 | { AArch64::Z18, 114U }, |
| 5195 | { AArch64::Z19, 115U }, |
| 5196 | { AArch64::Z20, 116U }, |
| 5197 | { AArch64::Z21, 117U }, |
| 5198 | { AArch64::Z22, 118U }, |
| 5199 | { AArch64::Z23, 119U }, |
| 5200 | { AArch64::Z24, 120U }, |
| 5201 | { AArch64::Z25, 121U }, |
| 5202 | { AArch64::Z26, 122U }, |
| 5203 | { AArch64::Z27, 123U }, |
| 5204 | { AArch64::Z28, 124U }, |
| 5205 | { AArch64::Z29, 125U }, |
| 5206 | { AArch64::Z30, 126U }, |
| 5207 | { AArch64::Z31, 127U }, |
| 5208 | }; |
| 5209 | extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf); |
| 5210 | |
| 5211 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = { |
| 5212 | { AArch64::FFR, 47U }, |
| 5213 | { AArch64::FP, 29U }, |
| 5214 | { AArch64::LR, 30U }, |
| 5215 | { AArch64::SP, 31U }, |
| 5216 | { AArch64::VG, 46U }, |
| 5217 | { AArch64::WSP, 31U }, |
| 5218 | { AArch64::WZR, 31U }, |
| 5219 | { AArch64::XZR, 31U }, |
| 5220 | { AArch64::B0, 64U }, |
| 5221 | { AArch64::B1, 65U }, |
| 5222 | { AArch64::B2, 66U }, |
| 5223 | { AArch64::B3, 67U }, |
| 5224 | { AArch64::B4, 68U }, |
| 5225 | { AArch64::B5, 69U }, |
| 5226 | { AArch64::B6, 70U }, |
| 5227 | { AArch64::B7, 71U }, |
| 5228 | { AArch64::B8, 72U }, |
| 5229 | { AArch64::B9, 73U }, |
| 5230 | { AArch64::B10, 74U }, |
| 5231 | { AArch64::B11, 75U }, |
| 5232 | { AArch64::B12, 76U }, |
| 5233 | { AArch64::B13, 77U }, |
| 5234 | { AArch64::B14, 78U }, |
| 5235 | { AArch64::B15, 79U }, |
| 5236 | { AArch64::B16, 80U }, |
| 5237 | { AArch64::B17, 81U }, |
| 5238 | { AArch64::B18, 82U }, |
| 5239 | { AArch64::B19, 83U }, |
| 5240 | { AArch64::B20, 84U }, |
| 5241 | { AArch64::B21, 85U }, |
| 5242 | { AArch64::B22, 86U }, |
| 5243 | { AArch64::B23, 87U }, |
| 5244 | { AArch64::B24, 88U }, |
| 5245 | { AArch64::B25, 89U }, |
| 5246 | { AArch64::B26, 90U }, |
| 5247 | { AArch64::B27, 91U }, |
| 5248 | { AArch64::B28, 92U }, |
| 5249 | { AArch64::B29, 93U }, |
| 5250 | { AArch64::B30, 94U }, |
| 5251 | { AArch64::B31, 95U }, |
| 5252 | { AArch64::D0, 64U }, |
| 5253 | { AArch64::D1, 65U }, |
| 5254 | { AArch64::D2, 66U }, |
| 5255 | { AArch64::D3, 67U }, |
| 5256 | { AArch64::D4, 68U }, |
| 5257 | { AArch64::D5, 69U }, |
| 5258 | { AArch64::D6, 70U }, |
| 5259 | { AArch64::D7, 71U }, |
| 5260 | { AArch64::D8, 72U }, |
| 5261 | { AArch64::D9, 73U }, |
| 5262 | { AArch64::D10, 74U }, |
| 5263 | { AArch64::D11, 75U }, |
| 5264 | { AArch64::D12, 76U }, |
| 5265 | { AArch64::D13, 77U }, |
| 5266 | { AArch64::D14, 78U }, |
| 5267 | { AArch64::D15, 79U }, |
| 5268 | { AArch64::D16, 80U }, |
| 5269 | { AArch64::D17, 81U }, |
| 5270 | { AArch64::D18, 82U }, |
| 5271 | { AArch64::D19, 83U }, |
| 5272 | { AArch64::D20, 84U }, |
| 5273 | { AArch64::D21, 85U }, |
| 5274 | { AArch64::D22, 86U }, |
| 5275 | { AArch64::D23, 87U }, |
| 5276 | { AArch64::D24, 88U }, |
| 5277 | { AArch64::D25, 89U }, |
| 5278 | { AArch64::D26, 90U }, |
| 5279 | { AArch64::D27, 91U }, |
| 5280 | { AArch64::D28, 92U }, |
| 5281 | { AArch64::D29, 93U }, |
| 5282 | { AArch64::D30, 94U }, |
| 5283 | { AArch64::D31, 95U }, |
| 5284 | { AArch64::H0, 64U }, |
| 5285 | { AArch64::H1, 65U }, |
| 5286 | { AArch64::H2, 66U }, |
| 5287 | { AArch64::H3, 67U }, |
| 5288 | { AArch64::H4, 68U }, |
| 5289 | { AArch64::H5, 69U }, |
| 5290 | { AArch64::H6, 70U }, |
| 5291 | { AArch64::H7, 71U }, |
| 5292 | { AArch64::H8, 72U }, |
| 5293 | { AArch64::H9, 73U }, |
| 5294 | { AArch64::H10, 74U }, |
| 5295 | { AArch64::H11, 75U }, |
| 5296 | { AArch64::H12, 76U }, |
| 5297 | { AArch64::H13, 77U }, |
| 5298 | { AArch64::H14, 78U }, |
| 5299 | { AArch64::H15, 79U }, |
| 5300 | { AArch64::H16, 80U }, |
| 5301 | { AArch64::H17, 81U }, |
| 5302 | { AArch64::H18, 82U }, |
| 5303 | { AArch64::H19, 83U }, |
| 5304 | { AArch64::H20, 84U }, |
| 5305 | { AArch64::H21, 85U }, |
| 5306 | { AArch64::H22, 86U }, |
| 5307 | { AArch64::H23, 87U }, |
| 5308 | { AArch64::H24, 88U }, |
| 5309 | { AArch64::H25, 89U }, |
| 5310 | { AArch64::H26, 90U }, |
| 5311 | { AArch64::H27, 91U }, |
| 5312 | { AArch64::H28, 92U }, |
| 5313 | { AArch64::H29, 93U }, |
| 5314 | { AArch64::H30, 94U }, |
| 5315 | { AArch64::H31, 95U }, |
| 5316 | { AArch64::P0, 48U }, |
| 5317 | { AArch64::P1, 49U }, |
| 5318 | { AArch64::P2, 50U }, |
| 5319 | { AArch64::P3, 51U }, |
| 5320 | { AArch64::P4, 52U }, |
| 5321 | { AArch64::P5, 53U }, |
| 5322 | { AArch64::P6, 54U }, |
| 5323 | { AArch64::P7, 55U }, |
| 5324 | { AArch64::P8, 56U }, |
| 5325 | { AArch64::P9, 57U }, |
| 5326 | { AArch64::P10, 58U }, |
| 5327 | { AArch64::P11, 59U }, |
| 5328 | { AArch64::P12, 60U }, |
| 5329 | { AArch64::P13, 61U }, |
| 5330 | { AArch64::P14, 62U }, |
| 5331 | { AArch64::P15, 63U }, |
| 5332 | { AArch64::Q0, 64U }, |
| 5333 | { AArch64::Q1, 65U }, |
| 5334 | { AArch64::Q2, 66U }, |
| 5335 | { AArch64::Q3, 67U }, |
| 5336 | { AArch64::Q4, 68U }, |
| 5337 | { AArch64::Q5, 69U }, |
| 5338 | { AArch64::Q6, 70U }, |
| 5339 | { AArch64::Q7, 71U }, |
| 5340 | { AArch64::Q8, 72U }, |
| 5341 | { AArch64::Q9, 73U }, |
| 5342 | { AArch64::Q10, 74U }, |
| 5343 | { AArch64::Q11, 75U }, |
| 5344 | { AArch64::Q12, 76U }, |
| 5345 | { AArch64::Q13, 77U }, |
| 5346 | { AArch64::Q14, 78U }, |
| 5347 | { AArch64::Q15, 79U }, |
| 5348 | { AArch64::Q16, 80U }, |
| 5349 | { AArch64::Q17, 81U }, |
| 5350 | { AArch64::Q18, 82U }, |
| 5351 | { AArch64::Q19, 83U }, |
| 5352 | { AArch64::Q20, 84U }, |
| 5353 | { AArch64::Q21, 85U }, |
| 5354 | { AArch64::Q22, 86U }, |
| 5355 | { AArch64::Q23, 87U }, |
| 5356 | { AArch64::Q24, 88U }, |
| 5357 | { AArch64::Q25, 89U }, |
| 5358 | { AArch64::Q26, 90U }, |
| 5359 | { AArch64::Q27, 91U }, |
| 5360 | { AArch64::Q28, 92U }, |
| 5361 | { AArch64::Q29, 93U }, |
| 5362 | { AArch64::Q30, 94U }, |
| 5363 | { AArch64::Q31, 95U }, |
| 5364 | { AArch64::S0, 64U }, |
| 5365 | { AArch64::S1, 65U }, |
| 5366 | { AArch64::S2, 66U }, |
| 5367 | { AArch64::S3, 67U }, |
| 5368 | { AArch64::S4, 68U }, |
| 5369 | { AArch64::S5, 69U }, |
| 5370 | { AArch64::S6, 70U }, |
| 5371 | { AArch64::S7, 71U }, |
| 5372 | { AArch64::S8, 72U }, |
| 5373 | { AArch64::S9, 73U }, |
| 5374 | { AArch64::S10, 74U }, |
| 5375 | { AArch64::S11, 75U }, |
| 5376 | { AArch64::S12, 76U }, |
| 5377 | { AArch64::S13, 77U }, |
| 5378 | { AArch64::S14, 78U }, |
| 5379 | { AArch64::S15, 79U }, |
| 5380 | { AArch64::S16, 80U }, |
| 5381 | { AArch64::S17, 81U }, |
| 5382 | { AArch64::S18, 82U }, |
| 5383 | { AArch64::S19, 83U }, |
| 5384 | { AArch64::S20, 84U }, |
| 5385 | { AArch64::S21, 85U }, |
| 5386 | { AArch64::S22, 86U }, |
| 5387 | { AArch64::S23, 87U }, |
| 5388 | { AArch64::S24, 88U }, |
| 5389 | { AArch64::S25, 89U }, |
| 5390 | { AArch64::S26, 90U }, |
| 5391 | { AArch64::S27, 91U }, |
| 5392 | { AArch64::S28, 92U }, |
| 5393 | { AArch64::S29, 93U }, |
| 5394 | { AArch64::S30, 94U }, |
| 5395 | { AArch64::S31, 95U }, |
| 5396 | { AArch64::W0, 0U }, |
| 5397 | { AArch64::W1, 1U }, |
| 5398 | { AArch64::W2, 2U }, |
| 5399 | { AArch64::W3, 3U }, |
| 5400 | { AArch64::W4, 4U }, |
| 5401 | { AArch64::W5, 5U }, |
| 5402 | { AArch64::W6, 6U }, |
| 5403 | { AArch64::W7, 7U }, |
| 5404 | { AArch64::W8, 8U }, |
| 5405 | { AArch64::W9, 9U }, |
| 5406 | { AArch64::W10, 10U }, |
| 5407 | { AArch64::W11, 11U }, |
| 5408 | { AArch64::W12, 12U }, |
| 5409 | { AArch64::W13, 13U }, |
| 5410 | { AArch64::W14, 14U }, |
| 5411 | { AArch64::W15, 15U }, |
| 5412 | { AArch64::W16, 16U }, |
| 5413 | { AArch64::W17, 17U }, |
| 5414 | { AArch64::W18, 18U }, |
| 5415 | { AArch64::W19, 19U }, |
| 5416 | { AArch64::W20, 20U }, |
| 5417 | { AArch64::W21, 21U }, |
| 5418 | { AArch64::W22, 22U }, |
| 5419 | { AArch64::W23, 23U }, |
| 5420 | { AArch64::W24, 24U }, |
| 5421 | { AArch64::W25, 25U }, |
| 5422 | { AArch64::W26, 26U }, |
| 5423 | { AArch64::W27, 27U }, |
| 5424 | { AArch64::W28, 28U }, |
| 5425 | { AArch64::W29, 29U }, |
| 5426 | { AArch64::W30, 30U }, |
| 5427 | { AArch64::X0, 0U }, |
| 5428 | { AArch64::X1, 1U }, |
| 5429 | { AArch64::X2, 2U }, |
| 5430 | { AArch64::X3, 3U }, |
| 5431 | { AArch64::X4, 4U }, |
| 5432 | { AArch64::X5, 5U }, |
| 5433 | { AArch64::X6, 6U }, |
| 5434 | { AArch64::X7, 7U }, |
| 5435 | { AArch64::X8, 8U }, |
| 5436 | { AArch64::X9, 9U }, |
| 5437 | { AArch64::X10, 10U }, |
| 5438 | { AArch64::X11, 11U }, |
| 5439 | { AArch64::X12, 12U }, |
| 5440 | { AArch64::X13, 13U }, |
| 5441 | { AArch64::X14, 14U }, |
| 5442 | { AArch64::X15, 15U }, |
| 5443 | { AArch64::X16, 16U }, |
| 5444 | { AArch64::X17, 17U }, |
| 5445 | { AArch64::X18, 18U }, |
| 5446 | { AArch64::X19, 19U }, |
| 5447 | { AArch64::X20, 20U }, |
| 5448 | { AArch64::X21, 21U }, |
| 5449 | { AArch64::X22, 22U }, |
| 5450 | { AArch64::X23, 23U }, |
| 5451 | { AArch64::X24, 24U }, |
| 5452 | { AArch64::X25, 25U }, |
| 5453 | { AArch64::X26, 26U }, |
| 5454 | { AArch64::X27, 27U }, |
| 5455 | { AArch64::X28, 28U }, |
| 5456 | { AArch64::Z0, 96U }, |
| 5457 | { AArch64::Z1, 97U }, |
| 5458 | { AArch64::Z2, 98U }, |
| 5459 | { AArch64::Z3, 99U }, |
| 5460 | { AArch64::Z4, 100U }, |
| 5461 | { AArch64::Z5, 101U }, |
| 5462 | { AArch64::Z6, 102U }, |
| 5463 | { AArch64::Z7, 103U }, |
| 5464 | { AArch64::Z8, 104U }, |
| 5465 | { AArch64::Z9, 105U }, |
| 5466 | { AArch64::Z10, 106U }, |
| 5467 | { AArch64::Z11, 107U }, |
| 5468 | { AArch64::Z12, 108U }, |
| 5469 | { AArch64::Z13, 109U }, |
| 5470 | { AArch64::Z14, 110U }, |
| 5471 | { AArch64::Z15, 111U }, |
| 5472 | { AArch64::Z16, 112U }, |
| 5473 | { AArch64::Z17, 113U }, |
| 5474 | { AArch64::Z18, 114U }, |
| 5475 | { AArch64::Z19, 115U }, |
| 5476 | { AArch64::Z20, 116U }, |
| 5477 | { AArch64::Z21, 117U }, |
| 5478 | { AArch64::Z22, 118U }, |
| 5479 | { AArch64::Z23, 119U }, |
| 5480 | { AArch64::Z24, 120U }, |
| 5481 | { AArch64::Z25, 121U }, |
| 5482 | { AArch64::Z26, 122U }, |
| 5483 | { AArch64::Z27, 123U }, |
| 5484 | { AArch64::Z28, 124U }, |
| 5485 | { AArch64::Z29, 125U }, |
| 5486 | { AArch64::Z30, 126U }, |
| 5487 | { AArch64::Z31, 127U }, |
| 5488 | }; |
| 5489 | extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf); |
| 5490 | |
| 5491 | extern const uint16_t AArch64RegEncodingTable[] = { |
| 5492 | 0, |
| 5493 | 0, |
| 5494 | 29, |
| 5495 | 30, |
| 5496 | 0, |
| 5497 | 31, |
| 5498 | 0, |
| 5499 | 31, |
| 5500 | 31, |
| 5501 | 31, |
| 5502 | 0, |
| 5503 | 1, |
| 5504 | 2, |
| 5505 | 3, |
| 5506 | 4, |
| 5507 | 5, |
| 5508 | 6, |
| 5509 | 7, |
| 5510 | 8, |
| 5511 | 9, |
| 5512 | 10, |
| 5513 | 11, |
| 5514 | 12, |
| 5515 | 13, |
| 5516 | 14, |
| 5517 | 15, |
| 5518 | 16, |
| 5519 | 17, |
| 5520 | 18, |
| 5521 | 19, |
| 5522 | 20, |
| 5523 | 21, |
| 5524 | 22, |
| 5525 | 23, |
| 5526 | 24, |
| 5527 | 25, |
| 5528 | 26, |
| 5529 | 27, |
| 5530 | 28, |
| 5531 | 29, |
| 5532 | 30, |
| 5533 | 31, |
| 5534 | 0, |
| 5535 | 1, |
| 5536 | 2, |
| 5537 | 3, |
| 5538 | 4, |
| 5539 | 5, |
| 5540 | 6, |
| 5541 | 7, |
| 5542 | 8, |
| 5543 | 9, |
| 5544 | 10, |
| 5545 | 11, |
| 5546 | 12, |
| 5547 | 13, |
| 5548 | 14, |
| 5549 | 15, |
| 5550 | 16, |
| 5551 | 17, |
| 5552 | 18, |
| 5553 | 19, |
| 5554 | 20, |
| 5555 | 21, |
| 5556 | 22, |
| 5557 | 23, |
| 5558 | 24, |
| 5559 | 25, |
| 5560 | 26, |
| 5561 | 27, |
| 5562 | 28, |
| 5563 | 29, |
| 5564 | 30, |
| 5565 | 31, |
| 5566 | 0, |
| 5567 | 1, |
| 5568 | 2, |
| 5569 | 3, |
| 5570 | 4, |
| 5571 | 5, |
| 5572 | 6, |
| 5573 | 7, |
| 5574 | 8, |
| 5575 | 9, |
| 5576 | 10, |
| 5577 | 11, |
| 5578 | 12, |
| 5579 | 13, |
| 5580 | 14, |
| 5581 | 15, |
| 5582 | 16, |
| 5583 | 17, |
| 5584 | 18, |
| 5585 | 19, |
| 5586 | 20, |
| 5587 | 21, |
| 5588 | 22, |
| 5589 | 23, |
| 5590 | 24, |
| 5591 | 25, |
| 5592 | 26, |
| 5593 | 27, |
| 5594 | 28, |
| 5595 | 29, |
| 5596 | 30, |
| 5597 | 31, |
| 5598 | 0, |
| 5599 | 1, |
| 5600 | 2, |
| 5601 | 3, |
| 5602 | 4, |
| 5603 | 5, |
| 5604 | 6, |
| 5605 | 7, |
| 5606 | 8, |
| 5607 | 9, |
| 5608 | 10, |
| 5609 | 11, |
| 5610 | 12, |
| 5611 | 13, |
| 5612 | 14, |
| 5613 | 15, |
| 5614 | 0, |
| 5615 | 1, |
| 5616 | 2, |
| 5617 | 3, |
| 5618 | 4, |
| 5619 | 5, |
| 5620 | 6, |
| 5621 | 7, |
| 5622 | 8, |
| 5623 | 9, |
| 5624 | 10, |
| 5625 | 11, |
| 5626 | 12, |
| 5627 | 13, |
| 5628 | 14, |
| 5629 | 15, |
| 5630 | 16, |
| 5631 | 17, |
| 5632 | 18, |
| 5633 | 19, |
| 5634 | 20, |
| 5635 | 21, |
| 5636 | 22, |
| 5637 | 23, |
| 5638 | 24, |
| 5639 | 25, |
| 5640 | 26, |
| 5641 | 27, |
| 5642 | 28, |
| 5643 | 29, |
| 5644 | 30, |
| 5645 | 31, |
| 5646 | 0, |
| 5647 | 1, |
| 5648 | 2, |
| 5649 | 3, |
| 5650 | 4, |
| 5651 | 5, |
| 5652 | 6, |
| 5653 | 7, |
| 5654 | 8, |
| 5655 | 9, |
| 5656 | 10, |
| 5657 | 11, |
| 5658 | 12, |
| 5659 | 13, |
| 5660 | 14, |
| 5661 | 15, |
| 5662 | 16, |
| 5663 | 17, |
| 5664 | 18, |
| 5665 | 19, |
| 5666 | 20, |
| 5667 | 21, |
| 5668 | 22, |
| 5669 | 23, |
| 5670 | 24, |
| 5671 | 25, |
| 5672 | 26, |
| 5673 | 27, |
| 5674 | 28, |
| 5675 | 29, |
| 5676 | 30, |
| 5677 | 31, |
| 5678 | 0, |
| 5679 | 1, |
| 5680 | 2, |
| 5681 | 3, |
| 5682 | 4, |
| 5683 | 5, |
| 5684 | 6, |
| 5685 | 7, |
| 5686 | 8, |
| 5687 | 9, |
| 5688 | 10, |
| 5689 | 11, |
| 5690 | 12, |
| 5691 | 13, |
| 5692 | 14, |
| 5693 | 15, |
| 5694 | 16, |
| 5695 | 17, |
| 5696 | 18, |
| 5697 | 19, |
| 5698 | 20, |
| 5699 | 21, |
| 5700 | 22, |
| 5701 | 23, |
| 5702 | 24, |
| 5703 | 25, |
| 5704 | 26, |
| 5705 | 27, |
| 5706 | 28, |
| 5707 | 29, |
| 5708 | 30, |
| 5709 | 0, |
| 5710 | 1, |
| 5711 | 2, |
| 5712 | 3, |
| 5713 | 4, |
| 5714 | 5, |
| 5715 | 6, |
| 5716 | 7, |
| 5717 | 8, |
| 5718 | 9, |
| 5719 | 10, |
| 5720 | 11, |
| 5721 | 12, |
| 5722 | 13, |
| 5723 | 14, |
| 5724 | 15, |
| 5725 | 16, |
| 5726 | 17, |
| 5727 | 18, |
| 5728 | 19, |
| 5729 | 20, |
| 5730 | 21, |
| 5731 | 22, |
| 5732 | 23, |
| 5733 | 24, |
| 5734 | 25, |
| 5735 | 26, |
| 5736 | 27, |
| 5737 | 28, |
| 5738 | 0, |
| 5739 | 1, |
| 5740 | 2, |
| 5741 | 3, |
| 5742 | 4, |
| 5743 | 5, |
| 5744 | 6, |
| 5745 | 7, |
| 5746 | 8, |
| 5747 | 9, |
| 5748 | 10, |
| 5749 | 11, |
| 5750 | 12, |
| 5751 | 13, |
| 5752 | 14, |
| 5753 | 15, |
| 5754 | 16, |
| 5755 | 17, |
| 5756 | 18, |
| 5757 | 19, |
| 5758 | 20, |
| 5759 | 21, |
| 5760 | 22, |
| 5761 | 23, |
| 5762 | 24, |
| 5763 | 25, |
| 5764 | 26, |
| 5765 | 27, |
| 5766 | 28, |
| 5767 | 29, |
| 5768 | 30, |
| 5769 | 31, |
| 5770 | 0, |
| 5771 | 1, |
| 5772 | 2, |
| 5773 | 3, |
| 5774 | 4, |
| 5775 | 5, |
| 5776 | 6, |
| 5777 | 7, |
| 5778 | 8, |
| 5779 | 9, |
| 5780 | 10, |
| 5781 | 11, |
| 5782 | 12, |
| 5783 | 13, |
| 5784 | 14, |
| 5785 | 15, |
| 5786 | 16, |
| 5787 | 17, |
| 5788 | 18, |
| 5789 | 19, |
| 5790 | 20, |
| 5791 | 21, |
| 5792 | 22, |
| 5793 | 23, |
| 5794 | 24, |
| 5795 | 25, |
| 5796 | 26, |
| 5797 | 27, |
| 5798 | 28, |
| 5799 | 29, |
| 5800 | 30, |
| 5801 | 31, |
| 5802 | 0, |
| 5803 | 1, |
| 5804 | 2, |
| 5805 | 3, |
| 5806 | 4, |
| 5807 | 5, |
| 5808 | 6, |
| 5809 | 7, |
| 5810 | 8, |
| 5811 | 9, |
| 5812 | 10, |
| 5813 | 11, |
| 5814 | 12, |
| 5815 | 13, |
| 5816 | 14, |
| 5817 | 15, |
| 5818 | 16, |
| 5819 | 17, |
| 5820 | 18, |
| 5821 | 19, |
| 5822 | 20, |
| 5823 | 21, |
| 5824 | 22, |
| 5825 | 23, |
| 5826 | 24, |
| 5827 | 25, |
| 5828 | 26, |
| 5829 | 27, |
| 5830 | 28, |
| 5831 | 29, |
| 5832 | 30, |
| 5833 | 31, |
| 5834 | 0, |
| 5835 | 1, |
| 5836 | 2, |
| 5837 | 3, |
| 5838 | 4, |
| 5839 | 5, |
| 5840 | 6, |
| 5841 | 7, |
| 5842 | 8, |
| 5843 | 9, |
| 5844 | 10, |
| 5845 | 11, |
| 5846 | 12, |
| 5847 | 13, |
| 5848 | 14, |
| 5849 | 15, |
| 5850 | 16, |
| 5851 | 17, |
| 5852 | 18, |
| 5853 | 19, |
| 5854 | 20, |
| 5855 | 21, |
| 5856 | 22, |
| 5857 | 23, |
| 5858 | 24, |
| 5859 | 25, |
| 5860 | 26, |
| 5861 | 27, |
| 5862 | 28, |
| 5863 | 29, |
| 5864 | 30, |
| 5865 | 31, |
| 5866 | 0, |
| 5867 | 1, |
| 5868 | 2, |
| 5869 | 3, |
| 5870 | 4, |
| 5871 | 5, |
| 5872 | 6, |
| 5873 | 7, |
| 5874 | 8, |
| 5875 | 9, |
| 5876 | 10, |
| 5877 | 11, |
| 5878 | 12, |
| 5879 | 13, |
| 5880 | 14, |
| 5881 | 15, |
| 5882 | 16, |
| 5883 | 17, |
| 5884 | 18, |
| 5885 | 19, |
| 5886 | 20, |
| 5887 | 21, |
| 5888 | 22, |
| 5889 | 23, |
| 5890 | 24, |
| 5891 | 25, |
| 5892 | 26, |
| 5893 | 27, |
| 5894 | 28, |
| 5895 | 29, |
| 5896 | 30, |
| 5897 | 31, |
| 5898 | 0, |
| 5899 | 1, |
| 5900 | 2, |
| 5901 | 3, |
| 5902 | 4, |
| 5903 | 5, |
| 5904 | 6, |
| 5905 | 7, |
| 5906 | 8, |
| 5907 | 9, |
| 5908 | 10, |
| 5909 | 11, |
| 5910 | 12, |
| 5911 | 13, |
| 5912 | 14, |
| 5913 | 15, |
| 5914 | 16, |
| 5915 | 17, |
| 5916 | 18, |
| 5917 | 19, |
| 5918 | 20, |
| 5919 | 21, |
| 5920 | 22, |
| 5921 | 23, |
| 5922 | 24, |
| 5923 | 25, |
| 5924 | 26, |
| 5925 | 27, |
| 5926 | 28, |
| 5927 | 29, |
| 5928 | 30, |
| 5929 | 31, |
| 5930 | 0, |
| 5931 | 1, |
| 5932 | 2, |
| 5933 | 3, |
| 5934 | 4, |
| 5935 | 5, |
| 5936 | 6, |
| 5937 | 7, |
| 5938 | 8, |
| 5939 | 9, |
| 5940 | 10, |
| 5941 | 11, |
| 5942 | 12, |
| 5943 | 13, |
| 5944 | 14, |
| 5945 | 15, |
| 5946 | 16, |
| 5947 | 17, |
| 5948 | 18, |
| 5949 | 19, |
| 5950 | 20, |
| 5951 | 21, |
| 5952 | 22, |
| 5953 | 23, |
| 5954 | 24, |
| 5955 | 25, |
| 5956 | 26, |
| 5957 | 27, |
| 5958 | 28, |
| 5959 | 29, |
| 5960 | 30, |
| 5961 | 31, |
| 5962 | 0, |
| 5963 | 1, |
| 5964 | 2, |
| 5965 | 3, |
| 5966 | 4, |
| 5967 | 5, |
| 5968 | 6, |
| 5969 | 7, |
| 5970 | 8, |
| 5971 | 9, |
| 5972 | 10, |
| 5973 | 11, |
| 5974 | 12, |
| 5975 | 13, |
| 5976 | 14, |
| 5977 | 15, |
| 5978 | 16, |
| 5979 | 17, |
| 5980 | 18, |
| 5981 | 19, |
| 5982 | 20, |
| 5983 | 21, |
| 5984 | 22, |
| 5985 | 23, |
| 5986 | 24, |
| 5987 | 25, |
| 5988 | 26, |
| 5989 | 27, |
| 5990 | 28, |
| 5991 | 29, |
| 5992 | 30, |
| 5993 | 31, |
| 5994 | 22, |
| 5995 | 0, |
| 5996 | 2, |
| 5997 | 4, |
| 5998 | 6, |
| 5999 | 8, |
| 6000 | 10, |
| 6001 | 12, |
| 6002 | 14, |
| 6003 | 16, |
| 6004 | 18, |
| 6005 | 20, |
| 6006 | 30, |
| 6007 | 0, |
| 6008 | 2, |
| 6009 | 4, |
| 6010 | 6, |
| 6011 | 8, |
| 6012 | 10, |
| 6013 | 12, |
| 6014 | 14, |
| 6015 | 16, |
| 6016 | 18, |
| 6017 | 20, |
| 6018 | 22, |
| 6019 | 24, |
| 6020 | 26, |
| 6021 | 28, |
| 6022 | 30, |
| 6023 | 28, |
| 6024 | 0, |
| 6025 | 2, |
| 6026 | 4, |
| 6027 | 6, |
| 6028 | 8, |
| 6029 | 10, |
| 6030 | 12, |
| 6031 | 14, |
| 6032 | 16, |
| 6033 | 18, |
| 6034 | 20, |
| 6035 | 22, |
| 6036 | 24, |
| 6037 | 26, |
| 6038 | 0, |
| 6039 | 1, |
| 6040 | 2, |
| 6041 | 3, |
| 6042 | 4, |
| 6043 | 5, |
| 6044 | 6, |
| 6045 | 7, |
| 6046 | 8, |
| 6047 | 9, |
| 6048 | 10, |
| 6049 | 11, |
| 6050 | 12, |
| 6051 | 13, |
| 6052 | 14, |
| 6053 | 15, |
| 6054 | 16, |
| 6055 | 17, |
| 6056 | 18, |
| 6057 | 19, |
| 6058 | 20, |
| 6059 | 21, |
| 6060 | 22, |
| 6061 | 23, |
| 6062 | 24, |
| 6063 | 25, |
| 6064 | 26, |
| 6065 | 27, |
| 6066 | 28, |
| 6067 | 29, |
| 6068 | 30, |
| 6069 | 31, |
| 6070 | 0, |
| 6071 | 1, |
| 6072 | 2, |
| 6073 | 3, |
| 6074 | 4, |
| 6075 | 5, |
| 6076 | 6, |
| 6077 | 7, |
| 6078 | 8, |
| 6079 | 9, |
| 6080 | 10, |
| 6081 | 11, |
| 6082 | 12, |
| 6083 | 13, |
| 6084 | 14, |
| 6085 | 15, |
| 6086 | 16, |
| 6087 | 17, |
| 6088 | 18, |
| 6089 | 19, |
| 6090 | 20, |
| 6091 | 21, |
| 6092 | 22, |
| 6093 | 23, |
| 6094 | 24, |
| 6095 | 25, |
| 6096 | 26, |
| 6097 | 27, |
| 6098 | 28, |
| 6099 | 29, |
| 6100 | 30, |
| 6101 | 31, |
| 6102 | 0, |
| 6103 | 1, |
| 6104 | 2, |
| 6105 | 3, |
| 6106 | 4, |
| 6107 | 5, |
| 6108 | 6, |
| 6109 | 7, |
| 6110 | 8, |
| 6111 | 9, |
| 6112 | 10, |
| 6113 | 11, |
| 6114 | 12, |
| 6115 | 13, |
| 6116 | 14, |
| 6117 | 15, |
| 6118 | 16, |
| 6119 | 17, |
| 6120 | 18, |
| 6121 | 19, |
| 6122 | 20, |
| 6123 | 21, |
| 6124 | 22, |
| 6125 | 23, |
| 6126 | 24, |
| 6127 | 25, |
| 6128 | 26, |
| 6129 | 27, |
| 6130 | 28, |
| 6131 | 29, |
| 6132 | 30, |
| 6133 | 31, |
| 6134 | }; |
| 6135 | static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| 6136 | RI->InitMCRegisterInfo(AArch64RegDesc, 642, RA, PC, AArch64MCRegisterClasses, 186, AArch64RegUnitRoots, 116, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 123, |
| 6137 | AArch64SubRegIdxRanges, AArch64RegEncodingTable); |
| 6138 | |
| 6139 | switch (DwarfFlavour) { |
| 6140 | default: |
| 6141 | llvm_unreachable("Unknown DWARF flavour" ); |
| 6142 | case 0: |
| 6143 | RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false); |
| 6144 | break; |
| 6145 | } |
| 6146 | switch (EHFlavour) { |
| 6147 | default: |
| 6148 | llvm_unreachable("Unknown DWARF flavour" ); |
| 6149 | case 0: |
| 6150 | RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true); |
| 6151 | break; |
| 6152 | } |
| 6153 | switch (DwarfFlavour) { |
| 6154 | default: |
| 6155 | llvm_unreachable("Unknown DWARF flavour" ); |
| 6156 | case 0: |
| 6157 | RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false); |
| 6158 | break; |
| 6159 | } |
| 6160 | switch (EHFlavour) { |
| 6161 | default: |
| 6162 | llvm_unreachable("Unknown DWARF flavour" ); |
| 6163 | case 0: |
| 6164 | RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true); |
| 6165 | break; |
| 6166 | } |
| 6167 | } |
| 6168 | |
| 6169 | } // end namespace llvm |
| 6170 | |
| 6171 | #endif // GET_REGINFO_MC_DESC |
| 6172 | |
| 6173 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 6174 | |* *| |
| 6175 | |* Register Information Header Fragment *| |
| 6176 | |* *| |
| 6177 | |* Automatically generated file, do not edit! *| |
| 6178 | |* *| |
| 6179 | \*===----------------------------------------------------------------------===*/ |
| 6180 | |
| 6181 | |
| 6182 | #ifdef GET_REGINFO_HEADER |
| 6183 | #undef GET_REGINFO_HEADER |
| 6184 | |
| 6185 | #include "llvm/CodeGen/TargetRegisterInfo.h" |
| 6186 | |
| 6187 | namespace llvm { |
| 6188 | |
| 6189 | class AArch64FrameLowering; |
| 6190 | |
| 6191 | struct AArch64GenRegisterInfo : public TargetRegisterInfo { |
| 6192 | explicit AArch64GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
| 6193 | unsigned PC = 0, unsigned HwMode = 0); |
| 6194 | unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
| 6195 | LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| 6196 | LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| 6197 | const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override; |
| 6198 | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
| 6199 | unsigned getRegUnitWeight(unsigned RegUnit) const override; |
| 6200 | unsigned getNumRegPressureSets() const override; |
| 6201 | const char *getRegPressureSetName(unsigned Idx) const override; |
| 6202 | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
| 6203 | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
| 6204 | const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
| 6205 | ArrayRef<const char *> getRegMaskNames() const override; |
| 6206 | ArrayRef<const uint32_t *> getRegMasks() const override; |
| 6207 | /// Devirtualized TargetFrameLowering. |
| 6208 | static const AArch64FrameLowering *getFrameLowering( |
| 6209 | const MachineFunction &MF); |
| 6210 | }; |
| 6211 | |
| 6212 | namespace AArch64 { // Register classes |
| 6213 | extern const TargetRegisterClass FPR8RegClass; |
| 6214 | extern const TargetRegisterClass FPR16RegClass; |
| 6215 | extern const TargetRegisterClass FPR16_loRegClass; |
| 6216 | extern const TargetRegisterClass PPRRegClass; |
| 6217 | extern const TargetRegisterClass PPR_3bRegClass; |
| 6218 | extern const TargetRegisterClass GPR32allRegClass; |
| 6219 | extern const TargetRegisterClass FPR32RegClass; |
| 6220 | extern const TargetRegisterClass GPR32RegClass; |
| 6221 | extern const TargetRegisterClass GPR32spRegClass; |
| 6222 | extern const TargetRegisterClass GPR32commonRegClass; |
| 6223 | extern const TargetRegisterClass FPR32_with_hsub_in_FPR16_loRegClass; |
| 6224 | extern const TargetRegisterClass GPR32argRegClass; |
| 6225 | extern const TargetRegisterClass CCRRegClass; |
| 6226 | extern const TargetRegisterClass GPR32sponlyRegClass; |
| 6227 | extern const TargetRegisterClass WSeqPairsClassRegClass; |
| 6228 | extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass; |
| 6229 | extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass; |
| 6230 | extern const TargetRegisterClass GPR64allRegClass; |
| 6231 | extern const TargetRegisterClass FPR64RegClass; |
| 6232 | extern const TargetRegisterClass GPR64RegClass; |
| 6233 | extern const TargetRegisterClass GPR64spRegClass; |
| 6234 | extern const TargetRegisterClass GPR64commonRegClass; |
| 6235 | extern const TargetRegisterClass GPR64noipRegClass; |
| 6236 | extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass; |
| 6237 | extern const TargetRegisterClass tcGPR64RegClass; |
| 6238 | extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass; |
| 6239 | extern const TargetRegisterClass FPR64_loRegClass; |
| 6240 | extern const TargetRegisterClass GPR64x8ClassRegClass; |
| 6241 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass; |
| 6242 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass; |
| 6243 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6244 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6245 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass; |
| 6246 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6247 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6248 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass; |
| 6249 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6250 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6251 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6252 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass; |
| 6253 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass; |
| 6254 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6255 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6256 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass; |
| 6257 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6258 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6259 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6260 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6261 | extern const TargetRegisterClass GPR64argRegClass; |
| 6262 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass; |
| 6263 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6264 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6265 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass; |
| 6266 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6267 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6268 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6269 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6270 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass; |
| 6271 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6272 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6273 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6274 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6275 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6276 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass; |
| 6277 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6278 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass; |
| 6279 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6280 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6281 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6282 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass; |
| 6283 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6284 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6285 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass; |
| 6286 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass; |
| 6287 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass; |
| 6288 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass; |
| 6289 | extern const TargetRegisterClass GPR64x8Class_with_sub_32_in_GPR32argRegClass; |
| 6290 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64argRegClass; |
| 6291 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64argRegClass; |
| 6292 | extern const TargetRegisterClass rtcGPR64RegClass; |
| 6293 | extern const TargetRegisterClass GPR64sponlyRegClass; |
| 6294 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClass; |
| 6295 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClass; |
| 6296 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClass; |
| 6297 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_GPR64argRegClass; |
| 6298 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClass; |
| 6299 | extern const TargetRegisterClass DDRegClass; |
| 6300 | extern const TargetRegisterClass DD_with_dsub0_in_FPR64_loRegClass; |
| 6301 | extern const TargetRegisterClass DD_with_dsub1_in_FPR64_loRegClass; |
| 6302 | extern const TargetRegisterClass XSeqPairsClassRegClass; |
| 6303 | extern const TargetRegisterClass DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClass; |
| 6304 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass; |
| 6305 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass; |
| 6306 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass; |
| 6307 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass; |
| 6308 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass; |
| 6309 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass; |
| 6310 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass; |
| 6311 | extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass; |
| 6312 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass; |
| 6313 | extern const TargetRegisterClass FPR128RegClass; |
| 6314 | extern const TargetRegisterClass ZPRRegClass; |
| 6315 | extern const TargetRegisterClass FPR128_loRegClass; |
| 6316 | extern const TargetRegisterClass ZPR_4bRegClass; |
| 6317 | extern const TargetRegisterClass ZPR_3bRegClass; |
| 6318 | extern const TargetRegisterClass DDDRegClass; |
| 6319 | extern const TargetRegisterClass DDD_with_dsub0_in_FPR64_loRegClass; |
| 6320 | extern const TargetRegisterClass DDD_with_dsub1_in_FPR64_loRegClass; |
| 6321 | extern const TargetRegisterClass DDD_with_dsub2_in_FPR64_loRegClass; |
| 6322 | extern const TargetRegisterClass DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClass; |
| 6323 | extern const TargetRegisterClass DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass; |
| 6324 | extern const TargetRegisterClass DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass; |
| 6325 | extern const TargetRegisterClass DDDDRegClass; |
| 6326 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_loRegClass; |
| 6327 | extern const TargetRegisterClass DDDD_with_dsub1_in_FPR64_loRegClass; |
| 6328 | extern const TargetRegisterClass DDDD_with_dsub2_in_FPR64_loRegClass; |
| 6329 | extern const TargetRegisterClass DDDD_with_dsub3_in_FPR64_loRegClass; |
| 6330 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClass; |
| 6331 | extern const TargetRegisterClass DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass; |
| 6332 | extern const TargetRegisterClass DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass; |
| 6333 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass; |
| 6334 | extern const TargetRegisterClass DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass; |
| 6335 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass; |
| 6336 | extern const TargetRegisterClass QQRegClass; |
| 6337 | extern const TargetRegisterClass ZPR2RegClass; |
| 6338 | extern const TargetRegisterClass QQ_with_dsub_in_FPR64_loRegClass; |
| 6339 | extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass; |
| 6340 | extern const TargetRegisterClass ZPR2_with_dsub_in_FPR64_loRegClass; |
| 6341 | extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass; |
| 6342 | extern const TargetRegisterClass QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClass; |
| 6343 | extern const TargetRegisterClass ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass; |
| 6344 | extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass; |
| 6345 | extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass; |
| 6346 | extern const TargetRegisterClass ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass; |
| 6347 | extern const TargetRegisterClass QQQRegClass; |
| 6348 | extern const TargetRegisterClass ZPR3RegClass; |
| 6349 | extern const TargetRegisterClass QQQ_with_dsub_in_FPR64_loRegClass; |
| 6350 | extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass; |
| 6351 | extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass; |
| 6352 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_loRegClass; |
| 6353 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass; |
| 6354 | extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass; |
| 6355 | extern const TargetRegisterClass QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass; |
| 6356 | extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass; |
| 6357 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass; |
| 6358 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass; |
| 6359 | extern const TargetRegisterClass QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass; |
| 6360 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass; |
| 6361 | extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass; |
| 6362 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass; |
| 6363 | extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass; |
| 6364 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass; |
| 6365 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass; |
| 6366 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass; |
| 6367 | extern const TargetRegisterClass QQQQRegClass; |
| 6368 | extern const TargetRegisterClass ZPR4RegClass; |
| 6369 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_loRegClass; |
| 6370 | extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass; |
| 6371 | extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass; |
| 6372 | extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass; |
| 6373 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_loRegClass; |
| 6374 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass; |
| 6375 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass; |
| 6376 | extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass; |
| 6377 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass; |
| 6378 | extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass; |
| 6379 | extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass; |
| 6380 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass; |
| 6381 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass; |
| 6382 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass; |
| 6383 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass; |
| 6384 | extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass; |
| 6385 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass; |
| 6386 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass; |
| 6387 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass; |
| 6388 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass; |
| 6389 | extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass; |
| 6390 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass; |
| 6391 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass; |
| 6392 | extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass; |
| 6393 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass; |
| 6394 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass; |
| 6395 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass; |
| 6396 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass; |
| 6397 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass; |
| 6398 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass; |
| 6399 | } // end namespace AArch64 |
| 6400 | |
| 6401 | } // end namespace llvm |
| 6402 | |
| 6403 | #endif // GET_REGINFO_HEADER |
| 6404 | |
| 6405 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| 6406 | |* *| |
| 6407 | |* Target Register and Register Classes Information *| |
| 6408 | |* *| |
| 6409 | |* Automatically generated file, do not edit! *| |
| 6410 | |* *| |
| 6411 | \*===----------------------------------------------------------------------===*/ |
| 6412 | |
| 6413 | |
| 6414 | #ifdef GET_REGINFO_TARGET_DESC |
| 6415 | #undef GET_REGINFO_TARGET_DESC |
| 6416 | |
| 6417 | namespace llvm { |
| 6418 | |
| 6419 | extern const MCRegisterClass AArch64MCRegisterClasses[]; |
| 6420 | |
| 6421 | static const MVT::SimpleValueType VTLists[] = { |
| 6422 | /* 0 */ MVT::f32, MVT::i32, MVT::Other, |
| 6423 | /* 3 */ MVT::i64, MVT::Other, |
| 6424 | /* 5 */ MVT::f16, MVT::bf16, MVT::Other, |
| 6425 | /* 8 */ MVT::f16, MVT::Other, |
| 6426 | /* 10 */ MVT::f64, MVT::i64, MVT::v2f32, MVT::v1f64, MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::v4bf16, MVT::Other, |
| 6427 | /* 21 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::v8f16, MVT::v8bf16, MVT::Other, |
| 6428 | /* 31 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::Other, |
| 6429 | /* 40 */ MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64, MVT::v4f16, MVT::v4bf16, MVT::v2f32, MVT::v1f64, MVT::Other, |
| 6430 | /* 49 */ MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::Other, |
| 6431 | /* 54 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2bf16, MVT::nxv4bf16, MVT::nxv8bf16, MVT::nxv2f32, MVT::nxv4f32, MVT::nxv2f64, MVT::Other, |
| 6432 | /* 68 */ MVT::Untyped, MVT::Other, |
| 6433 | }; |
| 6434 | |
| 6435 | static const char *const SubRegIndexNameTable[] = { "bsub" , "dsub" , "dsub0" , "dsub1" , "dsub2" , "dsub3" , "hsub" , "qhisub" , "qsub" , "qsub0" , "qsub1" , "qsub2" , "qsub3" , "ssub" , "sub_32" , "sube32" , "sube64" , "subo32" , "subo64" , "x8sub_0" , "x8sub_1" , "x8sub_2" , "x8sub_3" , "x8sub_4" , "x8sub_5" , "x8sub_6" , "x8sub_7" , "zsub" , "zsub0" , "zsub1" , "zsub2" , "zsub3" , "zsub_hi" , "dsub1_then_bsub" , "dsub1_then_hsub" , "dsub1_then_ssub" , "dsub3_then_bsub" , "dsub3_then_hsub" , "dsub3_then_ssub" , "dsub2_then_bsub" , "dsub2_then_hsub" , "dsub2_then_ssub" , "qsub1_then_bsub" , "qsub1_then_dsub" , "qsub1_then_hsub" , "qsub1_then_ssub" , "qsub3_then_bsub" , "qsub3_then_dsub" , "qsub3_then_hsub" , "qsub3_then_ssub" , "qsub2_then_bsub" , "qsub2_then_dsub" , "qsub2_then_hsub" , "qsub2_then_ssub" , "x8sub_7_then_sub_32" , "x8sub_6_then_sub_32" , "x8sub_5_then_sub_32" , "x8sub_4_then_sub_32" , "x8sub_3_then_sub_32" , "x8sub_2_then_sub_32" , "x8sub_1_then_sub_32" , "subo64_then_sub_32" , "zsub1_then_bsub" , "zsub1_then_dsub" , "zsub1_then_hsub" , "zsub1_then_ssub" , "zsub1_then_zsub" , "zsub1_then_zsub_hi" , "zsub3_then_bsub" , "zsub3_then_dsub" , "zsub3_then_hsub" , "zsub3_then_ssub" , "zsub3_then_zsub" , "zsub3_then_zsub_hi" , "zsub2_then_bsub" , "zsub2_then_dsub" , "zsub2_then_hsub" , "zsub2_then_ssub" , "zsub2_then_zsub" , "zsub2_then_zsub_hi" , "dsub0_dsub1" , "dsub0_dsub1_dsub2" , "dsub1_dsub2" , "dsub1_dsub2_dsub3" , "dsub2_dsub3" , "dsub_qsub1_then_dsub" , "dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub" , "dsub_qsub1_then_dsub_qsub2_then_dsub" , "qsub0_qsub1" , "qsub0_qsub1_qsub2" , "qsub1_qsub2" , "qsub1_qsub2_qsub3" , "qsub2_qsub3" , "qsub1_then_dsub_qsub2_then_dsub" , "qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub" , "qsub2_then_dsub_qsub3_then_dsub" , "sub_32_x8sub_1_then_sub_32" , "x8sub_0_x8sub_1" , "x8sub_2_x8sub_3" , "x8sub_4_x8sub_5" , "x8sub_6_x8sub_7" , "x8sub_6_then_sub_32_x8sub_7_then_sub_32" , "x8sub_4_then_sub_32_x8sub_5_then_sub_32" , "x8sub_2_then_sub_32_x8sub_3_then_sub_32" , "sub_32_subo64_then_sub_32" , "dsub_zsub1_then_dsub" , "zsub_zsub1_then_zsub" , "dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub" , "dsub_zsub1_then_dsub_zsub2_then_dsub" , "zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub" , "zsub_zsub1_then_zsub_zsub2_then_zsub" , "zsub0_zsub1" , "zsub0_zsub1_zsub2" , "zsub1_zsub2" , "zsub1_zsub2_zsub3" , "zsub2_zsub3" , "zsub1_then_dsub_zsub2_then_dsub" , "zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub" , "zsub1_then_zsub_zsub2_then_zsub" , "zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub" , "zsub2_then_dsub_zsub3_then_dsub" , "zsub2_then_zsub_zsub3_then_zsub" , "" }; |
| 6436 | |
| 6437 | |
| 6438 | static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
| 6439 | LaneBitmask::getAll(), |
| 6440 | LaneBitmask(0x0000000000000001), // bsub |
| 6441 | LaneBitmask(0x0000000000000001), // dsub |
| 6442 | LaneBitmask(0x0000000000000001), // dsub0 |
| 6443 | LaneBitmask(0x0000000000000080), // dsub1 |
| 6444 | LaneBitmask(0x0000000000000200), // dsub2 |
| 6445 | LaneBitmask(0x0000000000000100), // dsub3 |
| 6446 | LaneBitmask(0x0000000000000001), // hsub |
| 6447 | LaneBitmask(0x0000000000000002), // qhisub |
| 6448 | LaneBitmask(0x0000000000000004), // qsub |
| 6449 | LaneBitmask(0x0000000000000001), // qsub0 |
| 6450 | LaneBitmask(0x0000000000000400), // qsub1 |
| 6451 | LaneBitmask(0x0000000000001000), // qsub2 |
| 6452 | LaneBitmask(0x0000000000000800), // qsub3 |
| 6453 | LaneBitmask(0x0000000000000001), // ssub |
| 6454 | LaneBitmask(0x0000000000000008), // sub_32 |
| 6455 | LaneBitmask(0x0000000000000010), // sube32 |
| 6456 | LaneBitmask(0x0000000000000008), // sube64 |
| 6457 | LaneBitmask(0x0000000000000020), // subo32 |
| 6458 | LaneBitmask(0x0000000000100000), // subo64 |
| 6459 | LaneBitmask(0x0000000000000008), // x8sub_0 |
| 6460 | LaneBitmask(0x0000000000080000), // x8sub_1 |
| 6461 | LaneBitmask(0x0000000000040000), // x8sub_2 |
| 6462 | LaneBitmask(0x0000000000020000), // x8sub_3 |
| 6463 | LaneBitmask(0x0000000000010000), // x8sub_4 |
| 6464 | LaneBitmask(0x0000000000008000), // x8sub_5 |
| 6465 | LaneBitmask(0x0000000000004000), // x8sub_6 |
| 6466 | LaneBitmask(0x0000000000002000), // x8sub_7 |
| 6467 | LaneBitmask(0x0000000000000001), // zsub |
| 6468 | LaneBitmask(0x0000000000000041), // zsub0 |
| 6469 | LaneBitmask(0x0000000000600000), // zsub1 |
| 6470 | LaneBitmask(0x0000000006000000), // zsub2 |
| 6471 | LaneBitmask(0x0000000001800000), // zsub3 |
| 6472 | LaneBitmask(0x0000000000000040), // zsub_hi |
| 6473 | LaneBitmask(0x0000000000000080), // dsub1_then_bsub |
| 6474 | LaneBitmask(0x0000000000000080), // dsub1_then_hsub |
| 6475 | LaneBitmask(0x0000000000000080), // dsub1_then_ssub |
| 6476 | LaneBitmask(0x0000000000000100), // dsub3_then_bsub |
| 6477 | LaneBitmask(0x0000000000000100), // dsub3_then_hsub |
| 6478 | LaneBitmask(0x0000000000000100), // dsub3_then_ssub |
| 6479 | LaneBitmask(0x0000000000000200), // dsub2_then_bsub |
| 6480 | LaneBitmask(0x0000000000000200), // dsub2_then_hsub |
| 6481 | LaneBitmask(0x0000000000000200), // dsub2_then_ssub |
| 6482 | LaneBitmask(0x0000000000000400), // qsub1_then_bsub |
| 6483 | LaneBitmask(0x0000000000000400), // qsub1_then_dsub |
| 6484 | LaneBitmask(0x0000000000000400), // qsub1_then_hsub |
| 6485 | LaneBitmask(0x0000000000000400), // qsub1_then_ssub |
| 6486 | LaneBitmask(0x0000000000000800), // qsub3_then_bsub |
| 6487 | LaneBitmask(0x0000000000000800), // qsub3_then_dsub |
| 6488 | LaneBitmask(0x0000000000000800), // qsub3_then_hsub |
| 6489 | LaneBitmask(0x0000000000000800), // qsub3_then_ssub |
| 6490 | LaneBitmask(0x0000000000001000), // qsub2_then_bsub |
| 6491 | LaneBitmask(0x0000000000001000), // qsub2_then_dsub |
| 6492 | LaneBitmask(0x0000000000001000), // qsub2_then_hsub |
| 6493 | LaneBitmask(0x0000000000001000), // qsub2_then_ssub |
| 6494 | LaneBitmask(0x0000000000002000), // x8sub_7_then_sub_32 |
| 6495 | LaneBitmask(0x0000000000004000), // x8sub_6_then_sub_32 |
| 6496 | LaneBitmask(0x0000000000008000), // x8sub_5_then_sub_32 |
| 6497 | LaneBitmask(0x0000000000010000), // x8sub_4_then_sub_32 |
| 6498 | LaneBitmask(0x0000000000020000), // x8sub_3_then_sub_32 |
| 6499 | LaneBitmask(0x0000000000040000), // x8sub_2_then_sub_32 |
| 6500 | LaneBitmask(0x0000000000080000), // x8sub_1_then_sub_32 |
| 6501 | LaneBitmask(0x0000000000100000), // subo64_then_sub_32 |
| 6502 | LaneBitmask(0x0000000000200000), // zsub1_then_bsub |
| 6503 | LaneBitmask(0x0000000000200000), // zsub1_then_dsub |
| 6504 | LaneBitmask(0x0000000000200000), // zsub1_then_hsub |
| 6505 | LaneBitmask(0x0000000000200000), // zsub1_then_ssub |
| 6506 | LaneBitmask(0x0000000000200000), // zsub1_then_zsub |
| 6507 | LaneBitmask(0x0000000000400000), // zsub1_then_zsub_hi |
| 6508 | LaneBitmask(0x0000000000800000), // zsub3_then_bsub |
| 6509 | LaneBitmask(0x0000000000800000), // zsub3_then_dsub |
| 6510 | LaneBitmask(0x0000000000800000), // zsub3_then_hsub |
| 6511 | LaneBitmask(0x0000000000800000), // zsub3_then_ssub |
| 6512 | LaneBitmask(0x0000000000800000), // zsub3_then_zsub |
| 6513 | LaneBitmask(0x0000000001000000), // zsub3_then_zsub_hi |
| 6514 | LaneBitmask(0x0000000002000000), // zsub2_then_bsub |
| 6515 | LaneBitmask(0x0000000002000000), // zsub2_then_dsub |
| 6516 | LaneBitmask(0x0000000002000000), // zsub2_then_hsub |
| 6517 | LaneBitmask(0x0000000002000000), // zsub2_then_ssub |
| 6518 | LaneBitmask(0x0000000002000000), // zsub2_then_zsub |
| 6519 | LaneBitmask(0x0000000004000000), // zsub2_then_zsub_hi |
| 6520 | LaneBitmask(0x0000000000000081), // dsub0_dsub1 |
| 6521 | LaneBitmask(0x0000000000000281), // dsub0_dsub1_dsub2 |
| 6522 | LaneBitmask(0x0000000000000280), // dsub1_dsub2 |
| 6523 | LaneBitmask(0x0000000000000380), // dsub1_dsub2_dsub3 |
| 6524 | LaneBitmask(0x0000000000000300), // dsub2_dsub3 |
| 6525 | LaneBitmask(0x0000000000000401), // dsub_qsub1_then_dsub |
| 6526 | LaneBitmask(0x0000000000001C01), // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 6527 | LaneBitmask(0x0000000000001401), // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 6528 | LaneBitmask(0x0000000000000401), // qsub0_qsub1 |
| 6529 | LaneBitmask(0x0000000000001401), // qsub0_qsub1_qsub2 |
| 6530 | LaneBitmask(0x0000000000001400), // qsub1_qsub2 |
| 6531 | LaneBitmask(0x0000000000001C00), // qsub1_qsub2_qsub3 |
| 6532 | LaneBitmask(0x0000000000001800), // qsub2_qsub3 |
| 6533 | LaneBitmask(0x0000000000001400), // qsub1_then_dsub_qsub2_then_dsub |
| 6534 | LaneBitmask(0x0000000000001C00), // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 6535 | LaneBitmask(0x0000000000001800), // qsub2_then_dsub_qsub3_then_dsub |
| 6536 | LaneBitmask(0x0000000000080008), // sub_32_x8sub_1_then_sub_32 |
| 6537 | LaneBitmask(0x0000000000080008), // x8sub_0_x8sub_1 |
| 6538 | LaneBitmask(0x0000000000060000), // x8sub_2_x8sub_3 |
| 6539 | LaneBitmask(0x0000000000018000), // x8sub_4_x8sub_5 |
| 6540 | LaneBitmask(0x0000000000006000), // x8sub_6_x8sub_7 |
| 6541 | LaneBitmask(0x0000000000006000), // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 6542 | LaneBitmask(0x0000000000018000), // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 6543 | LaneBitmask(0x0000000000060000), // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 6544 | LaneBitmask(0x0000000000100008), // sub_32_subo64_then_sub_32 |
| 6545 | LaneBitmask(0x0000000000200001), // dsub_zsub1_then_dsub |
| 6546 | LaneBitmask(0x0000000000200001), // zsub_zsub1_then_zsub |
| 6547 | LaneBitmask(0x0000000002A00001), // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 6548 | LaneBitmask(0x0000000002200001), // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 6549 | LaneBitmask(0x0000000002A00001), // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 6550 | LaneBitmask(0x0000000002200001), // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 6551 | LaneBitmask(0x0000000000600041), // zsub0_zsub1 |
| 6552 | LaneBitmask(0x0000000006600041), // zsub0_zsub1_zsub2 |
| 6553 | LaneBitmask(0x0000000006600000), // zsub1_zsub2 |
| 6554 | LaneBitmask(0x0000000007E00000), // zsub1_zsub2_zsub3 |
| 6555 | LaneBitmask(0x0000000007800000), // zsub2_zsub3 |
| 6556 | LaneBitmask(0x0000000002200000), // zsub1_then_dsub_zsub2_then_dsub |
| 6557 | LaneBitmask(0x0000000002A00000), // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 6558 | LaneBitmask(0x0000000002200000), // zsub1_then_zsub_zsub2_then_zsub |
| 6559 | LaneBitmask(0x0000000002A00000), // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 6560 | LaneBitmask(0x0000000002800000), // zsub2_then_dsub_zsub3_then_dsub |
| 6561 | LaneBitmask(0x0000000002800000), // zsub2_then_zsub_zsub3_then_zsub |
| 6562 | }; |
| 6563 | |
| 6564 | |
| 6565 | |
| 6566 | static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
| 6567 | // Mode = 0 (Default) |
| 6568 | { 8, 8, 8, VTLists+68 }, // FPR8 |
| 6569 | { 16, 16, 16, VTLists+5 }, // FPR16 |
| 6570 | { 16, 16, 16, VTLists+8 }, // FPR16_lo |
| 6571 | { 16, 16, 16, VTLists+49 }, // PPR |
| 6572 | { 16, 16, 16, VTLists+49 }, // PPR_3b |
| 6573 | { 32, 32, 32, VTLists+1 }, // GPR32all |
| 6574 | { 32, 32, 32, VTLists+0 }, // FPR32 |
| 6575 | { 32, 32, 32, VTLists+1 }, // GPR32 |
| 6576 | { 32, 32, 32, VTLists+1 }, // GPR32sp |
| 6577 | { 32, 32, 32, VTLists+1 }, // GPR32common |
| 6578 | { 32, 32, 32, VTLists+0 }, // FPR32_with_hsub_in_FPR16_lo |
| 6579 | { 32, 32, 32, VTLists+1 }, // GPR32arg |
| 6580 | { 32, 32, 32, VTLists+1 }, // CCR |
| 6581 | { 32, 32, 32, VTLists+1 }, // GPR32sponly |
| 6582 | { 64, 64, 32, VTLists+68 }, // WSeqPairsClass |
| 6583 | { 64, 64, 32, VTLists+68 }, // WSeqPairsClass_with_subo32_in_GPR32common |
| 6584 | { 64, 64, 32, VTLists+68 }, // WSeqPairsClass_with_sube32_in_GPR32arg |
| 6585 | { 64, 64, 64, VTLists+3 }, // GPR64all |
| 6586 | { 64, 64, 64, VTLists+10 }, // FPR64 |
| 6587 | { 64, 64, 64, VTLists+3 }, // GPR64 |
| 6588 | { 64, 64, 64, VTLists+3 }, // GPR64sp |
| 6589 | { 64, 64, 64, VTLists+3 }, // GPR64common |
| 6590 | { 64, 64, 64, VTLists+3 }, // GPR64noip |
| 6591 | { 64, 64, 64, VTLists+3 }, // GPR64common_and_GPR64noip |
| 6592 | { 64, 64, 64, VTLists+3 }, // tcGPR64 |
| 6593 | { 64, 64, 64, VTLists+3 }, // GPR64noip_and_tcGPR64 |
| 6594 | { 64, 64, 64, VTLists+40 }, // FPR64_lo |
| 6595 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class |
| 6596 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 6597 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 6598 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6599 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6600 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 6601 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6602 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6603 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 6604 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6605 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6606 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6607 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 6608 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 6609 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6610 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6611 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 6612 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6613 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6614 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6615 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6616 | { 64, 64, 64, VTLists+3 }, // GPR64arg |
| 6617 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 6618 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6619 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6620 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 6621 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6622 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6623 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6624 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6625 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 6626 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6627 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6628 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6629 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6630 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6631 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 6632 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6633 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 6634 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6635 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6636 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6637 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 6638 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6639 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6640 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 6641 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 6642 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 6643 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 6644 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_sub_32_in_GPR32arg |
| 6645 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 6646 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 6647 | { 64, 64, 64, VTLists+3 }, // rtcGPR64 |
| 6648 | { 64, 64, 64, VTLists+3 }, // GPR64sponly |
| 6649 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 6650 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 6651 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 6652 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 6653 | { 64, 64, 64, VTLists+3 }, // GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 6654 | { 128, 128, 64, VTLists+68 }, // DD |
| 6655 | { 128, 128, 64, VTLists+68 }, // DD_with_dsub0_in_FPR64_lo |
| 6656 | { 128, 128, 64, VTLists+68 }, // DD_with_dsub1_in_FPR64_lo |
| 6657 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass |
| 6658 | { 128, 128, 64, VTLists+68 }, // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 6659 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_subo64_in_GPR64common |
| 6660 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_subo64_in_GPR64noip |
| 6661 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_sube64_in_GPR64noip |
| 6662 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_sube64_in_tcGPR64 |
| 6663 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 6664 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_subo64_in_tcGPR64 |
| 6665 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 6666 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_sub_32_in_GPR32arg |
| 6667 | { 128, 128, 64, VTLists+68 }, // XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 6668 | { 128, 128, 128, VTLists+21 }, // FPR128 |
| 6669 | { 128, 128, 128, VTLists+54 }, // ZPR |
| 6670 | { 128, 128, 128, VTLists+31 }, // FPR128_lo |
| 6671 | { 128, 128, 128, VTLists+54 }, // ZPR_4b |
| 6672 | { 128, 128, 128, VTLists+54 }, // ZPR_3b |
| 6673 | { 192, 192, 64, VTLists+68 }, // DDD |
| 6674 | { 192, 192, 64, VTLists+68 }, // DDD_with_dsub0_in_FPR64_lo |
| 6675 | { 192, 192, 64, VTLists+68 }, // DDD_with_dsub1_in_FPR64_lo |
| 6676 | { 192, 192, 64, VTLists+68 }, // DDD_with_dsub2_in_FPR64_lo |
| 6677 | { 192, 192, 64, VTLists+68 }, // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 6678 | { 192, 192, 64, VTLists+68 }, // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 6679 | { 192, 192, 64, VTLists+68 }, // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 6680 | { 256, 256, 64, VTLists+68 }, // DDDD |
| 6681 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub0_in_FPR64_lo |
| 6682 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub1_in_FPR64_lo |
| 6683 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub2_in_FPR64_lo |
| 6684 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub3_in_FPR64_lo |
| 6685 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 6686 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 6687 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 6688 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 6689 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 6690 | { 256, 256, 64, VTLists+68 }, // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 6691 | { 256, 256, 128, VTLists+68 }, // QQ |
| 6692 | { 256, 256, 128, VTLists+68 }, // ZPR2 |
| 6693 | { 256, 256, 128, VTLists+68 }, // QQ_with_dsub_in_FPR64_lo |
| 6694 | { 256, 256, 128, VTLists+68 }, // QQ_with_qsub1_in_FPR128_lo |
| 6695 | { 256, 256, 128, VTLists+68 }, // ZPR2_with_dsub_in_FPR64_lo |
| 6696 | { 256, 256, 128, VTLists+68 }, // ZPR2_with_zsub1_in_ZPR_4b |
| 6697 | { 256, 256, 128, VTLists+68 }, // QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 6698 | { 256, 256, 128, VTLists+68 }, // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 6699 | { 256, 256, 128, VTLists+68 }, // ZPR2_with_zsub0_in_ZPR_3b |
| 6700 | { 256, 256, 128, VTLists+68 }, // ZPR2_with_zsub1_in_ZPR_3b |
| 6701 | { 256, 256, 128, VTLists+68 }, // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 6702 | { 384, 384, 128, VTLists+68 }, // QQQ |
| 6703 | { 384, 384, 128, VTLists+68 }, // ZPR3 |
| 6704 | { 384, 384, 128, VTLists+68 }, // QQQ_with_dsub_in_FPR64_lo |
| 6705 | { 384, 384, 128, VTLists+68 }, // QQQ_with_qsub1_in_FPR128_lo |
| 6706 | { 384, 384, 128, VTLists+68 }, // QQQ_with_qsub2_in_FPR128_lo |
| 6707 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_dsub_in_FPR64_lo |
| 6708 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub1_in_ZPR_4b |
| 6709 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub2_in_ZPR_4b |
| 6710 | { 384, 384, 128, VTLists+68 }, // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 6711 | { 384, 384, 128, VTLists+68 }, // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 6712 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 6713 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 6714 | { 384, 384, 128, VTLists+68 }, // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 6715 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 6716 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub0_in_ZPR_3b |
| 6717 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub1_in_ZPR_3b |
| 6718 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub2_in_ZPR_3b |
| 6719 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 6720 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 6721 | { 384, 384, 128, VTLists+68 }, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 6722 | { 512, 512, 128, VTLists+68 }, // QQQQ |
| 6723 | { 512, 512, 128, VTLists+68 }, // ZPR4 |
| 6724 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_dsub_in_FPR64_lo |
| 6725 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_qsub1_in_FPR128_lo |
| 6726 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_qsub2_in_FPR128_lo |
| 6727 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_qsub3_in_FPR128_lo |
| 6728 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo |
| 6729 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub1_in_ZPR_4b |
| 6730 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub2_in_ZPR_4b |
| 6731 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub3_in_ZPR_4b |
| 6732 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 6733 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 6734 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 6735 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 6736 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 6737 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 6738 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 6739 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 6740 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 6741 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 6742 | { 512, 512, 128, VTLists+68 }, // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 6743 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 6744 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub0_in_ZPR_3b |
| 6745 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub1_in_ZPR_3b |
| 6746 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub2_in_ZPR_3b |
| 6747 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub3_in_ZPR_3b |
| 6748 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 6749 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 6750 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 6751 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 6752 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 6753 | { 512, 512, 128, VTLists+68 }, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 6754 | }; |
| 6755 | |
| 6756 | static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
| 6757 | |
| 6758 | static const uint32_t FPR8SubClassMask[] = { |
| 6759 | 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6760 | 0x04040446, 0x00000000, 0x05c00000, 0xfffffff0, 0xffffffff, 0x03ffffff, // bsub |
| 6761 | 0x00000000, 0x00000000, 0x05c00000, 0x07fffe00, 0x00000000, 0x00000000, // dsub1_then_bsub |
| 6762 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub3_then_bsub |
| 6763 | 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, // dsub2_then_bsub |
| 6764 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // qsub1_then_bsub |
| 6765 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_bsub |
| 6766 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub2_then_bsub |
| 6767 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub1_then_bsub |
| 6768 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub3_then_bsub |
| 6769 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub2_then_bsub |
| 6770 | }; |
| 6771 | |
| 6772 | static const uint32_t FPR16SubClassMask[] = { |
| 6773 | 0x00000006, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6774 | 0x04040440, 0x00000000, 0x05c00000, 0xfffffff0, 0xffffffff, 0x03ffffff, // hsub |
| 6775 | 0x00000000, 0x00000000, 0x05c00000, 0x07fffe00, 0x00000000, 0x00000000, // dsub1_then_hsub |
| 6776 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub3_then_hsub |
| 6777 | 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, // dsub2_then_hsub |
| 6778 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // qsub1_then_hsub |
| 6779 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_hsub |
| 6780 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub2_then_hsub |
| 6781 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub1_then_hsub |
| 6782 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub3_then_hsub |
| 6783 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub2_then_hsub |
| 6784 | }; |
| 6785 | |
| 6786 | static const uint32_t FPR16_loSubClassMask[] = { |
| 6787 | 0x00000004, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6788 | 0x04000400, 0x00000000, 0x04800000, 0xa522a5c0, 0x129d492e, 0x0291d491, // hsub |
| 6789 | 0x00000000, 0x00000000, 0x05000000, 0x0764e800, 0x00000000, 0x00000000, // dsub1_then_hsub |
| 6790 | 0x00000000, 0x00000000, 0x00000000, 0x06900000, 0x00000000, 0x00000000, // dsub3_then_hsub |
| 6791 | 0x00000000, 0x00000000, 0x00000000, 0x07c8d000, 0x00000000, 0x00000000, // dsub2_then_hsub |
| 6792 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x2004c202, 0x00004c30, // qsub1_then_hsub |
| 6793 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub3_then_hsub |
| 6794 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // qsub2_then_hsub |
| 6795 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // zsub1_then_hsub |
| 6796 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub3_then_hsub |
| 6797 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub2_then_hsub |
| 6798 | }; |
| 6799 | |
| 6800 | static const uint32_t PPRSubClassMask[] = { |
| 6801 | 0x00000018, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6802 | }; |
| 6803 | |
| 6804 | static const uint32_t PPR_3bSubClassMask[] = { |
| 6805 | 0x00000010, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6806 | }; |
| 6807 | |
| 6808 | static const uint32_t GPR32allSubClassMask[] = { |
| 6809 | 0x00002ba0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6810 | 0xfbfa0000, 0xffffffff, 0xfa3fffff, 0x0000000f, 0x00000000, 0x00000000, // sub_32 |
| 6811 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sube32 |
| 6812 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // subo32 |
| 6813 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7_then_sub_32 |
| 6814 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32 |
| 6815 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5_then_sub_32 |
| 6816 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32 |
| 6817 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3_then_sub_32 |
| 6818 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32 |
| 6819 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1_then_sub_32 |
| 6820 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // subo64_then_sub_32 |
| 6821 | }; |
| 6822 | |
| 6823 | static const uint32_t FPR32SubClassMask[] = { |
| 6824 | 0x00000440, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6825 | 0x04040000, 0x00000000, 0x05c00000, 0xfffffff0, 0xffffffff, 0x03ffffff, // ssub |
| 6826 | 0x00000000, 0x00000000, 0x05c00000, 0x07fffe00, 0x00000000, 0x00000000, // dsub1_then_ssub |
| 6827 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub3_then_ssub |
| 6828 | 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, // dsub2_then_ssub |
| 6829 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // qsub1_then_ssub |
| 6830 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_ssub |
| 6831 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub2_then_ssub |
| 6832 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub1_then_ssub |
| 6833 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub3_then_ssub |
| 6834 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub2_then_ssub |
| 6835 | }; |
| 6836 | |
| 6837 | static const uint32_t GPR32SubClassMask[] = { |
| 6838 | 0x00000a80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6839 | 0xfbe80000, 0xffffffff, 0xfa3effff, 0x0000000f, 0x00000000, 0x00000000, // sub_32 |
| 6840 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sube32 |
| 6841 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // subo32 |
| 6842 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7_then_sub_32 |
| 6843 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32 |
| 6844 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5_then_sub_32 |
| 6845 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32 |
| 6846 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3_then_sub_32 |
| 6847 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32 |
| 6848 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1_then_sub_32 |
| 6849 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // subo64_then_sub_32 |
| 6850 | }; |
| 6851 | |
| 6852 | static const uint32_t GPR32spSubClassMask[] = { |
| 6853 | 0x00002b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6854 | 0xfbb00000, 0xffffffff, 0xfa3fffff, 0x0000000f, 0x00000000, 0x00000000, // sub_32 |
| 6855 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sube32 |
| 6856 | 0x00018000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // subo32 |
| 6857 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7_then_sub_32 |
| 6858 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32 |
| 6859 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5_then_sub_32 |
| 6860 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32 |
| 6861 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3_then_sub_32 |
| 6862 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32 |
| 6863 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1_then_sub_32 |
| 6864 | 0x00000000, 0x00000000, 0xe8000000, 0x0000000f, 0x00000000, 0x00000000, // subo64_then_sub_32 |
| 6865 | }; |
| 6866 | |
| 6867 | static const uint32_t GPR32commonSubClassMask[] = { |
| 6868 | 0x00000a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6869 | 0xfba00000, 0xffffffff, 0xfa3effff, 0x0000000f, 0x00000000, 0x00000000, // sub_32 |
| 6870 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sube32 |
| 6871 | 0x00018000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // subo32 |
| 6872 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7_then_sub_32 |
| 6873 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32 |
| 6874 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5_then_sub_32 |
| 6875 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32 |
| 6876 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3_then_sub_32 |
| 6877 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32 |
| 6878 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1_then_sub_32 |
| 6879 | 0x00000000, 0x00000000, 0xe8000000, 0x0000000f, 0x00000000, 0x00000000, // subo64_then_sub_32 |
| 6880 | }; |
| 6881 | |
| 6882 | static const uint32_t FPR32_with_hsub_in_FPR16_loSubClassMask[] = { |
| 6883 | 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6884 | 0x04000000, 0x00000000, 0x04800000, 0xa522a5c0, 0x129d492e, 0x0291d491, // ssub |
| 6885 | 0x00000000, 0x00000000, 0x05000000, 0x0764e800, 0x00000000, 0x00000000, // dsub1_then_ssub |
| 6886 | 0x00000000, 0x00000000, 0x00000000, 0x06900000, 0x00000000, 0x00000000, // dsub3_then_ssub |
| 6887 | 0x00000000, 0x00000000, 0x00000000, 0x07c8d000, 0x00000000, 0x00000000, // dsub2_then_ssub |
| 6888 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x2004c202, 0x00004c30, // qsub1_then_ssub |
| 6889 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub3_then_ssub |
| 6890 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // qsub2_then_ssub |
| 6891 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // zsub1_then_ssub |
| 6892 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub3_then_ssub |
| 6893 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub2_then_ssub |
| 6894 | }; |
| 6895 | |
| 6896 | static const uint32_t GPR32argSubClassMask[] = { |
| 6897 | 0x00000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6898 | 0x00000000, 0x00010000, 0x00107000, 0x00000004, 0x00000000, 0x00000000, // sub_32 |
| 6899 | 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // sube32 |
| 6900 | 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, // subo32 |
| 6901 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, // x8sub_7_then_sub_32 |
| 6902 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32 |
| 6903 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, // x8sub_5_then_sub_32 |
| 6904 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32 |
| 6905 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, // x8sub_3_then_sub_32 |
| 6906 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32 |
| 6907 | 0x00000000, 0x00000000, 0x00107000, 0x00000000, 0x00000000, 0x00000000, // x8sub_1_then_sub_32 |
| 6908 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, // subo64_then_sub_32 |
| 6909 | }; |
| 6910 | |
| 6911 | static const uint32_t CCRSubClassMask[] = { |
| 6912 | 0x00001000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6913 | }; |
| 6914 | |
| 6915 | static const uint32_t GPR32sponlySubClassMask[] = { |
| 6916 | 0x00002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6917 | 0x00000000, 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, // sub_32 |
| 6918 | }; |
| 6919 | |
| 6920 | static const uint32_t WSeqPairsClassSubClassMask[] = { |
| 6921 | 0x0001c000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6922 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // sub_32_x8sub_1_then_sub_32 |
| 6923 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 6924 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 6925 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 6926 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32 |
| 6927 | }; |
| 6928 | |
| 6929 | static const uint32_t WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask[] = { |
| 6930 | 0x00018000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6931 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // sub_32_x8sub_1_then_sub_32 |
| 6932 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 6933 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 6934 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 6935 | 0x00000000, 0x00000000, 0xe8000000, 0x0000000f, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32 |
| 6936 | }; |
| 6937 | |
| 6938 | static const uint32_t WSeqPairsClass_with_sube32_in_GPR32argSubClassMask[] = { |
| 6939 | 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6940 | 0x00000000, 0x00000000, 0x00107000, 0x00000000, 0x00000000, 0x00000000, // sub_32_x8sub_1_then_sub_32 |
| 6941 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 6942 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 6943 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 6944 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, // sub_32_subo64_then_sub_32 |
| 6945 | }; |
| 6946 | |
| 6947 | static const uint32_t GPR64allSubClassMask[] = { |
| 6948 | 0x03fa0000, 0x00010000, 0x00018000, 0x00000000, 0x00000000, 0x00000000, |
| 6949 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // sube64 |
| 6950 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // subo64 |
| 6951 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 6952 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 6953 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 6954 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 6955 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 6956 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 6957 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 6958 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 6959 | }; |
| 6960 | |
| 6961 | static const uint32_t FPR64SubClassMask[] = { |
| 6962 | 0x04040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 6963 | 0x00000000, 0x00000000, 0x00000000, 0xf80001f0, 0xffffffff, 0x03ffffff, // dsub |
| 6964 | 0x00000000, 0x00000000, 0x05c00000, 0x07fffe00, 0x00000000, 0x00000000, // dsub0 |
| 6965 | 0x00000000, 0x00000000, 0x05c00000, 0x07fffe00, 0x00000000, 0x00000000, // dsub1 |
| 6966 | 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, // dsub2 |
| 6967 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub3 |
| 6968 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // qsub1_then_dsub |
| 6969 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub3_then_dsub |
| 6970 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub2_then_dsub |
| 6971 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub1_then_dsub |
| 6972 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub3_then_dsub |
| 6973 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub2_then_dsub |
| 6974 | }; |
| 6975 | |
| 6976 | static const uint32_t GPR64SubClassMask[] = { |
| 6977 | 0x03e80000, 0x00010000, 0x00008000, 0x00000000, 0x00000000, 0x00000000, |
| 6978 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // sube64 |
| 6979 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // subo64 |
| 6980 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 6981 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 6982 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 6983 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 6984 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 6985 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 6986 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 6987 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 6988 | }; |
| 6989 | |
| 6990 | static const uint32_t GPR64spSubClassMask[] = { |
| 6991 | 0x03b00000, 0x00010000, 0x00018000, 0x00000000, 0x00000000, 0x00000000, |
| 6992 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // sube64 |
| 6993 | 0x00000000, 0x00000000, 0xe8000000, 0x0000000f, 0x00000000, 0x00000000, // subo64 |
| 6994 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 6995 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 6996 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 6997 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 6998 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 6999 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7000 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7001 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7002 | }; |
| 7003 | |
| 7004 | static const uint32_t GPR64commonSubClassMask[] = { |
| 7005 | 0x03a00000, 0x00010000, 0x00008000, 0x00000000, 0x00000000, 0x00000000, |
| 7006 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, // sube64 |
| 7007 | 0x00000000, 0x00000000, 0xe8000000, 0x0000000f, 0x00000000, 0x00000000, // subo64 |
| 7008 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7009 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7010 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7011 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7012 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7013 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7014 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7015 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7016 | }; |
| 7017 | |
| 7018 | static const uint32_t GPR64noipSubClassMask[] = { |
| 7019 | 0x02c00000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 7020 | 0x00000000, 0x00000000, 0xa0000000, 0x00000006, 0x00000000, 0x00000000, // sube64 |
| 7021 | 0x00000000, 0x00000000, 0xb0000000, 0x00000006, 0x00000000, 0x00000000, // subo64 |
| 7022 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7023 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7024 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7025 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7026 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7027 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7028 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7029 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7030 | }; |
| 7031 | |
| 7032 | static const uint32_t GPR64common_and_GPR64noipSubClassMask[] = { |
| 7033 | 0x02800000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 7034 | 0x00000000, 0x00000000, 0xa0000000, 0x00000006, 0x00000000, 0x00000000, // sube64 |
| 7035 | 0x00000000, 0x00000000, 0xa0000000, 0x00000006, 0x00000000, 0x00000000, // subo64 |
| 7036 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7037 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7038 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7039 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7040 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7041 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7042 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7043 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7044 | }; |
| 7045 | |
| 7046 | static const uint32_t tcGPR64SubClassMask[] = { |
| 7047 | 0x03000000, 0x00010000, 0x00008000, 0x00000000, 0x00000000, 0x00000000, |
| 7048 | 0x00000000, 0x00000000, 0xc0000000, 0x0000000f, 0x00000000, 0x00000000, // sube64 |
| 7049 | 0x00000000, 0x00000000, 0x00000000, 0x0000000f, 0x00000000, 0x00000000, // subo64 |
| 7050 | 0x00000000, 0xf7fe0f88, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7051 | 0x00000000, 0x92700800, 0x003e7f6b, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7052 | 0x00000000, 0x92700800, 0x003e7f6b, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7053 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7054 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7055 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7056 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7057 | 0x00000000, 0x00000000, 0x00307a00, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7058 | }; |
| 7059 | |
| 7060 | static const uint32_t GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7061 | 0x02000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 7062 | 0x00000000, 0x00000000, 0x80000000, 0x00000006, 0x00000000, 0x00000000, // sube64 |
| 7063 | 0x00000000, 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000, // subo64 |
| 7064 | 0x00000000, 0x701e0080, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7065 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7066 | 0x00000000, 0x82000000, 0x003a7f03, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7067 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7068 | 0x00000000, 0x00000000, 0x00347a60, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7069 | 0x00000000, 0x00000000, 0x00307a00, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7070 | 0x00000000, 0x00000000, 0x00187c00, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7071 | 0x00000000, 0x00000000, 0x00107800, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7072 | }; |
| 7073 | |
| 7074 | static const uint32_t FPR64_loSubClassMask[] = { |
| 7075 | 0x04000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 7076 | 0x00000000, 0x00000000, 0x00000000, 0xa00001c0, 0x129d492e, 0x0291d491, // dsub |
| 7077 | 0x00000000, 0x00000000, 0x04800000, 0x0522a400, 0x00000000, 0x00000000, // dsub0 |
| 7078 | 0x00000000, 0x00000000, 0x05000000, 0x0764e800, 0x00000000, 0x00000000, // dsub1 |
| 7079 | 0x00000000, 0x00000000, 0x00000000, 0x07c8d000, 0x00000000, 0x00000000, // dsub2 |
| 7080 | 0x00000000, 0x00000000, 0x00000000, 0x06900000, 0x00000000, 0x00000000, // dsub3 |
| 7081 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x2004c202, 0x00004c30, // qsub1_then_dsub |
| 7082 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub3_then_dsub |
| 7083 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // qsub2_then_dsub |
| 7084 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // zsub1_then_dsub |
| 7085 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub3_then_dsub |
| 7086 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub2_then_dsub |
| 7087 | }; |
| 7088 | |
| 7089 | static const uint32_t GPR64x8ClassSubClassMask[] = { |
| 7090 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, |
| 7091 | }; |
| 7092 | |
| 7093 | static const uint32_t GPR64x8Class_with_x8sub_0_in_GPR64noipSubClassMask[] = { |
| 7094 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, |
| 7095 | }; |
| 7096 | |
| 7097 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask[] = { |
| 7098 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, |
| 7099 | }; |
| 7100 | |
| 7101 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7102 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, |
| 7103 | }; |
| 7104 | |
| 7105 | static const uint32_t GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7106 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, |
| 7107 | }; |
| 7108 | |
| 7109 | static const uint32_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask[] = { |
| 7110 | 0x00000000, 0x68023001, 0x00387e82, 0x00000000, 0x00000000, 0x00000000, |
| 7111 | }; |
| 7112 | |
| 7113 | static const uint32_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7114 | 0x00000000, 0x28045002, 0x00347ae4, 0x00000000, 0x00000000, 0x00000000, |
| 7115 | }; |
| 7116 | |
| 7117 | static const uint32_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7118 | 0x00000000, 0x58086004, 0x001c7cc4, 0x00000000, 0x00000000, 0x00000000, |
| 7119 | }; |
| 7120 | |
| 7121 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64SubClassMask[] = { |
| 7122 | 0x00000000, 0xf7fe0f88, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, |
| 7123 | }; |
| 7124 | |
| 7125 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7126 | 0x00000000, 0xa8809010, 0x00327b90, 0x00000000, 0x00000000, 0x00000000, |
| 7127 | }; |
| 7128 | |
| 7129 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7130 | 0x00000000, 0x4900a020, 0x001a7d91, 0x00000000, 0x00000000, 0x00000000, |
| 7131 | }; |
| 7132 | |
| 7133 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7134 | 0x00000000, 0x0c00c040, 0x001679dc, 0x00000000, 0x00000000, 0x00000000, |
| 7135 | }; |
| 7136 | |
| 7137 | static const uint32_t GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7138 | 0x00000000, 0x701e0080, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, |
| 7139 | }; |
| 7140 | |
| 7141 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask[] = { |
| 7142 | 0x00000000, 0xe3820100, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, |
| 7143 | }; |
| 7144 | |
| 7145 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7146 | 0x00000000, 0xa4a40200, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, |
| 7147 | }; |
| 7148 | |
| 7149 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7150 | 0x00000000, 0x55480400, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, |
| 7151 | }; |
| 7152 | |
| 7153 | static const uint32_t GPR64x8Class_with_x8sub_1_in_tcGPR64SubClassMask[] = { |
| 7154 | 0x00000000, 0x92700800, 0x003e7f6b, 0x00000000, 0x00000000, 0x00000000, |
| 7155 | }; |
| 7156 | |
| 7157 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7158 | 0x00000000, 0x28001000, 0x00307a80, 0x00000000, 0x00000000, 0x00000000, |
| 7159 | }; |
| 7160 | |
| 7161 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7162 | 0x00000000, 0x48002000, 0x00187c80, 0x00000000, 0x00000000, 0x00000000, |
| 7163 | }; |
| 7164 | |
| 7165 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7166 | 0x00000000, 0x08004000, 0x001478c4, 0x00000000, 0x00000000, 0x00000000, |
| 7167 | }; |
| 7168 | |
| 7169 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7170 | 0x00000000, 0x08008000, 0x00127990, 0x00000000, 0x00000000, 0x00000000, |
| 7171 | }; |
| 7172 | |
| 7173 | static const uint32_t GPR64argSubClassMask[] = { |
| 7174 | 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 7175 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, // sube64 |
| 7176 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, // subo64 |
| 7177 | 0x00000000, 0x00000000, 0x00107000, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7178 | 0x00000000, 0x00000000, 0x00107000, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7179 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7180 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7181 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7182 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7183 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7184 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7185 | }; |
| 7186 | |
| 7187 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask[] = { |
| 7188 | 0x00000000, 0x60020000, 0x00387e82, 0x00000000, 0x00000000, 0x00000000, |
| 7189 | }; |
| 7190 | |
| 7191 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7192 | 0x00000000, 0x20040000, 0x00347ae4, 0x00000000, 0x00000000, 0x00000000, |
| 7193 | }; |
| 7194 | |
| 7195 | static const uint32_t GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7196 | 0x00000000, 0x50080000, 0x001c7cc4, 0x00000000, 0x00000000, 0x00000000, |
| 7197 | }; |
| 7198 | |
| 7199 | static const uint32_t GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7200 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, |
| 7201 | }; |
| 7202 | |
| 7203 | static const uint32_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7204 | 0x00000000, 0x80200000, 0x00367b68, 0x00000000, 0x00000000, 0x00000000, |
| 7205 | }; |
| 7206 | |
| 7207 | static const uint32_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7208 | 0x00000000, 0x10400000, 0x001e7d49, 0x00000000, 0x00000000, 0x00000000, |
| 7209 | }; |
| 7210 | |
| 7211 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7212 | 0x00000000, 0xa0800000, 0x00327b90, 0x00000000, 0x00000000, 0x00000000, |
| 7213 | }; |
| 7214 | |
| 7215 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7216 | 0x00000000, 0x41000000, 0x001a7d91, 0x00000000, 0x00000000, 0x00000000, |
| 7217 | }; |
| 7218 | |
| 7219 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7220 | 0x00000000, 0x82000000, 0x003a7f03, 0x00000000, 0x00000000, 0x00000000, |
| 7221 | }; |
| 7222 | |
| 7223 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7224 | 0x00000000, 0x04000000, 0x001679dc, 0x00000000, 0x00000000, 0x00000000, |
| 7225 | }; |
| 7226 | |
| 7227 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7228 | 0x00000000, 0x08000000, 0x00107880, 0x00000000, 0x00000000, 0x00000000, |
| 7229 | }; |
| 7230 | |
| 7231 | static const uint32_t GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7232 | 0x00000000, 0x10000000, 0x001c7c40, 0x00000000, 0x00000000, 0x00000000, |
| 7233 | }; |
| 7234 | |
| 7235 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7236 | 0x00000000, 0x20000000, 0x00307a80, 0x00000000, 0x00000000, 0x00000000, |
| 7237 | }; |
| 7238 | |
| 7239 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7240 | 0x00000000, 0x40000000, 0x00187c80, 0x00000000, 0x00000000, 0x00000000, |
| 7241 | }; |
| 7242 | |
| 7243 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask[] = { |
| 7244 | 0x00000000, 0x80000000, 0x00327b00, 0x00000000, 0x00000000, 0x00000000, |
| 7245 | }; |
| 7246 | |
| 7247 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7248 | 0x00000000, 0x00000000, 0x001a7d01, 0x00000000, 0x00000000, 0x00000000, |
| 7249 | }; |
| 7250 | |
| 7251 | static const uint32_t GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7252 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, |
| 7253 | }; |
| 7254 | |
| 7255 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7256 | 0x00000000, 0x00000000, 0x001478c4, 0x00000000, 0x00000000, 0x00000000, |
| 7257 | }; |
| 7258 | |
| 7259 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7260 | 0x00000000, 0x00000000, 0x00167948, 0x00000000, 0x00000000, 0x00000000, |
| 7261 | }; |
| 7262 | |
| 7263 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7264 | 0x00000000, 0x00000000, 0x00127990, 0x00000000, 0x00000000, 0x00000000, |
| 7265 | }; |
| 7266 | |
| 7267 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7268 | 0x00000000, 0x00000000, 0x00347a60, 0x00000000, 0x00000000, 0x00000000, |
| 7269 | }; |
| 7270 | |
| 7271 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7272 | 0x00000000, 0x00000000, 0x00147840, 0x00000000, 0x00000000, 0x00000000, |
| 7273 | }; |
| 7274 | |
| 7275 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7276 | 0x00000000, 0x00000000, 0x00107880, 0x00000000, 0x00000000, 0x00000000, |
| 7277 | }; |
| 7278 | |
| 7279 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask[] = { |
| 7280 | 0x00000000, 0x00000000, 0x00127900, 0x00000000, 0x00000000, 0x00000000, |
| 7281 | }; |
| 7282 | |
| 7283 | static const uint32_t GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7284 | 0x00000000, 0x00000000, 0x00307a00, 0x00000000, 0x00000000, 0x00000000, |
| 7285 | }; |
| 7286 | |
| 7287 | static const uint32_t GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7288 | 0x00000000, 0x00000000, 0x00187c00, 0x00000000, 0x00000000, 0x00000000, |
| 7289 | }; |
| 7290 | |
| 7291 | static const uint32_t GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7292 | 0x00000000, 0x00000000, 0x00107800, 0x00000000, 0x00000000, 0x00000000, |
| 7293 | }; |
| 7294 | |
| 7295 | static const uint32_t GPR64x8Class_with_sub_32_in_GPR32argSubClassMask[] = { |
| 7296 | 0x00000000, 0x00000000, 0x00107000, 0x00000000, 0x00000000, 0x00000000, |
| 7297 | }; |
| 7298 | |
| 7299 | static const uint32_t GPR64x8Class_with_x8sub_2_in_GPR64argSubClassMask[] = { |
| 7300 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, |
| 7301 | }; |
| 7302 | |
| 7303 | static const uint32_t GPR64x8Class_with_x8sub_4_in_GPR64argSubClassMask[] = { |
| 7304 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, |
| 7305 | }; |
| 7306 | |
| 7307 | static const uint32_t rtcGPR64SubClassMask[] = { |
| 7308 | 0x00000000, 0x00000000, 0x00008000, 0x00000000, 0x00000000, 0x00000000, |
| 7309 | 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, // sube64 |
| 7310 | 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, // subo64 |
| 7311 | 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, // x8sub_0 |
| 7312 | 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, // x8sub_1 |
| 7313 | 0x00000000, 0x00000000, 0x00040000, 0x00000000, 0x00000000, 0x00000000, // x8sub_2 |
| 7314 | 0x00000000, 0x00000000, 0x00040000, 0x00000000, 0x00000000, 0x00000000, // x8sub_3 |
| 7315 | 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, 0x00000000, // x8sub_4 |
| 7316 | 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, 0x00000000, // x8sub_5 |
| 7317 | 0x00000000, 0x00000000, 0x00200000, 0x00000000, 0x00000000, 0x00000000, // x8sub_6 |
| 7318 | 0x00000000, 0x00000000, 0x00200000, 0x00000000, 0x00000000, 0x00000000, // x8sub_7 |
| 7319 | }; |
| 7320 | |
| 7321 | static const uint32_t GPR64sponlySubClassMask[] = { |
| 7322 | 0x00000000, 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000, |
| 7323 | }; |
| 7324 | |
| 7325 | static const uint32_t GPR64x8Class_with_x8sub_0_in_rtcGPR64SubClassMask[] = { |
| 7326 | 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, |
| 7327 | }; |
| 7328 | |
| 7329 | static const uint32_t GPR64x8Class_with_x8sub_2_in_rtcGPR64SubClassMask[] = { |
| 7330 | 0x00000000, 0x00000000, 0x00040000, 0x00000000, 0x00000000, 0x00000000, |
| 7331 | }; |
| 7332 | |
| 7333 | static const uint32_t GPR64x8Class_with_x8sub_4_in_rtcGPR64SubClassMask[] = { |
| 7334 | 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, 0x00000000, |
| 7335 | }; |
| 7336 | |
| 7337 | static const uint32_t GPR64x8Class_with_x8sub_6_in_GPR64argSubClassMask[] = { |
| 7338 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, |
| 7339 | }; |
| 7340 | |
| 7341 | static const uint32_t GPR64x8Class_with_x8sub_6_in_rtcGPR64SubClassMask[] = { |
| 7342 | 0x00000000, 0x00000000, 0x00200000, 0x00000000, 0x00000000, 0x00000000, |
| 7343 | }; |
| 7344 | |
| 7345 | static const uint32_t DDSubClassMask[] = { |
| 7346 | 0x00000000, 0x00000000, 0x05c00000, 0x00000000, 0x00000000, 0x00000000, |
| 7347 | 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, // dsub0_dsub1 |
| 7348 | 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, // dsub1_dsub2 |
| 7349 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub2_dsub3 |
| 7350 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // dsub_qsub1_then_dsub |
| 7351 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub1_then_dsub_qsub2_then_dsub |
| 7352 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub2_then_dsub_qsub3_then_dsub |
| 7353 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // dsub_zsub1_then_dsub |
| 7354 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub1_then_dsub_zsub2_then_dsub |
| 7355 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub2_then_dsub_zsub3_then_dsub |
| 7356 | }; |
| 7357 | |
| 7358 | static const uint32_t DD_with_dsub0_in_FPR64_loSubClassMask[] = { |
| 7359 | 0x00000000, 0x00000000, 0x04800000, 0x00000000, 0x00000000, 0x00000000, |
| 7360 | 0x00000000, 0x00000000, 0x00000000, 0x0522a400, 0x00000000, 0x00000000, // dsub0_dsub1 |
| 7361 | 0x00000000, 0x00000000, 0x00000000, 0x0764e800, 0x00000000, 0x00000000, // dsub1_dsub2 |
| 7362 | 0x00000000, 0x00000000, 0x00000000, 0x07c80000, 0x00000000, 0x00000000, // dsub2_dsub3 |
| 7363 | 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x10044102, 0x00004410, // dsub_qsub1_then_dsub |
| 7364 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2004c200, 0x00004c30, // qsub1_then_dsub_qsub2_then_dsub |
| 7365 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, // qsub2_then_dsub_qsub3_then_dsub |
| 7366 | 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0299082c, 0x02919081, // dsub_zsub1_then_dsub |
| 7367 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x03b3b182, // zsub1_then_dsub_zsub2_then_dsub |
| 7368 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub2_then_dsub_zsub3_then_dsub |
| 7369 | }; |
| 7370 | |
| 7371 | static const uint32_t DD_with_dsub1_in_FPR64_loSubClassMask[] = { |
| 7372 | 0x00000000, 0x00000000, 0x05000000, 0x00000000, 0x00000000, 0x00000000, |
| 7373 | 0x00000000, 0x00000000, 0x00000000, 0x0764e800, 0x00000000, 0x00000000, // dsub0_dsub1 |
| 7374 | 0x00000000, 0x00000000, 0x00000000, 0x07c8d000, 0x00000000, 0x00000000, // dsub1_dsub2 |
| 7375 | 0x00000000, 0x00000000, 0x00000000, 0x06900000, 0x00000000, 0x00000000, // dsub2_dsub3 |
| 7376 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x2004c202, 0x00004c30, // dsub_qsub1_then_dsub |
| 7377 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // qsub1_then_dsub_qsub2_then_dsub |
| 7378 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub2_then_dsub_qsub3_then_dsub |
| 7379 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // dsub_zsub1_then_dsub |
| 7380 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub1_then_dsub_zsub2_then_dsub |
| 7381 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub2_then_dsub_zsub3_then_dsub |
| 7382 | }; |
| 7383 | |
| 7384 | static const uint32_t XSeqPairsClassSubClassMask[] = { |
| 7385 | 0x00000000, 0x00000000, 0xfa000000, 0x0000000f, 0x00000000, 0x00000000, |
| 7386 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7387 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7388 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7389 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7390 | }; |
| 7391 | |
| 7392 | static const uint32_t DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loSubClassMask[] = { |
| 7393 | 0x00000000, 0x00000000, 0x04000000, 0x00000000, 0x00000000, 0x00000000, |
| 7394 | 0x00000000, 0x00000000, 0x00000000, 0x0520a000, 0x00000000, 0x00000000, // dsub0_dsub1 |
| 7395 | 0x00000000, 0x00000000, 0x00000000, 0x0740c000, 0x00000000, 0x00000000, // dsub1_dsub2 |
| 7396 | 0x00000000, 0x00000000, 0x00000000, 0x06800000, 0x00000000, 0x00000000, // dsub2_dsub3 |
| 7397 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00044002, 0x00004410, // dsub_qsub1_then_dsub |
| 7398 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00048000, 0x00004c20, // qsub1_then_dsub_qsub2_then_dsub |
| 7399 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004840, // qsub2_then_dsub_qsub3_then_dsub |
| 7400 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0299002c, 0x02919080, // dsub_zsub1_then_dsub |
| 7401 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ba0000, 0x03b3b100, // zsub1_then_dsub_zsub2_then_dsub |
| 7402 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub2_then_dsub_zsub3_then_dsub |
| 7403 | }; |
| 7404 | |
| 7405 | static const uint32_t XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask[] = { |
| 7406 | 0x00000000, 0x00000000, 0xe8000000, 0x0000000f, 0x00000000, 0x00000000, |
| 7407 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7408 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7409 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7410 | 0xf8000000, 0xfffeffff, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7411 | }; |
| 7412 | |
| 7413 | static const uint32_t XSeqPairsClass_with_subo64_in_GPR64noipSubClassMask[] = { |
| 7414 | 0x00000000, 0x00000000, 0xb0000000, 0x00000006, 0x00000000, 0x00000000, |
| 7415 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7416 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7417 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7418 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7419 | }; |
| 7420 | |
| 7421 | static const uint32_t XSeqPairsClass_with_sube64_in_GPR64noipSubClassMask[] = { |
| 7422 | 0x00000000, 0x00000000, 0xa0000000, 0x00000006, 0x00000000, 0x00000000, |
| 7423 | 0x10000000, 0x781e7087, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7424 | 0x20000000, 0xeb82b131, 0x003a7f93, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7425 | 0x40000000, 0xaca4d252, 0x00367bfc, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7426 | 0x80000000, 0x5d48e464, 0x001e7ddd, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7427 | }; |
| 7428 | |
| 7429 | static const uint32_t XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask[] = { |
| 7430 | 0x00000000, 0x00000000, 0xc0000000, 0x0000000f, 0x00000000, 0x00000000, |
| 7431 | 0x00000000, 0xf7fe0f88, 0x003e7fff, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7432 | 0x00000000, 0x92700800, 0x003e7f6b, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7433 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7434 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7435 | }; |
| 7436 | |
| 7437 | static const uint32_t XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7438 | 0x00000000, 0x00000000, 0x80000000, 0x00000006, 0x00000000, 0x00000000, |
| 7439 | 0x00000000, 0x701e0080, 0x003c7ee6, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7440 | 0x00000000, 0x82000000, 0x003a7f03, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7441 | 0x00000000, 0x00000000, 0x00347a60, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7442 | 0x00000000, 0x00000000, 0x00187c00, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7443 | }; |
| 7444 | |
| 7445 | static const uint32_t XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask[] = { |
| 7446 | 0x00000000, 0x00000000, 0x00000000, 0x0000000f, 0x00000000, 0x00000000, |
| 7447 | 0x00000000, 0x92700800, 0x003e7f6b, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7448 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7449 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7450 | 0x00000000, 0x00000000, 0x00307a00, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7451 | }; |
| 7452 | |
| 7453 | static const uint32_t XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64SubClassMask[] = { |
| 7454 | 0x00000000, 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000, |
| 7455 | 0x00000000, 0x10100000, 0x003c7e62, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7456 | 0x00000000, 0x00000000, 0x00387e02, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7457 | 0x00000000, 0x00000000, 0x00307a00, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7458 | 0x00000000, 0x00000000, 0x00107800, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7459 | }; |
| 7460 | |
| 7461 | static const uint32_t XSeqPairsClass_with_sub_32_in_GPR32argSubClassMask[] = { |
| 7462 | 0x00000000, 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, |
| 7463 | 0x00000000, 0x00000000, 0x00107000, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7464 | 0x00000000, 0x00000000, 0x00106000, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7465 | 0x00000000, 0x00000000, 0x00104000, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7466 | 0x00000000, 0x00000000, 0x00100000, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7467 | }; |
| 7468 | |
| 7469 | static const uint32_t XSeqPairsClass_with_sube64_in_rtcGPR64SubClassMask[] = { |
| 7470 | 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, 0x00000000, |
| 7471 | 0x00000000, 0x00000000, 0x00020000, 0x00000000, 0x00000000, 0x00000000, // x8sub_0_x8sub_1 |
| 7472 | 0x00000000, 0x00000000, 0x00040000, 0x00000000, 0x00000000, 0x00000000, // x8sub_2_x8sub_3 |
| 7473 | 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, 0x00000000, // x8sub_4_x8sub_5 |
| 7474 | 0x00000000, 0x00000000, 0x00200000, 0x00000000, 0x00000000, 0x00000000, // x8sub_6_x8sub_7 |
| 7475 | }; |
| 7476 | |
| 7477 | static const uint32_t FPR128SubClassMask[] = { |
| 7478 | 0x00000000, 0x00000000, 0x00000000, 0x00000050, 0x00000000, 0x00000000, |
| 7479 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // qsub0 |
| 7480 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0xf404c742, 0x00004c70, // qsub1 |
| 7481 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub2 |
| 7482 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub3 |
| 7483 | 0x00000000, 0x00000000, 0x00000000, 0x900001a0, 0x0bfb38bd, 0x03ffb38f, // zsub |
| 7484 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub1_then_zsub |
| 7485 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub3_then_zsub |
| 7486 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub2_then_zsub |
| 7487 | }; |
| 7488 | |
| 7489 | static const uint32_t ZPRSubClassMask[] = { |
| 7490 | 0x00000000, 0x00000000, 0x00000000, 0x000001a0, 0x00000000, 0x00000000, |
| 7491 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub0 |
| 7492 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub1 |
| 7493 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub2 |
| 7494 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub3 |
| 7495 | }; |
| 7496 | |
| 7497 | static const uint32_t FPR128_loSubClassMask[] = { |
| 7498 | 0x00000000, 0x00000000, 0x00000000, 0x00000040, 0x00000000, 0x00000000, |
| 7499 | 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x10044102, 0x00004410, // qsub0 |
| 7500 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x2004c202, 0x00004c30, // qsub1 |
| 7501 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // qsub2 |
| 7502 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub3 |
| 7503 | 0x00000000, 0x00000000, 0x00000000, 0x80000180, 0x0299082c, 0x02919081, // zsub |
| 7504 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // zsub1_then_zsub |
| 7505 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub3_then_zsub |
| 7506 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub2_then_zsub |
| 7507 | }; |
| 7508 | |
| 7509 | static const uint32_t ZPR_4bSubClassMask[] = { |
| 7510 | 0x00000000, 0x00000000, 0x00000000, 0x00000180, 0x00000000, 0x00000000, |
| 7511 | 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0299082c, 0x02919081, // zsub0 |
| 7512 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // zsub1 |
| 7513 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub2 |
| 7514 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub3 |
| 7515 | }; |
| 7516 | |
| 7517 | static const uint32_t ZPR_3bSubClassMask[] = { |
| 7518 | 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, |
| 7519 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02900028, 0x02910000, // zsub0 |
| 7520 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00030, 0x03b20000, // zsub1 |
| 7521 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03400000, 0x03e40000, // zsub2 |
| 7522 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03480000, // zsub3 |
| 7523 | }; |
| 7524 | |
| 7525 | static const uint32_t DDDSubClassMask[] = { |
| 7526 | 0x00000000, 0x00000000, 0x00000000, 0x0000fe00, 0x00000000, 0x00000000, |
| 7527 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7528 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7529 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7530 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7531 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7532 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7533 | }; |
| 7534 | |
| 7535 | static const uint32_t DDD_with_dsub0_in_FPR64_loSubClassMask[] = { |
| 7536 | 0x00000000, 0x00000000, 0x00000000, 0x0000a400, 0x00000000, 0x00000000, |
| 7537 | 0x00000000, 0x00000000, 0x00000000, 0x05220000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7538 | 0x00000000, 0x00000000, 0x00000000, 0x07640000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7539 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10044100, 0x00004410, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7540 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00004c30, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7541 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990800, 0x02919081, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7542 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7543 | }; |
| 7544 | |
| 7545 | static const uint32_t DDD_with_dsub1_in_FPR64_loSubClassMask[] = { |
| 7546 | 0x00000000, 0x00000000, 0x00000000, 0x0000e800, 0x00000000, 0x00000000, |
| 7547 | 0x00000000, 0x00000000, 0x00000000, 0x07640000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7548 | 0x00000000, 0x00000000, 0x00000000, 0x07c80000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7549 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2004c200, 0x00004c30, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7550 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7551 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x03b3b182, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7552 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7553 | }; |
| 7554 | |
| 7555 | static const uint32_t DDD_with_dsub2_in_FPR64_loSubClassMask[] = { |
| 7556 | 0x00000000, 0x00000000, 0x00000000, 0x0000d000, 0x00000000, 0x00000000, |
| 7557 | 0x00000000, 0x00000000, 0x00000000, 0x07c80000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7558 | 0x00000000, 0x00000000, 0x00000000, 0x06900000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7559 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7560 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7561 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7562 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7563 | }; |
| 7564 | |
| 7565 | static const uint32_t DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loSubClassMask[] = { |
| 7566 | 0x00000000, 0x00000000, 0x00000000, 0x0000a000, 0x00000000, 0x00000000, |
| 7567 | 0x00000000, 0x00000000, 0x00000000, 0x05200000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7568 | 0x00000000, 0x00000000, 0x00000000, 0x07400000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7569 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00044000, 0x00004410, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7570 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004c20, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7571 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990000, 0x02919080, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7572 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7573 | }; |
| 7574 | |
| 7575 | static const uint32_t DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSubClassMask[] = { |
| 7576 | 0x00000000, 0x00000000, 0x00000000, 0x0000c000, 0x00000000, 0x00000000, |
| 7577 | 0x00000000, 0x00000000, 0x00000000, 0x07400000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7578 | 0x00000000, 0x00000000, 0x00000000, 0x06800000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7579 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00048000, 0x00004c20, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7580 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004840, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7581 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ba0000, 0x03b3b100, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7582 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7583 | }; |
| 7584 | |
| 7585 | static const uint32_t DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSubClassMask[] = { |
| 7586 | 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000, 0x00000000, |
| 7587 | 0x00000000, 0x00000000, 0x00000000, 0x05000000, 0x00000000, 0x00000000, // dsub0_dsub1_dsub2 |
| 7588 | 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x00000000, 0x00000000, // dsub1_dsub2_dsub3 |
| 7589 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00004400, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 7590 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004800, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7591 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02980000, 0x02919000, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 7592 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3a000, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7593 | }; |
| 7594 | |
| 7595 | static const uint32_t DDDDSubClassMask[] = { |
| 7596 | 0x00000000, 0x00000000, 0x00000000, 0x07ff0000, 0x00000000, 0x00000000, |
| 7597 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7598 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7599 | }; |
| 7600 | |
| 7601 | static const uint32_t DDDD_with_dsub0_in_FPR64_loSubClassMask[] = { |
| 7602 | 0x00000000, 0x00000000, 0x00000000, 0x05220000, 0x00000000, 0x00000000, |
| 7603 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00004410, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7604 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919081, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7605 | }; |
| 7606 | |
| 7607 | static const uint32_t DDDD_with_dsub1_in_FPR64_loSubClassMask[] = { |
| 7608 | 0x00000000, 0x00000000, 0x00000000, 0x07640000, 0x00000000, 0x00000000, |
| 7609 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00004c30, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7610 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7611 | }; |
| 7612 | |
| 7613 | static const uint32_t DDDD_with_dsub2_in_FPR64_loSubClassMask[] = { |
| 7614 | 0x00000000, 0x00000000, 0x00000000, 0x07c80000, 0x00000000, 0x00000000, |
| 7615 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7616 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7617 | }; |
| 7618 | |
| 7619 | static const uint32_t DDDD_with_dsub3_in_FPR64_loSubClassMask[] = { |
| 7620 | 0x00000000, 0x00000000, 0x00000000, 0x06900000, 0x00000000, 0x00000000, |
| 7621 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7622 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7623 | }; |
| 7624 | |
| 7625 | static const uint32_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loSubClassMask[] = { |
| 7626 | 0x00000000, 0x00000000, 0x00000000, 0x05200000, 0x00000000, 0x00000000, |
| 7627 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004410, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7628 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919080, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7629 | }; |
| 7630 | |
| 7631 | static const uint32_t DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSubClassMask[] = { |
| 7632 | 0x00000000, 0x00000000, 0x00000000, 0x07400000, 0x00000000, 0x00000000, |
| 7633 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004c20, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7634 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7635 | }; |
| 7636 | |
| 7637 | static const uint32_t DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSubClassMask[] = { |
| 7638 | 0x00000000, 0x00000000, 0x00000000, 0x06800000, 0x00000000, 0x00000000, |
| 7639 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004840, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7640 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7641 | }; |
| 7642 | |
| 7643 | static const uint32_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSubClassMask[] = { |
| 7644 | 0x00000000, 0x00000000, 0x00000000, 0x05000000, 0x00000000, 0x00000000, |
| 7645 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004400, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7646 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919000, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7647 | }; |
| 7648 | |
| 7649 | static const uint32_t DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSubClassMask[] = { |
| 7650 | 0x00000000, 0x00000000, 0x00000000, 0x06000000, 0x00000000, 0x00000000, |
| 7651 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004800, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7652 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3a000, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7653 | }; |
| 7654 | |
| 7655 | static const uint32_t DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSubClassMask[] = { |
| 7656 | 0x00000000, 0x00000000, 0x00000000, 0x04000000, 0x00000000, 0x00000000, |
| 7657 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004000, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 7658 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02918000, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 7659 | }; |
| 7660 | |
| 7661 | static const uint32_t QQSubClassMask[] = { |
| 7662 | 0x00000000, 0x00000000, 0x00000000, 0x68000000, 0x00000002, 0x00000000, |
| 7663 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub0_qsub1 |
| 7664 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf404c740, 0x00004c70, // qsub1_qsub2 |
| 7665 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub2_qsub3 |
| 7666 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0bfb38bd, 0x03ffb38f, // zsub_zsub1_then_zsub |
| 7667 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub1_then_zsub_zsub2_then_zsub |
| 7668 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub2_then_zsub_zsub3_then_zsub |
| 7669 | }; |
| 7670 | |
| 7671 | static const uint32_t ZPR2SubClassMask[] = { |
| 7672 | 0x00000000, 0x00000000, 0x00000000, 0x90000000, 0x0000003d, 0x00000000, |
| 7673 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub0_zsub1 |
| 7674 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub1_zsub2 |
| 7675 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub2_zsub3 |
| 7676 | }; |
| 7677 | |
| 7678 | static const uint32_t QQ_with_dsub_in_FPR64_loSubClassMask[] = { |
| 7679 | 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000002, 0x00000000, |
| 7680 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10044100, 0x00004410, // qsub0_qsub1 |
| 7681 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2004c200, 0x00004c30, // qsub1_qsub2 |
| 7682 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, // qsub2_qsub3 |
| 7683 | 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0299082c, 0x02919081, // zsub_zsub1_then_zsub |
| 7684 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x03b3b182, // zsub1_then_zsub_zsub2_then_zsub |
| 7685 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub2_then_zsub_zsub3_then_zsub |
| 7686 | }; |
| 7687 | |
| 7688 | static const uint32_t QQ_with_qsub1_in_FPR128_loSubClassMask[] = { |
| 7689 | 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00000002, 0x00000000, |
| 7690 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2004c200, 0x00004c30, // qsub0_qsub1 |
| 7691 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40048400, 0x00004c60, // qsub1_qsub2 |
| 7692 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub2_qsub3 |
| 7693 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb103d, 0x03b3b182, // zsub_zsub1_then_zsub |
| 7694 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub1_then_zsub_zsub2_then_zsub |
| 7695 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub2_then_zsub_zsub3_then_zsub |
| 7696 | }; |
| 7697 | |
| 7698 | static const uint32_t ZPR2_with_dsub_in_FPR64_loSubClassMask[] = { |
| 7699 | 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x0000002c, 0x00000000, |
| 7700 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990800, 0x02919081, // zsub0_zsub1 |
| 7701 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x03b3b182, // zsub1_zsub2 |
| 7702 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub2_zsub3 |
| 7703 | }; |
| 7704 | |
| 7705 | static const uint32_t ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = { |
| 7706 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000003d, 0x00000000, |
| 7707 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x03b3b182, // zsub0_zsub1 |
| 7708 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub1_zsub2 |
| 7709 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub2_zsub3 |
| 7710 | }; |
| 7711 | |
| 7712 | static const uint32_t QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask[] = { |
| 7713 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002, 0x00000000, |
| 7714 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00044000, 0x00004410, // qsub0_qsub1 |
| 7715 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00048000, 0x00004c20, // qsub1_qsub2 |
| 7716 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004840, // qsub2_qsub3 |
| 7717 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0299002c, 0x02919080, // zsub_zsub1_then_zsub |
| 7718 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ba0000, 0x03b3b100, // zsub1_then_zsub_zsub2_then_zsub |
| 7719 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub2_then_zsub_zsub3_then_zsub |
| 7720 | }; |
| 7721 | |
| 7722 | static const uint32_t ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask[] = { |
| 7723 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000002c, 0x00000000, |
| 7724 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990000, 0x02919080, // zsub0_zsub1 |
| 7725 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ba0000, 0x03b3b100, // zsub1_zsub2 |
| 7726 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub2_zsub3 |
| 7727 | }; |
| 7728 | |
| 7729 | static const uint32_t ZPR2_with_zsub0_in_ZPR_3bSubClassMask[] = { |
| 7730 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000028, 0x00000000, |
| 7731 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02900000, 0x02910000, // zsub0_zsub1 |
| 7732 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00000, 0x03b20000, // zsub1_zsub2 |
| 7733 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03e40000, // zsub2_zsub3 |
| 7734 | }; |
| 7735 | |
| 7736 | static const uint32_t ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = { |
| 7737 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000030, 0x00000000, |
| 7738 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00000, 0x03b20000, // zsub0_zsub1 |
| 7739 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03400000, 0x03e40000, // zsub1_zsub2 |
| 7740 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03480000, // zsub2_zsub3 |
| 7741 | }; |
| 7742 | |
| 7743 | static const uint32_t ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask[] = { |
| 7744 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, 0x00000000, |
| 7745 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02800000, 0x02900000, // zsub0_zsub1 |
| 7746 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03000000, 0x03a00000, // zsub1_zsub2 |
| 7747 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03400000, // zsub2_zsub3 |
| 7748 | }; |
| 7749 | |
| 7750 | static const uint32_t QQQSubClassMask[] = { |
| 7751 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0004c740, 0x00000000, |
| 7752 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub0_qsub1_qsub2 |
| 7753 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, // qsub1_qsub2_qsub3 |
| 7754 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0bfb3880, 0x03ffb38f, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7755 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7756 | }; |
| 7757 | |
| 7758 | static const uint32_t ZPR3SubClassMask[] = { |
| 7759 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fb3880, 0x00000000, |
| 7760 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub0_zsub1_zsub2 |
| 7761 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub1_zsub2_zsub3 |
| 7762 | }; |
| 7763 | |
| 7764 | static const uint32_t QQQ_with_dsub_in_FPR64_loSubClassMask[] = { |
| 7765 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00044100, 0x00000000, |
| 7766 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00004410, // qsub0_qsub1_qsub2 |
| 7767 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00004c30, // qsub1_qsub2_qsub3 |
| 7768 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990800, 0x02919081, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7769 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7770 | }; |
| 7771 | |
| 7772 | static const uint32_t QQQ_with_qsub1_in_FPR128_loSubClassMask[] = { |
| 7773 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0004c200, 0x00000000, |
| 7774 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00004c30, // qsub0_qsub1_qsub2 |
| 7775 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, // qsub1_qsub2_qsub3 |
| 7776 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x03b3b182, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7777 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7778 | }; |
| 7779 | |
| 7780 | static const uint32_t QQQ_with_qsub2_in_FPR128_loSubClassMask[] = { |
| 7781 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00048400, 0x00000000, |
| 7782 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, // qsub0_qsub1_qsub2 |
| 7783 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, // qsub1_qsub2_qsub3 |
| 7784 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x03f7b304, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7785 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7786 | }; |
| 7787 | |
| 7788 | static const uint32_t ZPR3_with_dsub_in_FPR64_loSubClassMask[] = { |
| 7789 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990800, 0x00000000, |
| 7790 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919081, // zsub0_zsub1_zsub2 |
| 7791 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, // zsub1_zsub2_zsub3 |
| 7792 | }; |
| 7793 | |
| 7794 | static const uint32_t ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = { |
| 7795 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03bb1000, 0x00000000, |
| 7796 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, // zsub0_zsub1_zsub2 |
| 7797 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub1_zsub2_zsub3 |
| 7798 | }; |
| 7799 | |
| 7800 | static const uint32_t ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = { |
| 7801 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03fa2000, 0x00000000, |
| 7802 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub0_zsub1_zsub2 |
| 7803 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub1_zsub2_zsub3 |
| 7804 | }; |
| 7805 | |
| 7806 | static const uint32_t QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask[] = { |
| 7807 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00044000, 0x00000000, |
| 7808 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004410, // qsub0_qsub1_qsub2 |
| 7809 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004c20, // qsub1_qsub2_qsub3 |
| 7810 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990000, 0x02919080, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7811 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7812 | }; |
| 7813 | |
| 7814 | static const uint32_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = { |
| 7815 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00048000, 0x00000000, |
| 7816 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004c20, // qsub0_qsub1_qsub2 |
| 7817 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004840, // qsub1_qsub2_qsub3 |
| 7818 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ba0000, 0x03b3b100, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7819 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7820 | }; |
| 7821 | |
| 7822 | static const uint32_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask[] = { |
| 7823 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02990000, 0x00000000, |
| 7824 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919080, // zsub0_zsub1_zsub2 |
| 7825 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, // zsub1_zsub2_zsub3 |
| 7826 | }; |
| 7827 | |
| 7828 | static const uint32_t ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = { |
| 7829 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ba0000, 0x00000000, |
| 7830 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, // zsub0_zsub1_zsub2 |
| 7831 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub1_zsub2_zsub3 |
| 7832 | }; |
| 7833 | |
| 7834 | static const uint32_t QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask[] = { |
| 7835 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000, |
| 7836 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004400, // qsub0_qsub1_qsub2 |
| 7837 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004800, // qsub1_qsub2_qsub3 |
| 7838 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02980000, 0x02919000, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 7839 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3a000, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7840 | }; |
| 7841 | |
| 7842 | static const uint32_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask[] = { |
| 7843 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02980000, 0x00000000, |
| 7844 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919000, // zsub0_zsub1_zsub2 |
| 7845 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3a000, // zsub1_zsub2_zsub3 |
| 7846 | }; |
| 7847 | |
| 7848 | static const uint32_t ZPR3_with_zsub0_in_ZPR_3bSubClassMask[] = { |
| 7849 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02900000, 0x00000000, |
| 7850 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02910000, // zsub0_zsub1_zsub2 |
| 7851 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b20000, // zsub1_zsub2_zsub3 |
| 7852 | }; |
| 7853 | |
| 7854 | static const uint32_t ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = { |
| 7855 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00000, 0x00000000, |
| 7856 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b20000, // zsub0_zsub1_zsub2 |
| 7857 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03e40000, // zsub1_zsub2_zsub3 |
| 7858 | }; |
| 7859 | |
| 7860 | static const uint32_t ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = { |
| 7861 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03400000, 0x00000000, |
| 7862 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03e40000, // zsub0_zsub1_zsub2 |
| 7863 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03480000, // zsub1_zsub2_zsub3 |
| 7864 | }; |
| 7865 | |
| 7866 | static const uint32_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask[] = { |
| 7867 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02800000, 0x00000000, |
| 7868 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02900000, // zsub0_zsub1_zsub2 |
| 7869 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00000, // zsub1_zsub2_zsub3 |
| 7870 | }; |
| 7871 | |
| 7872 | static const uint32_t ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = { |
| 7873 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03000000, 0x00000000, |
| 7874 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00000, // zsub0_zsub1_zsub2 |
| 7875 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03400000, // zsub1_zsub2_zsub3 |
| 7876 | }; |
| 7877 | |
| 7878 | static const uint32_t ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask[] = { |
| 7879 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, 0x00000000, |
| 7880 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02800000, // zsub0_zsub1_zsub2 |
| 7881 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03000000, // zsub1_zsub2_zsub3 |
| 7882 | }; |
| 7883 | |
| 7884 | static const uint32_t QQQQSubClassMask[] = { |
| 7885 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf4000000, 0x00004c70, |
| 7886 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7887 | }; |
| 7888 | |
| 7889 | static const uint32_t ZPR4SubClassMask[] = { |
| 7890 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x03ffb38f, |
| 7891 | }; |
| 7892 | |
| 7893 | static const uint32_t QQQQ_with_dsub_in_FPR64_loSubClassMask[] = { |
| 7894 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000000, 0x00004410, |
| 7895 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919081, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7896 | }; |
| 7897 | |
| 7898 | static const uint32_t QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = { |
| 7899 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00004c30, |
| 7900 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7901 | }; |
| 7902 | |
| 7903 | static const uint32_t QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = { |
| 7904 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00004c60, |
| 7905 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7906 | }; |
| 7907 | |
| 7908 | static const uint32_t QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = { |
| 7909 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x00004840, |
| 7910 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7911 | }; |
| 7912 | |
| 7913 | static const uint32_t ZPR4_with_dsub_in_FPR64_loSubClassMask[] = { |
| 7914 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919081, |
| 7915 | }; |
| 7916 | |
| 7917 | static const uint32_t ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = { |
| 7918 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b182, |
| 7919 | }; |
| 7920 | |
| 7921 | static const uint32_t ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = { |
| 7922 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7b304, |
| 7923 | }; |
| 7924 | |
| 7925 | static const uint32_t ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = { |
| 7926 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03ffa208, |
| 7927 | }; |
| 7928 | |
| 7929 | static const uint32_t QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask[] = { |
| 7930 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004410, |
| 7931 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919080, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7932 | }; |
| 7933 | |
| 7934 | static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = { |
| 7935 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004c20, |
| 7936 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7937 | }; |
| 7938 | |
| 7939 | static const uint32_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = { |
| 7940 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004840, |
| 7941 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7942 | }; |
| 7943 | |
| 7944 | static const uint32_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask[] = { |
| 7945 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919080, |
| 7946 | }; |
| 7947 | |
| 7948 | static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = { |
| 7949 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3b100, |
| 7950 | }; |
| 7951 | |
| 7952 | static const uint32_t ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = { |
| 7953 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03f7a200, |
| 7954 | }; |
| 7955 | |
| 7956 | static const uint32_t QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask[] = { |
| 7957 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004400, |
| 7958 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919000, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7959 | }; |
| 7960 | |
| 7961 | static const uint32_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = { |
| 7962 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004800, |
| 7963 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3a000, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7964 | }; |
| 7965 | |
| 7966 | static const uint32_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask[] = { |
| 7967 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02919000, |
| 7968 | }; |
| 7969 | |
| 7970 | static const uint32_t ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = { |
| 7971 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b3a000, |
| 7972 | }; |
| 7973 | |
| 7974 | static const uint32_t QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask[] = { |
| 7975 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00004000, |
| 7976 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02918000, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 7977 | }; |
| 7978 | |
| 7979 | static const uint32_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask[] = { |
| 7980 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02918000, |
| 7981 | }; |
| 7982 | |
| 7983 | static const uint32_t ZPR4_with_zsub0_in_ZPR_3bSubClassMask[] = { |
| 7984 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02910000, |
| 7985 | }; |
| 7986 | |
| 7987 | static const uint32_t ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = { |
| 7988 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03b20000, |
| 7989 | }; |
| 7990 | |
| 7991 | static const uint32_t ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = { |
| 7992 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03e40000, |
| 7993 | }; |
| 7994 | |
| 7995 | static const uint32_t ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = { |
| 7996 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03480000, |
| 7997 | }; |
| 7998 | |
| 7999 | static const uint32_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask[] = { |
| 8000 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02900000, |
| 8001 | }; |
| 8002 | |
| 8003 | static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = { |
| 8004 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03a00000, |
| 8005 | }; |
| 8006 | |
| 8007 | static const uint32_t ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = { |
| 8008 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03400000, |
| 8009 | }; |
| 8010 | |
| 8011 | static const uint32_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask[] = { |
| 8012 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02800000, |
| 8013 | }; |
| 8014 | |
| 8015 | static const uint32_t ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = { |
| 8016 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x03000000, |
| 8017 | }; |
| 8018 | |
| 8019 | static const uint32_t ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask[] = { |
| 8020 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x02000000, |
| 8021 | }; |
| 8022 | |
| 8023 | static const uint16_t SuperRegIdxSeqs[] = { |
| 8024 | /* 0 */ 15, 0, |
| 8025 | /* 2 */ 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 0, |
| 8026 | /* 13 */ 29, 30, 31, 32, 0, |
| 8027 | /* 18 */ 15, 16, 18, 55, 56, 57, 58, 59, 60, 61, 62, 0, |
| 8028 | /* 30 */ 1, 34, 37, 40, 43, 47, 51, 63, 69, 75, 0, |
| 8029 | /* 41 */ 2, 3, 4, 5, 6, 44, 48, 52, 64, 70, 76, 0, |
| 8030 | /* 53 */ 7, 35, 38, 41, 45, 49, 53, 65, 71, 77, 0, |
| 8031 | /* 64 */ 14, 36, 39, 42, 46, 50, 54, 66, 72, 78, 0, |
| 8032 | /* 75 */ 10, 11, 12, 13, 28, 67, 73, 79, 0, |
| 8033 | /* 84 */ 98, 99, 100, 101, 0, |
| 8034 | /* 89 */ 97, 102, 103, 104, 105, 0, |
| 8035 | /* 95 */ 87, 108, 0, |
| 8036 | /* 98 */ 110, 0, |
| 8037 | /* 100 */ 113, 115, 0, |
| 8038 | /* 103 */ 112, 114, 116, 0, |
| 8039 | /* 107 */ 82, 84, 88, 95, 109, 118, 0, |
| 8040 | /* 114 */ 90, 92, 111, 120, 0, |
| 8041 | /* 119 */ 81, 83, 85, 86, 94, 96, 106, 117, 121, 0, |
| 8042 | /* 129 */ 89, 91, 93, 107, 119, 122, 0, |
| 8043 | }; |
| 8044 | |
| 8045 | static const TargetRegisterClass *const FPR16_loSuperclasses[] = { |
| 8046 | &AArch64::FPR16RegClass, |
| 8047 | nullptr |
| 8048 | }; |
| 8049 | |
| 8050 | static const TargetRegisterClass *const PPR_3bSuperclasses[] = { |
| 8051 | &AArch64::PPRRegClass, |
| 8052 | nullptr |
| 8053 | }; |
| 8054 | |
| 8055 | static const TargetRegisterClass *const GPR32Superclasses[] = { |
| 8056 | &AArch64::GPR32allRegClass, |
| 8057 | nullptr |
| 8058 | }; |
| 8059 | |
| 8060 | static const TargetRegisterClass *const GPR32spSuperclasses[] = { |
| 8061 | &AArch64::GPR32allRegClass, |
| 8062 | nullptr |
| 8063 | }; |
| 8064 | |
| 8065 | static const TargetRegisterClass *const GPR32commonSuperclasses[] = { |
| 8066 | &AArch64::GPR32allRegClass, |
| 8067 | &AArch64::GPR32RegClass, |
| 8068 | &AArch64::GPR32spRegClass, |
| 8069 | nullptr |
| 8070 | }; |
| 8071 | |
| 8072 | static const TargetRegisterClass *const FPR32_with_hsub_in_FPR16_loSuperclasses[] = { |
| 8073 | &AArch64::FPR32RegClass, |
| 8074 | nullptr |
| 8075 | }; |
| 8076 | |
| 8077 | static const TargetRegisterClass *const GPR32argSuperclasses[] = { |
| 8078 | &AArch64::GPR32allRegClass, |
| 8079 | &AArch64::GPR32RegClass, |
| 8080 | &AArch64::GPR32spRegClass, |
| 8081 | &AArch64::GPR32commonRegClass, |
| 8082 | nullptr |
| 8083 | }; |
| 8084 | |
| 8085 | static const TargetRegisterClass *const GPR32sponlySuperclasses[] = { |
| 8086 | &AArch64::GPR32allRegClass, |
| 8087 | &AArch64::GPR32spRegClass, |
| 8088 | nullptr |
| 8089 | }; |
| 8090 | |
| 8091 | static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = { |
| 8092 | &AArch64::WSeqPairsClassRegClass, |
| 8093 | nullptr |
| 8094 | }; |
| 8095 | |
| 8096 | static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32argSuperclasses[] = { |
| 8097 | &AArch64::WSeqPairsClassRegClass, |
| 8098 | &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass, |
| 8099 | nullptr |
| 8100 | }; |
| 8101 | |
| 8102 | static const TargetRegisterClass *const GPR64Superclasses[] = { |
| 8103 | &AArch64::GPR64allRegClass, |
| 8104 | nullptr |
| 8105 | }; |
| 8106 | |
| 8107 | static const TargetRegisterClass *const GPR64spSuperclasses[] = { |
| 8108 | &AArch64::GPR64allRegClass, |
| 8109 | nullptr |
| 8110 | }; |
| 8111 | |
| 8112 | static const TargetRegisterClass *const GPR64commonSuperclasses[] = { |
| 8113 | &AArch64::GPR64allRegClass, |
| 8114 | &AArch64::GPR64RegClass, |
| 8115 | &AArch64::GPR64spRegClass, |
| 8116 | nullptr |
| 8117 | }; |
| 8118 | |
| 8119 | static const TargetRegisterClass *const GPR64noipSuperclasses[] = { |
| 8120 | &AArch64::GPR64allRegClass, |
| 8121 | &AArch64::GPR64RegClass, |
| 8122 | nullptr |
| 8123 | }; |
| 8124 | |
| 8125 | static const TargetRegisterClass *const GPR64common_and_GPR64noipSuperclasses[] = { |
| 8126 | &AArch64::GPR64allRegClass, |
| 8127 | &AArch64::GPR64RegClass, |
| 8128 | &AArch64::GPR64spRegClass, |
| 8129 | &AArch64::GPR64commonRegClass, |
| 8130 | &AArch64::GPR64noipRegClass, |
| 8131 | nullptr |
| 8132 | }; |
| 8133 | |
| 8134 | static const TargetRegisterClass *const tcGPR64Superclasses[] = { |
| 8135 | &AArch64::GPR64allRegClass, |
| 8136 | &AArch64::GPR64RegClass, |
| 8137 | &AArch64::GPR64spRegClass, |
| 8138 | &AArch64::GPR64commonRegClass, |
| 8139 | nullptr |
| 8140 | }; |
| 8141 | |
| 8142 | static const TargetRegisterClass *const GPR64noip_and_tcGPR64Superclasses[] = { |
| 8143 | &AArch64::GPR64allRegClass, |
| 8144 | &AArch64::GPR64RegClass, |
| 8145 | &AArch64::GPR64spRegClass, |
| 8146 | &AArch64::GPR64commonRegClass, |
| 8147 | &AArch64::GPR64noipRegClass, |
| 8148 | &AArch64::GPR64common_and_GPR64noipRegClass, |
| 8149 | &AArch64::tcGPR64RegClass, |
| 8150 | nullptr |
| 8151 | }; |
| 8152 | |
| 8153 | static const TargetRegisterClass *const FPR64_loSuperclasses[] = { |
| 8154 | &AArch64::FPR64RegClass, |
| 8155 | nullptr |
| 8156 | }; |
| 8157 | |
| 8158 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_GPR64noipSuperclasses[] = { |
| 8159 | &AArch64::GPR64x8ClassRegClass, |
| 8160 | nullptr |
| 8161 | }; |
| 8162 | |
| 8163 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses[] = { |
| 8164 | &AArch64::GPR64x8ClassRegClass, |
| 8165 | nullptr |
| 8166 | }; |
| 8167 | |
| 8168 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8169 | &AArch64::GPR64x8ClassRegClass, |
| 8170 | nullptr |
| 8171 | }; |
| 8172 | |
| 8173 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8174 | &AArch64::GPR64x8ClassRegClass, |
| 8175 | nullptr |
| 8176 | }; |
| 8177 | |
| 8178 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses[] = { |
| 8179 | &AArch64::GPR64x8ClassRegClass, |
| 8180 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8181 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8182 | nullptr |
| 8183 | }; |
| 8184 | |
| 8185 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8186 | &AArch64::GPR64x8ClassRegClass, |
| 8187 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8188 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8189 | nullptr |
| 8190 | }; |
| 8191 | |
| 8192 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8193 | &AArch64::GPR64x8ClassRegClass, |
| 8194 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8195 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8196 | nullptr |
| 8197 | }; |
| 8198 | |
| 8199 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64Superclasses[] = { |
| 8200 | &AArch64::GPR64x8ClassRegClass, |
| 8201 | nullptr |
| 8202 | }; |
| 8203 | |
| 8204 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8205 | &AArch64::GPR64x8ClassRegClass, |
| 8206 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8207 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8208 | nullptr |
| 8209 | }; |
| 8210 | |
| 8211 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8212 | &AArch64::GPR64x8ClassRegClass, |
| 8213 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8214 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8215 | nullptr |
| 8216 | }; |
| 8217 | |
| 8218 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8219 | &AArch64::GPR64x8ClassRegClass, |
| 8220 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8221 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8222 | nullptr |
| 8223 | }; |
| 8224 | |
| 8225 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8226 | &AArch64::GPR64x8ClassRegClass, |
| 8227 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8228 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8229 | nullptr |
| 8230 | }; |
| 8231 | |
| 8232 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses[] = { |
| 8233 | &AArch64::GPR64x8ClassRegClass, |
| 8234 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8235 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8236 | nullptr |
| 8237 | }; |
| 8238 | |
| 8239 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8240 | &AArch64::GPR64x8ClassRegClass, |
| 8241 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8242 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8243 | nullptr |
| 8244 | }; |
| 8245 | |
| 8246 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8247 | &AArch64::GPR64x8ClassRegClass, |
| 8248 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8249 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8250 | nullptr |
| 8251 | }; |
| 8252 | |
| 8253 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_1_in_tcGPR64Superclasses[] = { |
| 8254 | &AArch64::GPR64x8ClassRegClass, |
| 8255 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8256 | nullptr |
| 8257 | }; |
| 8258 | |
| 8259 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8260 | &AArch64::GPR64x8ClassRegClass, |
| 8261 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8262 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8263 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8264 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8265 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8266 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8267 | nullptr |
| 8268 | }; |
| 8269 | |
| 8270 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8271 | &AArch64::GPR64x8ClassRegClass, |
| 8272 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8273 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8274 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8275 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8276 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8277 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8278 | nullptr |
| 8279 | }; |
| 8280 | |
| 8281 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8282 | &AArch64::GPR64x8ClassRegClass, |
| 8283 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8284 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8285 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8286 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8287 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8288 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8289 | nullptr |
| 8290 | }; |
| 8291 | |
| 8292 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8293 | &AArch64::GPR64x8ClassRegClass, |
| 8294 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8295 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8296 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8297 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8298 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8299 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8300 | nullptr |
| 8301 | }; |
| 8302 | |
| 8303 | static const TargetRegisterClass *const GPR64argSuperclasses[] = { |
| 8304 | &AArch64::GPR64allRegClass, |
| 8305 | &AArch64::GPR64RegClass, |
| 8306 | &AArch64::GPR64spRegClass, |
| 8307 | &AArch64::GPR64commonRegClass, |
| 8308 | &AArch64::GPR64noipRegClass, |
| 8309 | &AArch64::GPR64common_and_GPR64noipRegClass, |
| 8310 | &AArch64::tcGPR64RegClass, |
| 8311 | &AArch64::GPR64noip_and_tcGPR64RegClass, |
| 8312 | nullptr |
| 8313 | }; |
| 8314 | |
| 8315 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses[] = { |
| 8316 | &AArch64::GPR64x8ClassRegClass, |
| 8317 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8318 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8319 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8320 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8321 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8322 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8323 | nullptr |
| 8324 | }; |
| 8325 | |
| 8326 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8327 | &AArch64::GPR64x8ClassRegClass, |
| 8328 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8329 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8330 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8331 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8332 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8333 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8334 | nullptr |
| 8335 | }; |
| 8336 | |
| 8337 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8338 | &AArch64::GPR64x8ClassRegClass, |
| 8339 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8340 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8341 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8342 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8343 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8344 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8345 | nullptr |
| 8346 | }; |
| 8347 | |
| 8348 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8349 | &AArch64::GPR64x8ClassRegClass, |
| 8350 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8351 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8352 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8353 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8354 | nullptr |
| 8355 | }; |
| 8356 | |
| 8357 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8358 | &AArch64::GPR64x8ClassRegClass, |
| 8359 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8360 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8361 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8362 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8363 | nullptr |
| 8364 | }; |
| 8365 | |
| 8366 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8367 | &AArch64::GPR64x8ClassRegClass, |
| 8368 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8369 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8370 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8371 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8372 | nullptr |
| 8373 | }; |
| 8374 | |
| 8375 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8376 | &AArch64::GPR64x8ClassRegClass, |
| 8377 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8378 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8379 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8380 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8381 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8382 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8383 | nullptr |
| 8384 | }; |
| 8385 | |
| 8386 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8387 | &AArch64::GPR64x8ClassRegClass, |
| 8388 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8389 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8390 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8391 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8392 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8393 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8394 | nullptr |
| 8395 | }; |
| 8396 | |
| 8397 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8398 | &AArch64::GPR64x8ClassRegClass, |
| 8399 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8400 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8401 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8402 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8403 | nullptr |
| 8404 | }; |
| 8405 | |
| 8406 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8407 | &AArch64::GPR64x8ClassRegClass, |
| 8408 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8409 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8410 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8411 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8412 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8413 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8414 | nullptr |
| 8415 | }; |
| 8416 | |
| 8417 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8418 | &AArch64::GPR64x8ClassRegClass, |
| 8419 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8420 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8421 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8422 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8423 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8424 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8425 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8426 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8427 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8428 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8429 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8430 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8431 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8432 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8433 | nullptr |
| 8434 | }; |
| 8435 | |
| 8436 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8437 | &AArch64::GPR64x8ClassRegClass, |
| 8438 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8439 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8440 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8441 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8442 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8443 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8444 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8445 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8446 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8447 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8448 | nullptr |
| 8449 | }; |
| 8450 | |
| 8451 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8452 | &AArch64::GPR64x8ClassRegClass, |
| 8453 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8454 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8455 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8456 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8457 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8458 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8459 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8460 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8461 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8462 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8463 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8464 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8465 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8466 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8467 | nullptr |
| 8468 | }; |
| 8469 | |
| 8470 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8471 | &AArch64::GPR64x8ClassRegClass, |
| 8472 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8473 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8474 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8475 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8476 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8477 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8478 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8479 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8480 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8481 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8482 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8483 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8484 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8485 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8486 | nullptr |
| 8487 | }; |
| 8488 | |
| 8489 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses[] = { |
| 8490 | &AArch64::GPR64x8ClassRegClass, |
| 8491 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8492 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8493 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8494 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8495 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8496 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8497 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8498 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8499 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8500 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8501 | nullptr |
| 8502 | }; |
| 8503 | |
| 8504 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8505 | &AArch64::GPR64x8ClassRegClass, |
| 8506 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8507 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8508 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8509 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8510 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8511 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8512 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8513 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8514 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8515 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8516 | nullptr |
| 8517 | }; |
| 8518 | |
| 8519 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8520 | &AArch64::GPR64x8ClassRegClass, |
| 8521 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8522 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8523 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8524 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8525 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8526 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8527 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8528 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8529 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8530 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8531 | nullptr |
| 8532 | }; |
| 8533 | |
| 8534 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8535 | &AArch64::GPR64x8ClassRegClass, |
| 8536 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8537 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8538 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8539 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8540 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8541 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8542 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8543 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8544 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8545 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8546 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8547 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8548 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8549 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8550 | nullptr |
| 8551 | }; |
| 8552 | |
| 8553 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8554 | &AArch64::GPR64x8ClassRegClass, |
| 8555 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8556 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8557 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8558 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8559 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8560 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8561 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8562 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8563 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8564 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8565 | nullptr |
| 8566 | }; |
| 8567 | |
| 8568 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8569 | &AArch64::GPR64x8ClassRegClass, |
| 8570 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8571 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8572 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8573 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8574 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8575 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8576 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8577 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8578 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8579 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8580 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8581 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8582 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8583 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8584 | nullptr |
| 8585 | }; |
| 8586 | |
| 8587 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8588 | &AArch64::GPR64x8ClassRegClass, |
| 8589 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8590 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8591 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8592 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8593 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8594 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8595 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8596 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8597 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8598 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8599 | nullptr |
| 8600 | }; |
| 8601 | |
| 8602 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8603 | &AArch64::GPR64x8ClassRegClass, |
| 8604 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8605 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8606 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8607 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8608 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8609 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8610 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8611 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8612 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8613 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8614 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8615 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8616 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8617 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8618 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8619 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8620 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8621 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8622 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8623 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8624 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8625 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 8626 | nullptr |
| 8627 | }; |
| 8628 | |
| 8629 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8630 | &AArch64::GPR64x8ClassRegClass, |
| 8631 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8632 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8633 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8634 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8635 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8636 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8637 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8638 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8639 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8640 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8641 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8642 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8643 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8644 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8645 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8646 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8647 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8648 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8649 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8650 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8651 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8652 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8653 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8654 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8655 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8656 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8657 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8658 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8659 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8660 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8661 | nullptr |
| 8662 | }; |
| 8663 | |
| 8664 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses[] = { |
| 8665 | &AArch64::GPR64x8ClassRegClass, |
| 8666 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8667 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8668 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8669 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8670 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8671 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8672 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8673 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8674 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8675 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8676 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8677 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8678 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8679 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8680 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8681 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8682 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8683 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8684 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8685 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8686 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8687 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8688 | nullptr |
| 8689 | }; |
| 8690 | |
| 8691 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8692 | &AArch64::GPR64x8ClassRegClass, |
| 8693 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8694 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8695 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8696 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8697 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8698 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8699 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8700 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8701 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8702 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8703 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8704 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8705 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8706 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8707 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8708 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8709 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8710 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8711 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8712 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8713 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 8714 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 8715 | nullptr |
| 8716 | }; |
| 8717 | |
| 8718 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8719 | &AArch64::GPR64x8ClassRegClass, |
| 8720 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8721 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8722 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8723 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8724 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8725 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8726 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8727 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8728 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8729 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8730 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8731 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8732 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8733 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8734 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8735 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8736 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8737 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8738 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8739 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8740 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8741 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 8742 | nullptr |
| 8743 | }; |
| 8744 | |
| 8745 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 8746 | &AArch64::GPR64x8ClassRegClass, |
| 8747 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8748 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8749 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8750 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8751 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8752 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8753 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8754 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8755 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8756 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8757 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8758 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8759 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8760 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8761 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8762 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8763 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8764 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8765 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8766 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8767 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8768 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8769 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8770 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8771 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8772 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8773 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8774 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8775 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8776 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8777 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8778 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8779 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8780 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8781 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8782 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8783 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 8784 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8785 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8786 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8787 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 8788 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8789 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8790 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8791 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 8792 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 8793 | nullptr |
| 8794 | }; |
| 8795 | |
| 8796 | static const TargetRegisterClass *const GPR64x8Class_with_sub_32_in_GPR32argSuperclasses[] = { |
| 8797 | &AArch64::GPR64x8ClassRegClass, |
| 8798 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8799 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8800 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8801 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8802 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8803 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8804 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8805 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8806 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8807 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8808 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8809 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8810 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8811 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8812 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8813 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8814 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8815 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8816 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8817 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8818 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8819 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8820 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8821 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8822 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8823 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8824 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8825 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8826 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8827 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8828 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8829 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8830 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8831 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8832 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8833 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8834 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 8835 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8836 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8837 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8838 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 8839 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8840 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8841 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8842 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 8843 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 8844 | &AArch64::GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass, |
| 8845 | nullptr |
| 8846 | }; |
| 8847 | |
| 8848 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_GPR64argSuperclasses[] = { |
| 8849 | &AArch64::GPR64x8ClassRegClass, |
| 8850 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8851 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8852 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8853 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8854 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8855 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8856 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8857 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8858 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8859 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8860 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8861 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8862 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8863 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8864 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8865 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8866 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8867 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8868 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8869 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8870 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8871 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8872 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8873 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8874 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8875 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8876 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8877 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8878 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8879 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8880 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8881 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8882 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8883 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8884 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8885 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8886 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 8887 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8888 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8889 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8890 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 8891 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8892 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8893 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8894 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 8895 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 8896 | &AArch64::GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass, |
| 8897 | &AArch64::GPR64x8Class_with_sub_32_in_GPR32argRegClass, |
| 8898 | nullptr |
| 8899 | }; |
| 8900 | |
| 8901 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_GPR64argSuperclasses[] = { |
| 8902 | &AArch64::GPR64x8ClassRegClass, |
| 8903 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 8904 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8905 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8906 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8907 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8908 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8909 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8910 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8911 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8912 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8913 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8914 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 8915 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8916 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8917 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8918 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8919 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8920 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8921 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8922 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8923 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8924 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8925 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8926 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 8927 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8928 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8929 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8930 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8931 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8932 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8933 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8934 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8935 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8936 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8937 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8938 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8939 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 8940 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8941 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8942 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8943 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 8944 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8945 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8946 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8947 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 8948 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 8949 | &AArch64::GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass, |
| 8950 | &AArch64::GPR64x8Class_with_sub_32_in_GPR32argRegClass, |
| 8951 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64argRegClass, |
| 8952 | nullptr |
| 8953 | }; |
| 8954 | |
| 8955 | static const TargetRegisterClass *const rtcGPR64Superclasses[] = { |
| 8956 | &AArch64::GPR64allRegClass, |
| 8957 | &AArch64::GPR64RegClass, |
| 8958 | &AArch64::GPR64spRegClass, |
| 8959 | &AArch64::GPR64commonRegClass, |
| 8960 | &AArch64::tcGPR64RegClass, |
| 8961 | nullptr |
| 8962 | }; |
| 8963 | |
| 8964 | static const TargetRegisterClass *const GPR64sponlySuperclasses[] = { |
| 8965 | &AArch64::GPR64allRegClass, |
| 8966 | &AArch64::GPR64spRegClass, |
| 8967 | nullptr |
| 8968 | }; |
| 8969 | |
| 8970 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_0_in_rtcGPR64Superclasses[] = { |
| 8971 | &AArch64::GPR64x8ClassRegClass, |
| 8972 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8973 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8974 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8975 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 8976 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8977 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8978 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8979 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 8980 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8981 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8982 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 8983 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8984 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8985 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8986 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8987 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8988 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 8989 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8990 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 8991 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8992 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8993 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8994 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 8995 | nullptr |
| 8996 | }; |
| 8997 | |
| 8998 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_2_in_rtcGPR64Superclasses[] = { |
| 8999 | &AArch64::GPR64x8ClassRegClass, |
| 9000 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 9001 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9002 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9003 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9004 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9005 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 9006 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9007 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 9008 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9009 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9010 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 9011 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9012 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9013 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9014 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 9015 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9016 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9017 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9018 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9019 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9020 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9021 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 9022 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9023 | nullptr |
| 9024 | }; |
| 9025 | |
| 9026 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_4_in_rtcGPR64Superclasses[] = { |
| 9027 | &AArch64::GPR64x8ClassRegClass, |
| 9028 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 9029 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9030 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9031 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9032 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9033 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 9034 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9035 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 9036 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9037 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9038 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 9039 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9040 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9041 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9042 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 9043 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9044 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9045 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 9046 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9047 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9048 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9049 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 9050 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 9051 | nullptr |
| 9052 | }; |
| 9053 | |
| 9054 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_6_in_GPR64argSuperclasses[] = { |
| 9055 | &AArch64::GPR64x8ClassRegClass, |
| 9056 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 9057 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9058 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9059 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9060 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9061 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9062 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9063 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 9064 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9065 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9066 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9067 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 9068 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9069 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9070 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9071 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 9072 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9073 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9074 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9075 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9076 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9077 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9078 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9079 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 9080 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9081 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9082 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9083 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9084 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 9085 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9086 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9087 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9088 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9089 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9090 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9091 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9092 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 9093 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9094 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9095 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9096 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 9097 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9098 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9099 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 9100 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 9101 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 9102 | &AArch64::GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass, |
| 9103 | &AArch64::GPR64x8Class_with_sub_32_in_GPR32argRegClass, |
| 9104 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64argRegClass, |
| 9105 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64argRegClass, |
| 9106 | nullptr |
| 9107 | }; |
| 9108 | |
| 9109 | static const TargetRegisterClass *const GPR64x8Class_with_x8sub_6_in_rtcGPR64Superclasses[] = { |
| 9110 | &AArch64::GPR64x8ClassRegClass, |
| 9111 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 9112 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9113 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9114 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9115 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9116 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 9117 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9118 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 9119 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9120 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9121 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 9122 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9123 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 9124 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9125 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 9126 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9127 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9128 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 9129 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9130 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 9131 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 9132 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 9133 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 9134 | nullptr |
| 9135 | }; |
| 9136 | |
| 9137 | static const TargetRegisterClass *const DD_with_dsub0_in_FPR64_loSuperclasses[] = { |
| 9138 | &AArch64::DDRegClass, |
| 9139 | nullptr |
| 9140 | }; |
| 9141 | |
| 9142 | static const TargetRegisterClass *const DD_with_dsub1_in_FPR64_loSuperclasses[] = { |
| 9143 | &AArch64::DDRegClass, |
| 9144 | nullptr |
| 9145 | }; |
| 9146 | |
| 9147 | static const TargetRegisterClass *const DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loSuperclasses[] = { |
| 9148 | &AArch64::DDRegClass, |
| 9149 | &AArch64::DD_with_dsub0_in_FPR64_loRegClass, |
| 9150 | &AArch64::DD_with_dsub1_in_FPR64_loRegClass, |
| 9151 | nullptr |
| 9152 | }; |
| 9153 | |
| 9154 | static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = { |
| 9155 | &AArch64::XSeqPairsClassRegClass, |
| 9156 | nullptr |
| 9157 | }; |
| 9158 | |
| 9159 | static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64noipSuperclasses[] = { |
| 9160 | &AArch64::XSeqPairsClassRegClass, |
| 9161 | nullptr |
| 9162 | }; |
| 9163 | |
| 9164 | static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_GPR64noipSuperclasses[] = { |
| 9165 | &AArch64::XSeqPairsClassRegClass, |
| 9166 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9167 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass, |
| 9168 | nullptr |
| 9169 | }; |
| 9170 | |
| 9171 | static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = { |
| 9172 | &AArch64::XSeqPairsClassRegClass, |
| 9173 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9174 | nullptr |
| 9175 | }; |
| 9176 | |
| 9177 | static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 9178 | &AArch64::XSeqPairsClassRegClass, |
| 9179 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9180 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass, |
| 9181 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass, |
| 9182 | &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass, |
| 9183 | nullptr |
| 9184 | }; |
| 9185 | |
| 9186 | static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = { |
| 9187 | &AArch64::XSeqPairsClassRegClass, |
| 9188 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9189 | &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass, |
| 9190 | nullptr |
| 9191 | }; |
| 9192 | |
| 9193 | static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Superclasses[] = { |
| 9194 | &AArch64::XSeqPairsClassRegClass, |
| 9195 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9196 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass, |
| 9197 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass, |
| 9198 | &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass, |
| 9199 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass, |
| 9200 | &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass, |
| 9201 | nullptr |
| 9202 | }; |
| 9203 | |
| 9204 | static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32argSuperclasses[] = { |
| 9205 | &AArch64::XSeqPairsClassRegClass, |
| 9206 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9207 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass, |
| 9208 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass, |
| 9209 | &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass, |
| 9210 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass, |
| 9211 | &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass, |
| 9212 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass, |
| 9213 | nullptr |
| 9214 | }; |
| 9215 | |
| 9216 | static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses[] = { |
| 9217 | &AArch64::XSeqPairsClassRegClass, |
| 9218 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 9219 | &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass, |
| 9220 | &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass, |
| 9221 | nullptr |
| 9222 | }; |
| 9223 | |
| 9224 | static const TargetRegisterClass *const FPR128_loSuperclasses[] = { |
| 9225 | &AArch64::FPR128RegClass, |
| 9226 | nullptr |
| 9227 | }; |
| 9228 | |
| 9229 | static const TargetRegisterClass *const ZPR_4bSuperclasses[] = { |
| 9230 | &AArch64::ZPRRegClass, |
| 9231 | nullptr |
| 9232 | }; |
| 9233 | |
| 9234 | static const TargetRegisterClass *const ZPR_3bSuperclasses[] = { |
| 9235 | &AArch64::ZPRRegClass, |
| 9236 | &AArch64::ZPR_4bRegClass, |
| 9237 | nullptr |
| 9238 | }; |
| 9239 | |
| 9240 | static const TargetRegisterClass *const DDD_with_dsub0_in_FPR64_loSuperclasses[] = { |
| 9241 | &AArch64::DDDRegClass, |
| 9242 | nullptr |
| 9243 | }; |
| 9244 | |
| 9245 | static const TargetRegisterClass *const DDD_with_dsub1_in_FPR64_loSuperclasses[] = { |
| 9246 | &AArch64::DDDRegClass, |
| 9247 | nullptr |
| 9248 | }; |
| 9249 | |
| 9250 | static const TargetRegisterClass *const DDD_with_dsub2_in_FPR64_loSuperclasses[] = { |
| 9251 | &AArch64::DDDRegClass, |
| 9252 | nullptr |
| 9253 | }; |
| 9254 | |
| 9255 | static const TargetRegisterClass *const DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loSuperclasses[] = { |
| 9256 | &AArch64::DDDRegClass, |
| 9257 | &AArch64::DDD_with_dsub0_in_FPR64_loRegClass, |
| 9258 | &AArch64::DDD_with_dsub1_in_FPR64_loRegClass, |
| 9259 | nullptr |
| 9260 | }; |
| 9261 | |
| 9262 | static const TargetRegisterClass *const DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSuperclasses[] = { |
| 9263 | &AArch64::DDDRegClass, |
| 9264 | &AArch64::DDD_with_dsub1_in_FPR64_loRegClass, |
| 9265 | &AArch64::DDD_with_dsub2_in_FPR64_loRegClass, |
| 9266 | nullptr |
| 9267 | }; |
| 9268 | |
| 9269 | static const TargetRegisterClass *const DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSuperclasses[] = { |
| 9270 | &AArch64::DDDRegClass, |
| 9271 | &AArch64::DDD_with_dsub0_in_FPR64_loRegClass, |
| 9272 | &AArch64::DDD_with_dsub1_in_FPR64_loRegClass, |
| 9273 | &AArch64::DDD_with_dsub2_in_FPR64_loRegClass, |
| 9274 | &AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClass, |
| 9275 | &AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass, |
| 9276 | nullptr |
| 9277 | }; |
| 9278 | |
| 9279 | static const TargetRegisterClass *const DDDD_with_dsub0_in_FPR64_loSuperclasses[] = { |
| 9280 | &AArch64::DDDDRegClass, |
| 9281 | nullptr |
| 9282 | }; |
| 9283 | |
| 9284 | static const TargetRegisterClass *const DDDD_with_dsub1_in_FPR64_loSuperclasses[] = { |
| 9285 | &AArch64::DDDDRegClass, |
| 9286 | nullptr |
| 9287 | }; |
| 9288 | |
| 9289 | static const TargetRegisterClass *const DDDD_with_dsub2_in_FPR64_loSuperclasses[] = { |
| 9290 | &AArch64::DDDDRegClass, |
| 9291 | nullptr |
| 9292 | }; |
| 9293 | |
| 9294 | static const TargetRegisterClass *const DDDD_with_dsub3_in_FPR64_loSuperclasses[] = { |
| 9295 | &AArch64::DDDDRegClass, |
| 9296 | nullptr |
| 9297 | }; |
| 9298 | |
| 9299 | static const TargetRegisterClass *const DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loSuperclasses[] = { |
| 9300 | &AArch64::DDDDRegClass, |
| 9301 | &AArch64::DDDD_with_dsub0_in_FPR64_loRegClass, |
| 9302 | &AArch64::DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9303 | nullptr |
| 9304 | }; |
| 9305 | |
| 9306 | static const TargetRegisterClass *const DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSuperclasses[] = { |
| 9307 | &AArch64::DDDDRegClass, |
| 9308 | &AArch64::DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9309 | &AArch64::DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9310 | nullptr |
| 9311 | }; |
| 9312 | |
| 9313 | static const TargetRegisterClass *const DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSuperclasses[] = { |
| 9314 | &AArch64::DDDDRegClass, |
| 9315 | &AArch64::DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9316 | &AArch64::DDDD_with_dsub3_in_FPR64_loRegClass, |
| 9317 | nullptr |
| 9318 | }; |
| 9319 | |
| 9320 | static const TargetRegisterClass *const DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSuperclasses[] = { |
| 9321 | &AArch64::DDDDRegClass, |
| 9322 | &AArch64::DDDD_with_dsub0_in_FPR64_loRegClass, |
| 9323 | &AArch64::DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9324 | &AArch64::DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9325 | &AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9326 | &AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9327 | nullptr |
| 9328 | }; |
| 9329 | |
| 9330 | static const TargetRegisterClass *const DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSuperclasses[] = { |
| 9331 | &AArch64::DDDDRegClass, |
| 9332 | &AArch64::DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9333 | &AArch64::DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9334 | &AArch64::DDDD_with_dsub3_in_FPR64_loRegClass, |
| 9335 | &AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9336 | &AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass, |
| 9337 | nullptr |
| 9338 | }; |
| 9339 | |
| 9340 | static const TargetRegisterClass *const DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSuperclasses[] = { |
| 9341 | &AArch64::DDDDRegClass, |
| 9342 | &AArch64::DDDD_with_dsub0_in_FPR64_loRegClass, |
| 9343 | &AArch64::DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9344 | &AArch64::DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9345 | &AArch64::DDDD_with_dsub3_in_FPR64_loRegClass, |
| 9346 | &AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClass, |
| 9347 | &AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9348 | &AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass, |
| 9349 | &AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass, |
| 9350 | &AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass, |
| 9351 | nullptr |
| 9352 | }; |
| 9353 | |
| 9354 | static const TargetRegisterClass *const QQ_with_dsub_in_FPR64_loSuperclasses[] = { |
| 9355 | &AArch64::QQRegClass, |
| 9356 | nullptr |
| 9357 | }; |
| 9358 | |
| 9359 | static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = { |
| 9360 | &AArch64::QQRegClass, |
| 9361 | nullptr |
| 9362 | }; |
| 9363 | |
| 9364 | static const TargetRegisterClass *const ZPR2_with_dsub_in_FPR64_loSuperclasses[] = { |
| 9365 | &AArch64::ZPR2RegClass, |
| 9366 | nullptr |
| 9367 | }; |
| 9368 | |
| 9369 | static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = { |
| 9370 | &AArch64::ZPR2RegClass, |
| 9371 | nullptr |
| 9372 | }; |
| 9373 | |
| 9374 | static const TargetRegisterClass *const QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = { |
| 9375 | &AArch64::QQRegClass, |
| 9376 | &AArch64::QQ_with_dsub_in_FPR64_loRegClass, |
| 9377 | &AArch64::QQ_with_qsub1_in_FPR128_loRegClass, |
| 9378 | nullptr |
| 9379 | }; |
| 9380 | |
| 9381 | static const TargetRegisterClass *const ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = { |
| 9382 | &AArch64::ZPR2RegClass, |
| 9383 | &AArch64::ZPR2_with_dsub_in_FPR64_loRegClass, |
| 9384 | &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 9385 | nullptr |
| 9386 | }; |
| 9387 | |
| 9388 | static const TargetRegisterClass *const ZPR2_with_zsub0_in_ZPR_3bSuperclasses[] = { |
| 9389 | &AArch64::ZPR2RegClass, |
| 9390 | &AArch64::ZPR2_with_dsub_in_FPR64_loRegClass, |
| 9391 | &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 9392 | &AArch64::ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 9393 | nullptr |
| 9394 | }; |
| 9395 | |
| 9396 | static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = { |
| 9397 | &AArch64::ZPR2RegClass, |
| 9398 | &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 9399 | nullptr |
| 9400 | }; |
| 9401 | |
| 9402 | static const TargetRegisterClass *const ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = { |
| 9403 | &AArch64::ZPR2RegClass, |
| 9404 | &AArch64::ZPR2_with_dsub_in_FPR64_loRegClass, |
| 9405 | &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 9406 | &AArch64::ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 9407 | &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass, |
| 9408 | &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass, |
| 9409 | nullptr |
| 9410 | }; |
| 9411 | |
| 9412 | static const TargetRegisterClass *const QQQ_with_dsub_in_FPR64_loSuperclasses[] = { |
| 9413 | &AArch64::QQQRegClass, |
| 9414 | nullptr |
| 9415 | }; |
| 9416 | |
| 9417 | static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = { |
| 9418 | &AArch64::QQQRegClass, |
| 9419 | nullptr |
| 9420 | }; |
| 9421 | |
| 9422 | static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = { |
| 9423 | &AArch64::QQQRegClass, |
| 9424 | nullptr |
| 9425 | }; |
| 9426 | |
| 9427 | static const TargetRegisterClass *const ZPR3_with_dsub_in_FPR64_loSuperclasses[] = { |
| 9428 | &AArch64::ZPR3RegClass, |
| 9429 | nullptr |
| 9430 | }; |
| 9431 | |
| 9432 | static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = { |
| 9433 | &AArch64::ZPR3RegClass, |
| 9434 | nullptr |
| 9435 | }; |
| 9436 | |
| 9437 | static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = { |
| 9438 | &AArch64::ZPR3RegClass, |
| 9439 | nullptr |
| 9440 | }; |
| 9441 | |
| 9442 | static const TargetRegisterClass *const QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = { |
| 9443 | &AArch64::QQQRegClass, |
| 9444 | &AArch64::QQQ_with_dsub_in_FPR64_loRegClass, |
| 9445 | &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass, |
| 9446 | nullptr |
| 9447 | }; |
| 9448 | |
| 9449 | static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = { |
| 9450 | &AArch64::QQQRegClass, |
| 9451 | &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass, |
| 9452 | &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass, |
| 9453 | nullptr |
| 9454 | }; |
| 9455 | |
| 9456 | static const TargetRegisterClass *const ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = { |
| 9457 | &AArch64::ZPR3RegClass, |
| 9458 | &AArch64::ZPR3_with_dsub_in_FPR64_loRegClass, |
| 9459 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9460 | nullptr |
| 9461 | }; |
| 9462 | |
| 9463 | static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = { |
| 9464 | &AArch64::ZPR3RegClass, |
| 9465 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9466 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9467 | nullptr |
| 9468 | }; |
| 9469 | |
| 9470 | static const TargetRegisterClass *const QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = { |
| 9471 | &AArch64::QQQRegClass, |
| 9472 | &AArch64::QQQ_with_dsub_in_FPR64_loRegClass, |
| 9473 | &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass, |
| 9474 | &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass, |
| 9475 | &AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass, |
| 9476 | &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass, |
| 9477 | nullptr |
| 9478 | }; |
| 9479 | |
| 9480 | static const TargetRegisterClass *const ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = { |
| 9481 | &AArch64::ZPR3RegClass, |
| 9482 | &AArch64::ZPR3_with_dsub_in_FPR64_loRegClass, |
| 9483 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9484 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9485 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9486 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9487 | nullptr |
| 9488 | }; |
| 9489 | |
| 9490 | static const TargetRegisterClass *const ZPR3_with_zsub0_in_ZPR_3bSuperclasses[] = { |
| 9491 | &AArch64::ZPR3RegClass, |
| 9492 | &AArch64::ZPR3_with_dsub_in_FPR64_loRegClass, |
| 9493 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9494 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9495 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9496 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9497 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9498 | nullptr |
| 9499 | }; |
| 9500 | |
| 9501 | static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = { |
| 9502 | &AArch64::ZPR3RegClass, |
| 9503 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9504 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9505 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9506 | nullptr |
| 9507 | }; |
| 9508 | |
| 9509 | static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = { |
| 9510 | &AArch64::ZPR3RegClass, |
| 9511 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9512 | nullptr |
| 9513 | }; |
| 9514 | |
| 9515 | static const TargetRegisterClass *const ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = { |
| 9516 | &AArch64::ZPR3RegClass, |
| 9517 | &AArch64::ZPR3_with_dsub_in_FPR64_loRegClass, |
| 9518 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9519 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9520 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9521 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9522 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9523 | &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass, |
| 9524 | &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass, |
| 9525 | nullptr |
| 9526 | }; |
| 9527 | |
| 9528 | static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = { |
| 9529 | &AArch64::ZPR3RegClass, |
| 9530 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9531 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9532 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9533 | &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass, |
| 9534 | &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass, |
| 9535 | nullptr |
| 9536 | }; |
| 9537 | |
| 9538 | static const TargetRegisterClass *const ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = { |
| 9539 | &AArch64::ZPR3RegClass, |
| 9540 | &AArch64::ZPR3_with_dsub_in_FPR64_loRegClass, |
| 9541 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9542 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9543 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 9544 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9545 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 9546 | &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass, |
| 9547 | &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass, |
| 9548 | &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass, |
| 9549 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass, |
| 9550 | &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass, |
| 9551 | nullptr |
| 9552 | }; |
| 9553 | |
| 9554 | static const TargetRegisterClass *const QQQQ_with_dsub_in_FPR64_loSuperclasses[] = { |
| 9555 | &AArch64::QQQQRegClass, |
| 9556 | nullptr |
| 9557 | }; |
| 9558 | |
| 9559 | static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = { |
| 9560 | &AArch64::QQQQRegClass, |
| 9561 | nullptr |
| 9562 | }; |
| 9563 | |
| 9564 | static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = { |
| 9565 | &AArch64::QQQQRegClass, |
| 9566 | nullptr |
| 9567 | }; |
| 9568 | |
| 9569 | static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = { |
| 9570 | &AArch64::QQQQRegClass, |
| 9571 | nullptr |
| 9572 | }; |
| 9573 | |
| 9574 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_loSuperclasses[] = { |
| 9575 | &AArch64::ZPR4RegClass, |
| 9576 | nullptr |
| 9577 | }; |
| 9578 | |
| 9579 | static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = { |
| 9580 | &AArch64::ZPR4RegClass, |
| 9581 | nullptr |
| 9582 | }; |
| 9583 | |
| 9584 | static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = { |
| 9585 | &AArch64::ZPR4RegClass, |
| 9586 | nullptr |
| 9587 | }; |
| 9588 | |
| 9589 | static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = { |
| 9590 | &AArch64::ZPR4RegClass, |
| 9591 | nullptr |
| 9592 | }; |
| 9593 | |
| 9594 | static const TargetRegisterClass *const QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = { |
| 9595 | &AArch64::QQQQRegClass, |
| 9596 | &AArch64::QQQQ_with_dsub_in_FPR64_loRegClass, |
| 9597 | &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9598 | nullptr |
| 9599 | }; |
| 9600 | |
| 9601 | static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = { |
| 9602 | &AArch64::QQQQRegClass, |
| 9603 | &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9604 | &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9605 | nullptr |
| 9606 | }; |
| 9607 | |
| 9608 | static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = { |
| 9609 | &AArch64::QQQQRegClass, |
| 9610 | &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9611 | &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 9612 | nullptr |
| 9613 | }; |
| 9614 | |
| 9615 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = { |
| 9616 | &AArch64::ZPR4RegClass, |
| 9617 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9618 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9619 | nullptr |
| 9620 | }; |
| 9621 | |
| 9622 | static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = { |
| 9623 | &AArch64::ZPR4RegClass, |
| 9624 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9625 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9626 | nullptr |
| 9627 | }; |
| 9628 | |
| 9629 | static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = { |
| 9630 | &AArch64::ZPR4RegClass, |
| 9631 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9632 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9633 | nullptr |
| 9634 | }; |
| 9635 | |
| 9636 | static const TargetRegisterClass *const QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = { |
| 9637 | &AArch64::QQQQRegClass, |
| 9638 | &AArch64::QQQQ_with_dsub_in_FPR64_loRegClass, |
| 9639 | &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9640 | &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9641 | &AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9642 | &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9643 | nullptr |
| 9644 | }; |
| 9645 | |
| 9646 | static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = { |
| 9647 | &AArch64::QQQQRegClass, |
| 9648 | &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9649 | &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9650 | &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 9651 | &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9652 | &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 9653 | nullptr |
| 9654 | }; |
| 9655 | |
| 9656 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = { |
| 9657 | &AArch64::ZPR4RegClass, |
| 9658 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9659 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9660 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9661 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9662 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9663 | nullptr |
| 9664 | }; |
| 9665 | |
| 9666 | static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = { |
| 9667 | &AArch64::ZPR4RegClass, |
| 9668 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9669 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9670 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9671 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9672 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9673 | nullptr |
| 9674 | }; |
| 9675 | |
| 9676 | static const TargetRegisterClass *const QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = { |
| 9677 | &AArch64::QQQQRegClass, |
| 9678 | &AArch64::QQQQ_with_dsub_in_FPR64_loRegClass, |
| 9679 | &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9680 | &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9681 | &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 9682 | &AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 9683 | &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9684 | &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 9685 | &AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 9686 | &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 9687 | nullptr |
| 9688 | }; |
| 9689 | |
| 9690 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = { |
| 9691 | &AArch64::ZPR4RegClass, |
| 9692 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9693 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9694 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9695 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9696 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9697 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9698 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9699 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9700 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9701 | nullptr |
| 9702 | }; |
| 9703 | |
| 9704 | static const TargetRegisterClass *const ZPR4_with_zsub0_in_ZPR_3bSuperclasses[] = { |
| 9705 | &AArch64::ZPR4RegClass, |
| 9706 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9707 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9708 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9709 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9710 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9711 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9712 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9713 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9714 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9715 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9716 | nullptr |
| 9717 | }; |
| 9718 | |
| 9719 | static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = { |
| 9720 | &AArch64::ZPR4RegClass, |
| 9721 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9722 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9723 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9724 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9725 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9726 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9727 | nullptr |
| 9728 | }; |
| 9729 | |
| 9730 | static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = { |
| 9731 | &AArch64::ZPR4RegClass, |
| 9732 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9733 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9734 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9735 | nullptr |
| 9736 | }; |
| 9737 | |
| 9738 | static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = { |
| 9739 | &AArch64::ZPR4RegClass, |
| 9740 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9741 | nullptr |
| 9742 | }; |
| 9743 | |
| 9744 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = { |
| 9745 | &AArch64::ZPR4RegClass, |
| 9746 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9747 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9748 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9749 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9750 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9751 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9752 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9753 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9754 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9755 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9756 | &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass, |
| 9757 | &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9758 | nullptr |
| 9759 | }; |
| 9760 | |
| 9761 | static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = { |
| 9762 | &AArch64::ZPR4RegClass, |
| 9763 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9764 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9765 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9766 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9767 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9768 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9769 | &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9770 | &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9771 | nullptr |
| 9772 | }; |
| 9773 | |
| 9774 | static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = { |
| 9775 | &AArch64::ZPR4RegClass, |
| 9776 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9777 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9778 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9779 | &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9780 | &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 9781 | nullptr |
| 9782 | }; |
| 9783 | |
| 9784 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = { |
| 9785 | &AArch64::ZPR4RegClass, |
| 9786 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9787 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9788 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9789 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9790 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9791 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9792 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9793 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9794 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9795 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9796 | &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass, |
| 9797 | &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9798 | &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9799 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9800 | &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9801 | nullptr |
| 9802 | }; |
| 9803 | |
| 9804 | static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = { |
| 9805 | &AArch64::ZPR4RegClass, |
| 9806 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9807 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9808 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9809 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9810 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9811 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9812 | &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9813 | &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9814 | &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 9815 | &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9816 | &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 9817 | nullptr |
| 9818 | }; |
| 9819 | |
| 9820 | static const TargetRegisterClass *const ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = { |
| 9821 | &AArch64::ZPR4RegClass, |
| 9822 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 9823 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9824 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9825 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9826 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 9827 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9828 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9829 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 9830 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9831 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 9832 | &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass, |
| 9833 | &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9834 | &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9835 | &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 9836 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 9837 | &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9838 | &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 9839 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 9840 | &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 9841 | nullptr |
| 9842 | }; |
| 9843 | |
| 9844 | |
| 9845 | static inline unsigned GPR32AltOrderSelect(const MachineFunction &MF) { return 1; } |
| 9846 | |
| 9847 | static ArrayRef<MCPhysReg> GPR32GetRawAllocationOrder(const MachineFunction &MF) { |
| 9848 | static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 }; |
| 9849 | const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID]; |
| 9850 | const ArrayRef<MCPhysReg> Order[] = { |
| 9851 | makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| 9852 | makeArrayRef(AltOrder1) |
| 9853 | }; |
| 9854 | const unsigned Select = GPR32AltOrderSelect(MF); |
| 9855 | assert(Select < 2); |
| 9856 | return Order[Select]; |
| 9857 | } |
| 9858 | |
| 9859 | static inline unsigned GPR32spAltOrderSelect(const MachineFunction &MF) { return 1; } |
| 9860 | |
| 9861 | static ArrayRef<MCPhysReg> GPR32spGetRawAllocationOrder(const MachineFunction &MF) { |
| 9862 | static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 }; |
| 9863 | const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID]; |
| 9864 | const ArrayRef<MCPhysReg> Order[] = { |
| 9865 | makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| 9866 | makeArrayRef(AltOrder1) |
| 9867 | }; |
| 9868 | const unsigned Select = GPR32spAltOrderSelect(MF); |
| 9869 | assert(Select < 2); |
| 9870 | return Order[Select]; |
| 9871 | } |
| 9872 | |
| 9873 | static inline unsigned GPR32commonAltOrderSelect(const MachineFunction &MF) { return 1; } |
| 9874 | |
| 9875 | static ArrayRef<MCPhysReg> GPR32commonGetRawAllocationOrder(const MachineFunction &MF) { |
| 9876 | static const MCPhysReg AltOrder1[] = { AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 }; |
| 9877 | const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID]; |
| 9878 | const ArrayRef<MCPhysReg> Order[] = { |
| 9879 | makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| 9880 | makeArrayRef(AltOrder1) |
| 9881 | }; |
| 9882 | const unsigned Select = GPR32commonAltOrderSelect(MF); |
| 9883 | assert(Select < 2); |
| 9884 | return Order[Select]; |
| 9885 | } |
| 9886 | |
| 9887 | static inline unsigned GPR64AltOrderSelect(const MachineFunction &MF) { return 1; } |
| 9888 | |
| 9889 | static ArrayRef<MCPhysReg> GPR64GetRawAllocationOrder(const MachineFunction &MF) { |
| 9890 | static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 }; |
| 9891 | const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID]; |
| 9892 | const ArrayRef<MCPhysReg> Order[] = { |
| 9893 | makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| 9894 | makeArrayRef(AltOrder1) |
| 9895 | }; |
| 9896 | const unsigned Select = GPR64AltOrderSelect(MF); |
| 9897 | assert(Select < 2); |
| 9898 | return Order[Select]; |
| 9899 | } |
| 9900 | |
| 9901 | static inline unsigned GPR64spAltOrderSelect(const MachineFunction &MF) { return 1; } |
| 9902 | |
| 9903 | static ArrayRef<MCPhysReg> GPR64spGetRawAllocationOrder(const MachineFunction &MF) { |
| 9904 | static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 }; |
| 9905 | const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID]; |
| 9906 | const ArrayRef<MCPhysReg> Order[] = { |
| 9907 | makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| 9908 | makeArrayRef(AltOrder1) |
| 9909 | }; |
| 9910 | const unsigned Select = GPR64spAltOrderSelect(MF); |
| 9911 | assert(Select < 2); |
| 9912 | return Order[Select]; |
| 9913 | } |
| 9914 | |
| 9915 | static inline unsigned GPR64commonAltOrderSelect(const MachineFunction &MF) { return 1; } |
| 9916 | |
| 9917 | static ArrayRef<MCPhysReg> GPR64commonGetRawAllocationOrder(const MachineFunction &MF) { |
| 9918 | static const MCPhysReg AltOrder1[] = { AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 }; |
| 9919 | const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64commonRegClassID]; |
| 9920 | const ArrayRef<MCPhysReg> Order[] = { |
| 9921 | makeArrayRef(MCR.begin(), MCR.getNumRegs()), |
| 9922 | makeArrayRef(AltOrder1) |
| 9923 | }; |
| 9924 | const unsigned Select = GPR64commonAltOrderSelect(MF); |
| 9925 | assert(Select < 2); |
| 9926 | return Order[Select]; |
| 9927 | } |
| 9928 | |
| 9929 | namespace AArch64 { // Register class instances |
| 9930 | extern const TargetRegisterClass FPR8RegClass = { |
| 9931 | &AArch64MCRegisterClasses[FPR8RegClassID], |
| 9932 | FPR8SubClassMask, |
| 9933 | SuperRegIdxSeqs + 30, |
| 9934 | LaneBitmask(0x0000000000000001), |
| 9935 | 0, |
| 9936 | false, /* HasDisjunctSubRegs */ |
| 9937 | false, /* CoveredBySubRegs */ |
| 9938 | NullRegClasses, |
| 9939 | nullptr |
| 9940 | }; |
| 9941 | |
| 9942 | extern const TargetRegisterClass FPR16RegClass = { |
| 9943 | &AArch64MCRegisterClasses[FPR16RegClassID], |
| 9944 | FPR16SubClassMask, |
| 9945 | SuperRegIdxSeqs + 53, |
| 9946 | LaneBitmask(0x0000000000000001), |
| 9947 | 0, |
| 9948 | false, /* HasDisjunctSubRegs */ |
| 9949 | false, /* CoveredBySubRegs */ |
| 9950 | NullRegClasses, |
| 9951 | nullptr |
| 9952 | }; |
| 9953 | |
| 9954 | extern const TargetRegisterClass FPR16_loRegClass = { |
| 9955 | &AArch64MCRegisterClasses[FPR16_loRegClassID], |
| 9956 | FPR16_loSubClassMask, |
| 9957 | SuperRegIdxSeqs + 53, |
| 9958 | LaneBitmask(0x0000000000000001), |
| 9959 | 0, |
| 9960 | false, /* HasDisjunctSubRegs */ |
| 9961 | false, /* CoveredBySubRegs */ |
| 9962 | FPR16_loSuperclasses, |
| 9963 | nullptr |
| 9964 | }; |
| 9965 | |
| 9966 | extern const TargetRegisterClass PPRRegClass = { |
| 9967 | &AArch64MCRegisterClasses[PPRRegClassID], |
| 9968 | PPRSubClassMask, |
| 9969 | SuperRegIdxSeqs + 1, |
| 9970 | LaneBitmask(0x0000000000000001), |
| 9971 | 0, |
| 9972 | false, /* HasDisjunctSubRegs */ |
| 9973 | false, /* CoveredBySubRegs */ |
| 9974 | NullRegClasses, |
| 9975 | nullptr |
| 9976 | }; |
| 9977 | |
| 9978 | extern const TargetRegisterClass PPR_3bRegClass = { |
| 9979 | &AArch64MCRegisterClasses[PPR_3bRegClassID], |
| 9980 | PPR_3bSubClassMask, |
| 9981 | SuperRegIdxSeqs + 1, |
| 9982 | LaneBitmask(0x0000000000000001), |
| 9983 | 0, |
| 9984 | false, /* HasDisjunctSubRegs */ |
| 9985 | false, /* CoveredBySubRegs */ |
| 9986 | PPR_3bSuperclasses, |
| 9987 | nullptr |
| 9988 | }; |
| 9989 | |
| 9990 | extern const TargetRegisterClass GPR32allRegClass = { |
| 9991 | &AArch64MCRegisterClasses[GPR32allRegClassID], |
| 9992 | GPR32allSubClassMask, |
| 9993 | SuperRegIdxSeqs + 18, |
| 9994 | LaneBitmask(0x0000000000000001), |
| 9995 | 0, |
| 9996 | false, /* HasDisjunctSubRegs */ |
| 9997 | false, /* CoveredBySubRegs */ |
| 9998 | NullRegClasses, |
| 9999 | nullptr |
| 10000 | }; |
| 10001 | |
| 10002 | extern const TargetRegisterClass FPR32RegClass = { |
| 10003 | &AArch64MCRegisterClasses[FPR32RegClassID], |
| 10004 | FPR32SubClassMask, |
| 10005 | SuperRegIdxSeqs + 64, |
| 10006 | LaneBitmask(0x0000000000000001), |
| 10007 | 0, |
| 10008 | false, /* HasDisjunctSubRegs */ |
| 10009 | false, /* CoveredBySubRegs */ |
| 10010 | NullRegClasses, |
| 10011 | nullptr |
| 10012 | }; |
| 10013 | |
| 10014 | extern const TargetRegisterClass GPR32RegClass = { |
| 10015 | &AArch64MCRegisterClasses[GPR32RegClassID], |
| 10016 | GPR32SubClassMask, |
| 10017 | SuperRegIdxSeqs + 18, |
| 10018 | LaneBitmask(0x0000000000000001), |
| 10019 | 0, |
| 10020 | false, /* HasDisjunctSubRegs */ |
| 10021 | false, /* CoveredBySubRegs */ |
| 10022 | GPR32Superclasses, |
| 10023 | GPR32GetRawAllocationOrder |
| 10024 | }; |
| 10025 | |
| 10026 | extern const TargetRegisterClass GPR32spRegClass = { |
| 10027 | &AArch64MCRegisterClasses[GPR32spRegClassID], |
| 10028 | GPR32spSubClassMask, |
| 10029 | SuperRegIdxSeqs + 18, |
| 10030 | LaneBitmask(0x0000000000000001), |
| 10031 | 0, |
| 10032 | false, /* HasDisjunctSubRegs */ |
| 10033 | false, /* CoveredBySubRegs */ |
| 10034 | GPR32spSuperclasses, |
| 10035 | GPR32spGetRawAllocationOrder |
| 10036 | }; |
| 10037 | |
| 10038 | extern const TargetRegisterClass GPR32commonRegClass = { |
| 10039 | &AArch64MCRegisterClasses[GPR32commonRegClassID], |
| 10040 | GPR32commonSubClassMask, |
| 10041 | SuperRegIdxSeqs + 18, |
| 10042 | LaneBitmask(0x0000000000000001), |
| 10043 | 0, |
| 10044 | false, /* HasDisjunctSubRegs */ |
| 10045 | false, /* CoveredBySubRegs */ |
| 10046 | GPR32commonSuperclasses, |
| 10047 | GPR32commonGetRawAllocationOrder |
| 10048 | }; |
| 10049 | |
| 10050 | extern const TargetRegisterClass FPR32_with_hsub_in_FPR16_loRegClass = { |
| 10051 | &AArch64MCRegisterClasses[FPR32_with_hsub_in_FPR16_loRegClassID], |
| 10052 | FPR32_with_hsub_in_FPR16_loSubClassMask, |
| 10053 | SuperRegIdxSeqs + 64, |
| 10054 | LaneBitmask(0x0000000000000001), |
| 10055 | 0, |
| 10056 | false, /* HasDisjunctSubRegs */ |
| 10057 | false, /* CoveredBySubRegs */ |
| 10058 | FPR32_with_hsub_in_FPR16_loSuperclasses, |
| 10059 | nullptr |
| 10060 | }; |
| 10061 | |
| 10062 | extern const TargetRegisterClass GPR32argRegClass = { |
| 10063 | &AArch64MCRegisterClasses[GPR32argRegClassID], |
| 10064 | GPR32argSubClassMask, |
| 10065 | SuperRegIdxSeqs + 18, |
| 10066 | LaneBitmask(0x0000000000000001), |
| 10067 | 0, |
| 10068 | false, /* HasDisjunctSubRegs */ |
| 10069 | false, /* CoveredBySubRegs */ |
| 10070 | GPR32argSuperclasses, |
| 10071 | nullptr |
| 10072 | }; |
| 10073 | |
| 10074 | extern const TargetRegisterClass CCRRegClass = { |
| 10075 | &AArch64MCRegisterClasses[CCRRegClassID], |
| 10076 | CCRSubClassMask, |
| 10077 | SuperRegIdxSeqs + 1, |
| 10078 | LaneBitmask(0x0000000000000001), |
| 10079 | 0, |
| 10080 | false, /* HasDisjunctSubRegs */ |
| 10081 | false, /* CoveredBySubRegs */ |
| 10082 | NullRegClasses, |
| 10083 | nullptr |
| 10084 | }; |
| 10085 | |
| 10086 | extern const TargetRegisterClass GPR32sponlyRegClass = { |
| 10087 | &AArch64MCRegisterClasses[GPR32sponlyRegClassID], |
| 10088 | GPR32sponlySubClassMask, |
| 10089 | SuperRegIdxSeqs + 0, |
| 10090 | LaneBitmask(0x0000000000000001), |
| 10091 | 0, |
| 10092 | false, /* HasDisjunctSubRegs */ |
| 10093 | false, /* CoveredBySubRegs */ |
| 10094 | GPR32sponlySuperclasses, |
| 10095 | nullptr |
| 10096 | }; |
| 10097 | |
| 10098 | extern const TargetRegisterClass WSeqPairsClassRegClass = { |
| 10099 | &AArch64MCRegisterClasses[WSeqPairsClassRegClassID], |
| 10100 | WSeqPairsClassSubClassMask, |
| 10101 | SuperRegIdxSeqs + 89, |
| 10102 | LaneBitmask(0x0000000000000030), |
| 10103 | 0, |
| 10104 | true, /* HasDisjunctSubRegs */ |
| 10105 | true, /* CoveredBySubRegs */ |
| 10106 | NullRegClasses, |
| 10107 | nullptr |
| 10108 | }; |
| 10109 | |
| 10110 | extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = { |
| 10111 | &AArch64MCRegisterClasses[WSeqPairsClass_with_subo32_in_GPR32commonRegClassID], |
| 10112 | WSeqPairsClass_with_subo32_in_GPR32commonSubClassMask, |
| 10113 | SuperRegIdxSeqs + 89, |
| 10114 | LaneBitmask(0x0000000000000030), |
| 10115 | 0, |
| 10116 | true, /* HasDisjunctSubRegs */ |
| 10117 | true, /* CoveredBySubRegs */ |
| 10118 | WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses, |
| 10119 | nullptr |
| 10120 | }; |
| 10121 | |
| 10122 | extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass = { |
| 10123 | &AArch64MCRegisterClasses[WSeqPairsClass_with_sube32_in_GPR32argRegClassID], |
| 10124 | WSeqPairsClass_with_sube32_in_GPR32argSubClassMask, |
| 10125 | SuperRegIdxSeqs + 89, |
| 10126 | LaneBitmask(0x0000000000000030), |
| 10127 | 0, |
| 10128 | true, /* HasDisjunctSubRegs */ |
| 10129 | true, /* CoveredBySubRegs */ |
| 10130 | WSeqPairsClass_with_sube32_in_GPR32argSuperclasses, |
| 10131 | nullptr |
| 10132 | }; |
| 10133 | |
| 10134 | extern const TargetRegisterClass GPR64allRegClass = { |
| 10135 | &AArch64MCRegisterClasses[GPR64allRegClassID], |
| 10136 | GPR64allSubClassMask, |
| 10137 | SuperRegIdxSeqs + 2, |
| 10138 | LaneBitmask(0x0000000000000008), |
| 10139 | 0, |
| 10140 | false, /* HasDisjunctSubRegs */ |
| 10141 | false, /* CoveredBySubRegs */ |
| 10142 | NullRegClasses, |
| 10143 | nullptr |
| 10144 | }; |
| 10145 | |
| 10146 | extern const TargetRegisterClass FPR64RegClass = { |
| 10147 | &AArch64MCRegisterClasses[FPR64RegClassID], |
| 10148 | FPR64SubClassMask, |
| 10149 | SuperRegIdxSeqs + 41, |
| 10150 | LaneBitmask(0x0000000000000001), |
| 10151 | 0, |
| 10152 | false, /* HasDisjunctSubRegs */ |
| 10153 | false, /* CoveredBySubRegs */ |
| 10154 | NullRegClasses, |
| 10155 | nullptr |
| 10156 | }; |
| 10157 | |
| 10158 | extern const TargetRegisterClass GPR64RegClass = { |
| 10159 | &AArch64MCRegisterClasses[GPR64RegClassID], |
| 10160 | GPR64SubClassMask, |
| 10161 | SuperRegIdxSeqs + 2, |
| 10162 | LaneBitmask(0x0000000000000008), |
| 10163 | 0, |
| 10164 | false, /* HasDisjunctSubRegs */ |
| 10165 | false, /* CoveredBySubRegs */ |
| 10166 | GPR64Superclasses, |
| 10167 | GPR64GetRawAllocationOrder |
| 10168 | }; |
| 10169 | |
| 10170 | extern const TargetRegisterClass GPR64spRegClass = { |
| 10171 | &AArch64MCRegisterClasses[GPR64spRegClassID], |
| 10172 | GPR64spSubClassMask, |
| 10173 | SuperRegIdxSeqs + 2, |
| 10174 | LaneBitmask(0x0000000000000008), |
| 10175 | 0, |
| 10176 | false, /* HasDisjunctSubRegs */ |
| 10177 | false, /* CoveredBySubRegs */ |
| 10178 | GPR64spSuperclasses, |
| 10179 | GPR64spGetRawAllocationOrder |
| 10180 | }; |
| 10181 | |
| 10182 | extern const TargetRegisterClass GPR64commonRegClass = { |
| 10183 | &AArch64MCRegisterClasses[GPR64commonRegClassID], |
| 10184 | GPR64commonSubClassMask, |
| 10185 | SuperRegIdxSeqs + 2, |
| 10186 | LaneBitmask(0x0000000000000008), |
| 10187 | 0, |
| 10188 | false, /* HasDisjunctSubRegs */ |
| 10189 | false, /* CoveredBySubRegs */ |
| 10190 | GPR64commonSuperclasses, |
| 10191 | GPR64commonGetRawAllocationOrder |
| 10192 | }; |
| 10193 | |
| 10194 | extern const TargetRegisterClass GPR64noipRegClass = { |
| 10195 | &AArch64MCRegisterClasses[GPR64noipRegClassID], |
| 10196 | GPR64noipSubClassMask, |
| 10197 | SuperRegIdxSeqs + 2, |
| 10198 | LaneBitmask(0x0000000000000008), |
| 10199 | 0, |
| 10200 | false, /* HasDisjunctSubRegs */ |
| 10201 | false, /* CoveredBySubRegs */ |
| 10202 | GPR64noipSuperclasses, |
| 10203 | nullptr |
| 10204 | }; |
| 10205 | |
| 10206 | extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass = { |
| 10207 | &AArch64MCRegisterClasses[GPR64common_and_GPR64noipRegClassID], |
| 10208 | GPR64common_and_GPR64noipSubClassMask, |
| 10209 | SuperRegIdxSeqs + 2, |
| 10210 | LaneBitmask(0x0000000000000008), |
| 10211 | 0, |
| 10212 | false, /* HasDisjunctSubRegs */ |
| 10213 | false, /* CoveredBySubRegs */ |
| 10214 | GPR64common_and_GPR64noipSuperclasses, |
| 10215 | nullptr |
| 10216 | }; |
| 10217 | |
| 10218 | extern const TargetRegisterClass tcGPR64RegClass = { |
| 10219 | &AArch64MCRegisterClasses[tcGPR64RegClassID], |
| 10220 | tcGPR64SubClassMask, |
| 10221 | SuperRegIdxSeqs + 2, |
| 10222 | LaneBitmask(0x0000000000000008), |
| 10223 | 0, |
| 10224 | false, /* HasDisjunctSubRegs */ |
| 10225 | false, /* CoveredBySubRegs */ |
| 10226 | tcGPR64Superclasses, |
| 10227 | nullptr |
| 10228 | }; |
| 10229 | |
| 10230 | extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass = { |
| 10231 | &AArch64MCRegisterClasses[GPR64noip_and_tcGPR64RegClassID], |
| 10232 | GPR64noip_and_tcGPR64SubClassMask, |
| 10233 | SuperRegIdxSeqs + 2, |
| 10234 | LaneBitmask(0x0000000000000008), |
| 10235 | 0, |
| 10236 | false, /* HasDisjunctSubRegs */ |
| 10237 | false, /* CoveredBySubRegs */ |
| 10238 | GPR64noip_and_tcGPR64Superclasses, |
| 10239 | nullptr |
| 10240 | }; |
| 10241 | |
| 10242 | extern const TargetRegisterClass FPR64_loRegClass = { |
| 10243 | &AArch64MCRegisterClasses[FPR64_loRegClassID], |
| 10244 | FPR64_loSubClassMask, |
| 10245 | SuperRegIdxSeqs + 41, |
| 10246 | LaneBitmask(0x0000000000000001), |
| 10247 | 0, |
| 10248 | false, /* HasDisjunctSubRegs */ |
| 10249 | false, /* CoveredBySubRegs */ |
| 10250 | FPR64_loSuperclasses, |
| 10251 | nullptr |
| 10252 | }; |
| 10253 | |
| 10254 | extern const TargetRegisterClass GPR64x8ClassRegClass = { |
| 10255 | &AArch64MCRegisterClasses[GPR64x8ClassRegClassID], |
| 10256 | GPR64x8ClassSubClassMask, |
| 10257 | SuperRegIdxSeqs + 1, |
| 10258 | LaneBitmask(0x00000000000FE008), |
| 10259 | 0, |
| 10260 | true, /* HasDisjunctSubRegs */ |
| 10261 | true, /* CoveredBySubRegs */ |
| 10262 | NullRegClasses, |
| 10263 | nullptr |
| 10264 | }; |
| 10265 | |
| 10266 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass = { |
| 10267 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_GPR64noipRegClassID], |
| 10268 | GPR64x8Class_with_x8sub_0_in_GPR64noipSubClassMask, |
| 10269 | SuperRegIdxSeqs + 1, |
| 10270 | LaneBitmask(0x00000000000FE008), |
| 10271 | 0, |
| 10272 | true, /* HasDisjunctSubRegs */ |
| 10273 | true, /* CoveredBySubRegs */ |
| 10274 | GPR64x8Class_with_x8sub_0_in_GPR64noipSuperclasses, |
| 10275 | nullptr |
| 10276 | }; |
| 10277 | |
| 10278 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass = { |
| 10279 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID], |
| 10280 | GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask, |
| 10281 | SuperRegIdxSeqs + 1, |
| 10282 | LaneBitmask(0x00000000000FE008), |
| 10283 | 0, |
| 10284 | true, /* HasDisjunctSubRegs */ |
| 10285 | true, /* CoveredBySubRegs */ |
| 10286 | GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses, |
| 10287 | nullptr |
| 10288 | }; |
| 10289 | |
| 10290 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10291 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10292 | GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10293 | SuperRegIdxSeqs + 1, |
| 10294 | LaneBitmask(0x00000000000FE008), |
| 10295 | 0, |
| 10296 | true, /* HasDisjunctSubRegs */ |
| 10297 | true, /* CoveredBySubRegs */ |
| 10298 | GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10299 | nullptr |
| 10300 | }; |
| 10301 | |
| 10302 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10303 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10304 | GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10305 | SuperRegIdxSeqs + 1, |
| 10306 | LaneBitmask(0x00000000000FE008), |
| 10307 | 0, |
| 10308 | true, /* HasDisjunctSubRegs */ |
| 10309 | true, /* CoveredBySubRegs */ |
| 10310 | GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10311 | nullptr |
| 10312 | }; |
| 10313 | |
| 10314 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass = { |
| 10315 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID], |
| 10316 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask, |
| 10317 | SuperRegIdxSeqs + 1, |
| 10318 | LaneBitmask(0x00000000000FE008), |
| 10319 | 0, |
| 10320 | true, /* HasDisjunctSubRegs */ |
| 10321 | true, /* CoveredBySubRegs */ |
| 10322 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses, |
| 10323 | nullptr |
| 10324 | }; |
| 10325 | |
| 10326 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10327 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10328 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10329 | SuperRegIdxSeqs + 1, |
| 10330 | LaneBitmask(0x00000000000FE008), |
| 10331 | 0, |
| 10332 | true, /* HasDisjunctSubRegs */ |
| 10333 | true, /* CoveredBySubRegs */ |
| 10334 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10335 | nullptr |
| 10336 | }; |
| 10337 | |
| 10338 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10339 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10340 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10341 | SuperRegIdxSeqs + 1, |
| 10342 | LaneBitmask(0x00000000000FE008), |
| 10343 | 0, |
| 10344 | true, /* HasDisjunctSubRegs */ |
| 10345 | true, /* CoveredBySubRegs */ |
| 10346 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10347 | nullptr |
| 10348 | }; |
| 10349 | |
| 10350 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass = { |
| 10351 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64RegClassID], |
| 10352 | GPR64x8Class_with_x8sub_0_in_tcGPR64SubClassMask, |
| 10353 | SuperRegIdxSeqs + 1, |
| 10354 | LaneBitmask(0x00000000000FE008), |
| 10355 | 0, |
| 10356 | true, /* HasDisjunctSubRegs */ |
| 10357 | true, /* CoveredBySubRegs */ |
| 10358 | GPR64x8Class_with_x8sub_0_in_tcGPR64Superclasses, |
| 10359 | nullptr |
| 10360 | }; |
| 10361 | |
| 10362 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10363 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10364 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10365 | SuperRegIdxSeqs + 1, |
| 10366 | LaneBitmask(0x00000000000FE008), |
| 10367 | 0, |
| 10368 | true, /* HasDisjunctSubRegs */ |
| 10369 | true, /* CoveredBySubRegs */ |
| 10370 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10371 | nullptr |
| 10372 | }; |
| 10373 | |
| 10374 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10375 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10376 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10377 | SuperRegIdxSeqs + 1, |
| 10378 | LaneBitmask(0x00000000000FE008), |
| 10379 | 0, |
| 10380 | true, /* HasDisjunctSubRegs */ |
| 10381 | true, /* CoveredBySubRegs */ |
| 10382 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10383 | nullptr |
| 10384 | }; |
| 10385 | |
| 10386 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10387 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10388 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10389 | SuperRegIdxSeqs + 1, |
| 10390 | LaneBitmask(0x00000000000FE008), |
| 10391 | 0, |
| 10392 | true, /* HasDisjunctSubRegs */ |
| 10393 | true, /* CoveredBySubRegs */ |
| 10394 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10395 | nullptr |
| 10396 | }; |
| 10397 | |
| 10398 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass = { |
| 10399 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClassID], |
| 10400 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10401 | SuperRegIdxSeqs + 1, |
| 10402 | LaneBitmask(0x00000000000FE008), |
| 10403 | 0, |
| 10404 | true, /* HasDisjunctSubRegs */ |
| 10405 | true, /* CoveredBySubRegs */ |
| 10406 | GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64Superclasses, |
| 10407 | nullptr |
| 10408 | }; |
| 10409 | |
| 10410 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass = { |
| 10411 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID], |
| 10412 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask, |
| 10413 | SuperRegIdxSeqs + 1, |
| 10414 | LaneBitmask(0x00000000000FE008), |
| 10415 | 0, |
| 10416 | true, /* HasDisjunctSubRegs */ |
| 10417 | true, /* CoveredBySubRegs */ |
| 10418 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses, |
| 10419 | nullptr |
| 10420 | }; |
| 10421 | |
| 10422 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10423 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10424 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10425 | SuperRegIdxSeqs + 1, |
| 10426 | LaneBitmask(0x00000000000FE008), |
| 10427 | 0, |
| 10428 | true, /* HasDisjunctSubRegs */ |
| 10429 | true, /* CoveredBySubRegs */ |
| 10430 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10431 | nullptr |
| 10432 | }; |
| 10433 | |
| 10434 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10435 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10436 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10437 | SuperRegIdxSeqs + 1, |
| 10438 | LaneBitmask(0x00000000000FE008), |
| 10439 | 0, |
| 10440 | true, /* HasDisjunctSubRegs */ |
| 10441 | true, /* CoveredBySubRegs */ |
| 10442 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10443 | nullptr |
| 10444 | }; |
| 10445 | |
| 10446 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass = { |
| 10447 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_1_in_tcGPR64RegClassID], |
| 10448 | GPR64x8Class_with_x8sub_1_in_tcGPR64SubClassMask, |
| 10449 | SuperRegIdxSeqs + 1, |
| 10450 | LaneBitmask(0x00000000000FE008), |
| 10451 | 0, |
| 10452 | true, /* HasDisjunctSubRegs */ |
| 10453 | true, /* CoveredBySubRegs */ |
| 10454 | GPR64x8Class_with_x8sub_1_in_tcGPR64Superclasses, |
| 10455 | nullptr |
| 10456 | }; |
| 10457 | |
| 10458 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10459 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10460 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10461 | SuperRegIdxSeqs + 1, |
| 10462 | LaneBitmask(0x00000000000FE008), |
| 10463 | 0, |
| 10464 | true, /* HasDisjunctSubRegs */ |
| 10465 | true, /* CoveredBySubRegs */ |
| 10466 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10467 | nullptr |
| 10468 | }; |
| 10469 | |
| 10470 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10471 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10472 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10473 | SuperRegIdxSeqs + 1, |
| 10474 | LaneBitmask(0x00000000000FE008), |
| 10475 | 0, |
| 10476 | true, /* HasDisjunctSubRegs */ |
| 10477 | true, /* CoveredBySubRegs */ |
| 10478 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10479 | nullptr |
| 10480 | }; |
| 10481 | |
| 10482 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10483 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10484 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10485 | SuperRegIdxSeqs + 1, |
| 10486 | LaneBitmask(0x00000000000FE008), |
| 10487 | 0, |
| 10488 | true, /* HasDisjunctSubRegs */ |
| 10489 | true, /* CoveredBySubRegs */ |
| 10490 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10491 | nullptr |
| 10492 | }; |
| 10493 | |
| 10494 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10495 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10496 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10497 | SuperRegIdxSeqs + 1, |
| 10498 | LaneBitmask(0x00000000000FE008), |
| 10499 | 0, |
| 10500 | true, /* HasDisjunctSubRegs */ |
| 10501 | true, /* CoveredBySubRegs */ |
| 10502 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10503 | nullptr |
| 10504 | }; |
| 10505 | |
| 10506 | extern const TargetRegisterClass GPR64argRegClass = { |
| 10507 | &AArch64MCRegisterClasses[GPR64argRegClassID], |
| 10508 | GPR64argSubClassMask, |
| 10509 | SuperRegIdxSeqs + 2, |
| 10510 | LaneBitmask(0x0000000000000008), |
| 10511 | 0, |
| 10512 | false, /* HasDisjunctSubRegs */ |
| 10513 | false, /* CoveredBySubRegs */ |
| 10514 | GPR64argSuperclasses, |
| 10515 | nullptr |
| 10516 | }; |
| 10517 | |
| 10518 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass = { |
| 10519 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClassID], |
| 10520 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSubClassMask, |
| 10521 | SuperRegIdxSeqs + 1, |
| 10522 | LaneBitmask(0x00000000000FE008), |
| 10523 | 0, |
| 10524 | true, /* HasDisjunctSubRegs */ |
| 10525 | true, /* CoveredBySubRegs */ |
| 10526 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipSuperclasses, |
| 10527 | nullptr |
| 10528 | }; |
| 10529 | |
| 10530 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10531 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10532 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10533 | SuperRegIdxSeqs + 1, |
| 10534 | LaneBitmask(0x00000000000FE008), |
| 10535 | 0, |
| 10536 | true, /* HasDisjunctSubRegs */ |
| 10537 | true, /* CoveredBySubRegs */ |
| 10538 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10539 | nullptr |
| 10540 | }; |
| 10541 | |
| 10542 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10543 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10544 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10545 | SuperRegIdxSeqs + 1, |
| 10546 | LaneBitmask(0x00000000000FE008), |
| 10547 | 0, |
| 10548 | true, /* HasDisjunctSubRegs */ |
| 10549 | true, /* CoveredBySubRegs */ |
| 10550 | GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10551 | nullptr |
| 10552 | }; |
| 10553 | |
| 10554 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass = { |
| 10555 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClassID], |
| 10556 | GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10557 | SuperRegIdxSeqs + 1, |
| 10558 | LaneBitmask(0x00000000000FE008), |
| 10559 | 0, |
| 10560 | true, /* HasDisjunctSubRegs */ |
| 10561 | true, /* CoveredBySubRegs */ |
| 10562 | GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64Superclasses, |
| 10563 | nullptr |
| 10564 | }; |
| 10565 | |
| 10566 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10567 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10568 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10569 | SuperRegIdxSeqs + 1, |
| 10570 | LaneBitmask(0x00000000000FE008), |
| 10571 | 0, |
| 10572 | true, /* HasDisjunctSubRegs */ |
| 10573 | true, /* CoveredBySubRegs */ |
| 10574 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10575 | nullptr |
| 10576 | }; |
| 10577 | |
| 10578 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10579 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10580 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10581 | SuperRegIdxSeqs + 1, |
| 10582 | LaneBitmask(0x00000000000FE008), |
| 10583 | 0, |
| 10584 | true, /* HasDisjunctSubRegs */ |
| 10585 | true, /* CoveredBySubRegs */ |
| 10586 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10587 | nullptr |
| 10588 | }; |
| 10589 | |
| 10590 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10591 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10592 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10593 | SuperRegIdxSeqs + 1, |
| 10594 | LaneBitmask(0x00000000000FE008), |
| 10595 | 0, |
| 10596 | true, /* HasDisjunctSubRegs */ |
| 10597 | true, /* CoveredBySubRegs */ |
| 10598 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10599 | nullptr |
| 10600 | }; |
| 10601 | |
| 10602 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10603 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10604 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10605 | SuperRegIdxSeqs + 1, |
| 10606 | LaneBitmask(0x00000000000FE008), |
| 10607 | 0, |
| 10608 | true, /* HasDisjunctSubRegs */ |
| 10609 | true, /* CoveredBySubRegs */ |
| 10610 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10611 | nullptr |
| 10612 | }; |
| 10613 | |
| 10614 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass = { |
| 10615 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClassID], |
| 10616 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10617 | SuperRegIdxSeqs + 1, |
| 10618 | LaneBitmask(0x00000000000FE008), |
| 10619 | 0, |
| 10620 | true, /* HasDisjunctSubRegs */ |
| 10621 | true, /* CoveredBySubRegs */ |
| 10622 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64Superclasses, |
| 10623 | nullptr |
| 10624 | }; |
| 10625 | |
| 10626 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10627 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10628 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10629 | SuperRegIdxSeqs + 1, |
| 10630 | LaneBitmask(0x00000000000FE008), |
| 10631 | 0, |
| 10632 | true, /* HasDisjunctSubRegs */ |
| 10633 | true, /* CoveredBySubRegs */ |
| 10634 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10635 | nullptr |
| 10636 | }; |
| 10637 | |
| 10638 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10639 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10640 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10641 | SuperRegIdxSeqs + 1, |
| 10642 | LaneBitmask(0x00000000000FE008), |
| 10643 | 0, |
| 10644 | true, /* HasDisjunctSubRegs */ |
| 10645 | true, /* CoveredBySubRegs */ |
| 10646 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10647 | nullptr |
| 10648 | }; |
| 10649 | |
| 10650 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10651 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10652 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10653 | SuperRegIdxSeqs + 1, |
| 10654 | LaneBitmask(0x00000000000FE008), |
| 10655 | 0, |
| 10656 | true, /* HasDisjunctSubRegs */ |
| 10657 | true, /* CoveredBySubRegs */ |
| 10658 | GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10659 | nullptr |
| 10660 | }; |
| 10661 | |
| 10662 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10663 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10664 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10665 | SuperRegIdxSeqs + 1, |
| 10666 | LaneBitmask(0x00000000000FE008), |
| 10667 | 0, |
| 10668 | true, /* HasDisjunctSubRegs */ |
| 10669 | true, /* CoveredBySubRegs */ |
| 10670 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10671 | nullptr |
| 10672 | }; |
| 10673 | |
| 10674 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10675 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10676 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10677 | SuperRegIdxSeqs + 1, |
| 10678 | LaneBitmask(0x00000000000FE008), |
| 10679 | 0, |
| 10680 | true, /* HasDisjunctSubRegs */ |
| 10681 | true, /* CoveredBySubRegs */ |
| 10682 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10683 | nullptr |
| 10684 | }; |
| 10685 | |
| 10686 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass = { |
| 10687 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClassID], |
| 10688 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSubClassMask, |
| 10689 | SuperRegIdxSeqs + 1, |
| 10690 | LaneBitmask(0x00000000000FE008), |
| 10691 | 0, |
| 10692 | true, /* HasDisjunctSubRegs */ |
| 10693 | true, /* CoveredBySubRegs */ |
| 10694 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipSuperclasses, |
| 10695 | nullptr |
| 10696 | }; |
| 10697 | |
| 10698 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10699 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10700 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10701 | SuperRegIdxSeqs + 1, |
| 10702 | LaneBitmask(0x00000000000FE008), |
| 10703 | 0, |
| 10704 | true, /* HasDisjunctSubRegs */ |
| 10705 | true, /* CoveredBySubRegs */ |
| 10706 | GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10707 | nullptr |
| 10708 | }; |
| 10709 | |
| 10710 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass = { |
| 10711 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClassID], |
| 10712 | GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10713 | SuperRegIdxSeqs + 1, |
| 10714 | LaneBitmask(0x00000000000FE008), |
| 10715 | 0, |
| 10716 | true, /* HasDisjunctSubRegs */ |
| 10717 | true, /* CoveredBySubRegs */ |
| 10718 | GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64Superclasses, |
| 10719 | nullptr |
| 10720 | }; |
| 10721 | |
| 10722 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10723 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10724 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10725 | SuperRegIdxSeqs + 1, |
| 10726 | LaneBitmask(0x00000000000FE008), |
| 10727 | 0, |
| 10728 | true, /* HasDisjunctSubRegs */ |
| 10729 | true, /* CoveredBySubRegs */ |
| 10730 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10731 | nullptr |
| 10732 | }; |
| 10733 | |
| 10734 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10735 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10736 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10737 | SuperRegIdxSeqs + 1, |
| 10738 | LaneBitmask(0x00000000000FE008), |
| 10739 | 0, |
| 10740 | true, /* HasDisjunctSubRegs */ |
| 10741 | true, /* CoveredBySubRegs */ |
| 10742 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10743 | nullptr |
| 10744 | }; |
| 10745 | |
| 10746 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10747 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10748 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10749 | SuperRegIdxSeqs + 1, |
| 10750 | LaneBitmask(0x00000000000FE008), |
| 10751 | 0, |
| 10752 | true, /* HasDisjunctSubRegs */ |
| 10753 | true, /* CoveredBySubRegs */ |
| 10754 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10755 | nullptr |
| 10756 | }; |
| 10757 | |
| 10758 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass = { |
| 10759 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClassID], |
| 10760 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10761 | SuperRegIdxSeqs + 1, |
| 10762 | LaneBitmask(0x00000000000FE008), |
| 10763 | 0, |
| 10764 | true, /* HasDisjunctSubRegs */ |
| 10765 | true, /* CoveredBySubRegs */ |
| 10766 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64Superclasses, |
| 10767 | nullptr |
| 10768 | }; |
| 10769 | |
| 10770 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10771 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10772 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10773 | SuperRegIdxSeqs + 1, |
| 10774 | LaneBitmask(0x00000000000FE008), |
| 10775 | 0, |
| 10776 | true, /* HasDisjunctSubRegs */ |
| 10777 | true, /* CoveredBySubRegs */ |
| 10778 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10779 | nullptr |
| 10780 | }; |
| 10781 | |
| 10782 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10783 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10784 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10785 | SuperRegIdxSeqs + 1, |
| 10786 | LaneBitmask(0x00000000000FE008), |
| 10787 | 0, |
| 10788 | true, /* HasDisjunctSubRegs */ |
| 10789 | true, /* CoveredBySubRegs */ |
| 10790 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10791 | nullptr |
| 10792 | }; |
| 10793 | |
| 10794 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass = { |
| 10795 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClassID], |
| 10796 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSubClassMask, |
| 10797 | SuperRegIdxSeqs + 1, |
| 10798 | LaneBitmask(0x00000000000FE008), |
| 10799 | 0, |
| 10800 | true, /* HasDisjunctSubRegs */ |
| 10801 | true, /* CoveredBySubRegs */ |
| 10802 | GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipSuperclasses, |
| 10803 | nullptr |
| 10804 | }; |
| 10805 | |
| 10806 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass = { |
| 10807 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClassID], |
| 10808 | GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10809 | SuperRegIdxSeqs + 1, |
| 10810 | LaneBitmask(0x00000000000FE008), |
| 10811 | 0, |
| 10812 | true, /* HasDisjunctSubRegs */ |
| 10813 | true, /* CoveredBySubRegs */ |
| 10814 | GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64Superclasses, |
| 10815 | nullptr |
| 10816 | }; |
| 10817 | |
| 10818 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass = { |
| 10819 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClassID], |
| 10820 | GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10821 | SuperRegIdxSeqs + 1, |
| 10822 | LaneBitmask(0x00000000000FE008), |
| 10823 | 0, |
| 10824 | true, /* HasDisjunctSubRegs */ |
| 10825 | true, /* CoveredBySubRegs */ |
| 10826 | GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64Superclasses, |
| 10827 | nullptr |
| 10828 | }; |
| 10829 | |
| 10830 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass = { |
| 10831 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClassID], |
| 10832 | GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64SubClassMask, |
| 10833 | SuperRegIdxSeqs + 1, |
| 10834 | LaneBitmask(0x00000000000FE008), |
| 10835 | 0, |
| 10836 | true, /* HasDisjunctSubRegs */ |
| 10837 | true, /* CoveredBySubRegs */ |
| 10838 | GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64Superclasses, |
| 10839 | nullptr |
| 10840 | }; |
| 10841 | |
| 10842 | extern const TargetRegisterClass GPR64x8Class_with_sub_32_in_GPR32argRegClass = { |
| 10843 | &AArch64MCRegisterClasses[GPR64x8Class_with_sub_32_in_GPR32argRegClassID], |
| 10844 | GPR64x8Class_with_sub_32_in_GPR32argSubClassMask, |
| 10845 | SuperRegIdxSeqs + 1, |
| 10846 | LaneBitmask(0x00000000000FE008), |
| 10847 | 0, |
| 10848 | true, /* HasDisjunctSubRegs */ |
| 10849 | true, /* CoveredBySubRegs */ |
| 10850 | GPR64x8Class_with_sub_32_in_GPR32argSuperclasses, |
| 10851 | nullptr |
| 10852 | }; |
| 10853 | |
| 10854 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_GPR64argRegClass = { |
| 10855 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_GPR64argRegClassID], |
| 10856 | GPR64x8Class_with_x8sub_2_in_GPR64argSubClassMask, |
| 10857 | SuperRegIdxSeqs + 1, |
| 10858 | LaneBitmask(0x00000000000FE008), |
| 10859 | 0, |
| 10860 | true, /* HasDisjunctSubRegs */ |
| 10861 | true, /* CoveredBySubRegs */ |
| 10862 | GPR64x8Class_with_x8sub_2_in_GPR64argSuperclasses, |
| 10863 | nullptr |
| 10864 | }; |
| 10865 | |
| 10866 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_GPR64argRegClass = { |
| 10867 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_GPR64argRegClassID], |
| 10868 | GPR64x8Class_with_x8sub_4_in_GPR64argSubClassMask, |
| 10869 | SuperRegIdxSeqs + 1, |
| 10870 | LaneBitmask(0x00000000000FE008), |
| 10871 | 0, |
| 10872 | true, /* HasDisjunctSubRegs */ |
| 10873 | true, /* CoveredBySubRegs */ |
| 10874 | GPR64x8Class_with_x8sub_4_in_GPR64argSuperclasses, |
| 10875 | nullptr |
| 10876 | }; |
| 10877 | |
| 10878 | extern const TargetRegisterClass rtcGPR64RegClass = { |
| 10879 | &AArch64MCRegisterClasses[rtcGPR64RegClassID], |
| 10880 | rtcGPR64SubClassMask, |
| 10881 | SuperRegIdxSeqs + 2, |
| 10882 | LaneBitmask(0x0000000000000008), |
| 10883 | 0, |
| 10884 | false, /* HasDisjunctSubRegs */ |
| 10885 | false, /* CoveredBySubRegs */ |
| 10886 | rtcGPR64Superclasses, |
| 10887 | nullptr |
| 10888 | }; |
| 10889 | |
| 10890 | extern const TargetRegisterClass GPR64sponlyRegClass = { |
| 10891 | &AArch64MCRegisterClasses[GPR64sponlyRegClassID], |
| 10892 | GPR64sponlySubClassMask, |
| 10893 | SuperRegIdxSeqs + 1, |
| 10894 | LaneBitmask(0x0000000000000008), |
| 10895 | 0, |
| 10896 | false, /* HasDisjunctSubRegs */ |
| 10897 | false, /* CoveredBySubRegs */ |
| 10898 | GPR64sponlySuperclasses, |
| 10899 | nullptr |
| 10900 | }; |
| 10901 | |
| 10902 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClass = { |
| 10903 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClassID], |
| 10904 | GPR64x8Class_with_x8sub_0_in_rtcGPR64SubClassMask, |
| 10905 | SuperRegIdxSeqs + 1, |
| 10906 | LaneBitmask(0x00000000000FE008), |
| 10907 | 0, |
| 10908 | true, /* HasDisjunctSubRegs */ |
| 10909 | true, /* CoveredBySubRegs */ |
| 10910 | GPR64x8Class_with_x8sub_0_in_rtcGPR64Superclasses, |
| 10911 | nullptr |
| 10912 | }; |
| 10913 | |
| 10914 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClass = { |
| 10915 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClassID], |
| 10916 | GPR64x8Class_with_x8sub_2_in_rtcGPR64SubClassMask, |
| 10917 | SuperRegIdxSeqs + 1, |
| 10918 | LaneBitmask(0x00000000000FE008), |
| 10919 | 0, |
| 10920 | true, /* HasDisjunctSubRegs */ |
| 10921 | true, /* CoveredBySubRegs */ |
| 10922 | GPR64x8Class_with_x8sub_2_in_rtcGPR64Superclasses, |
| 10923 | nullptr |
| 10924 | }; |
| 10925 | |
| 10926 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClass = { |
| 10927 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClassID], |
| 10928 | GPR64x8Class_with_x8sub_4_in_rtcGPR64SubClassMask, |
| 10929 | SuperRegIdxSeqs + 1, |
| 10930 | LaneBitmask(0x00000000000FE008), |
| 10931 | 0, |
| 10932 | true, /* HasDisjunctSubRegs */ |
| 10933 | true, /* CoveredBySubRegs */ |
| 10934 | GPR64x8Class_with_x8sub_4_in_rtcGPR64Superclasses, |
| 10935 | nullptr |
| 10936 | }; |
| 10937 | |
| 10938 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_GPR64argRegClass = { |
| 10939 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_6_in_GPR64argRegClassID], |
| 10940 | GPR64x8Class_with_x8sub_6_in_GPR64argSubClassMask, |
| 10941 | SuperRegIdxSeqs + 1, |
| 10942 | LaneBitmask(0x00000000000FE008), |
| 10943 | 0, |
| 10944 | true, /* HasDisjunctSubRegs */ |
| 10945 | true, /* CoveredBySubRegs */ |
| 10946 | GPR64x8Class_with_x8sub_6_in_GPR64argSuperclasses, |
| 10947 | nullptr |
| 10948 | }; |
| 10949 | |
| 10950 | extern const TargetRegisterClass GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClass = { |
| 10951 | &AArch64MCRegisterClasses[GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClassID], |
| 10952 | GPR64x8Class_with_x8sub_6_in_rtcGPR64SubClassMask, |
| 10953 | SuperRegIdxSeqs + 1, |
| 10954 | LaneBitmask(0x00000000000FE008), |
| 10955 | 0, |
| 10956 | true, /* HasDisjunctSubRegs */ |
| 10957 | true, /* CoveredBySubRegs */ |
| 10958 | GPR64x8Class_with_x8sub_6_in_rtcGPR64Superclasses, |
| 10959 | nullptr |
| 10960 | }; |
| 10961 | |
| 10962 | extern const TargetRegisterClass DDRegClass = { |
| 10963 | &AArch64MCRegisterClasses[DDRegClassID], |
| 10964 | DDSubClassMask, |
| 10965 | SuperRegIdxSeqs + 119, |
| 10966 | LaneBitmask(0x0000000000000081), |
| 10967 | 0, |
| 10968 | true, /* HasDisjunctSubRegs */ |
| 10969 | true, /* CoveredBySubRegs */ |
| 10970 | NullRegClasses, |
| 10971 | nullptr |
| 10972 | }; |
| 10973 | |
| 10974 | extern const TargetRegisterClass DD_with_dsub0_in_FPR64_loRegClass = { |
| 10975 | &AArch64MCRegisterClasses[DD_with_dsub0_in_FPR64_loRegClassID], |
| 10976 | DD_with_dsub0_in_FPR64_loSubClassMask, |
| 10977 | SuperRegIdxSeqs + 119, |
| 10978 | LaneBitmask(0x0000000000000081), |
| 10979 | 0, |
| 10980 | true, /* HasDisjunctSubRegs */ |
| 10981 | true, /* CoveredBySubRegs */ |
| 10982 | DD_with_dsub0_in_FPR64_loSuperclasses, |
| 10983 | nullptr |
| 10984 | }; |
| 10985 | |
| 10986 | extern const TargetRegisterClass DD_with_dsub1_in_FPR64_loRegClass = { |
| 10987 | &AArch64MCRegisterClasses[DD_with_dsub1_in_FPR64_loRegClassID], |
| 10988 | DD_with_dsub1_in_FPR64_loSubClassMask, |
| 10989 | SuperRegIdxSeqs + 119, |
| 10990 | LaneBitmask(0x0000000000000081), |
| 10991 | 0, |
| 10992 | true, /* HasDisjunctSubRegs */ |
| 10993 | true, /* CoveredBySubRegs */ |
| 10994 | DD_with_dsub1_in_FPR64_loSuperclasses, |
| 10995 | nullptr |
| 10996 | }; |
| 10997 | |
| 10998 | extern const TargetRegisterClass XSeqPairsClassRegClass = { |
| 10999 | &AArch64MCRegisterClasses[XSeqPairsClassRegClassID], |
| 11000 | XSeqPairsClassSubClassMask, |
| 11001 | SuperRegIdxSeqs + 84, |
| 11002 | LaneBitmask(0x0000000000100008), |
| 11003 | 0, |
| 11004 | true, /* HasDisjunctSubRegs */ |
| 11005 | true, /* CoveredBySubRegs */ |
| 11006 | NullRegClasses, |
| 11007 | nullptr |
| 11008 | }; |
| 11009 | |
| 11010 | extern const TargetRegisterClass DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClass = { |
| 11011 | &AArch64MCRegisterClasses[DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClassID], |
| 11012 | DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loSubClassMask, |
| 11013 | SuperRegIdxSeqs + 119, |
| 11014 | LaneBitmask(0x0000000000000081), |
| 11015 | 0, |
| 11016 | true, /* HasDisjunctSubRegs */ |
| 11017 | true, /* CoveredBySubRegs */ |
| 11018 | DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loSuperclasses, |
| 11019 | nullptr |
| 11020 | }; |
| 11021 | |
| 11022 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = { |
| 11023 | &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64commonRegClassID], |
| 11024 | XSeqPairsClass_with_subo64_in_GPR64commonSubClassMask, |
| 11025 | SuperRegIdxSeqs + 84, |
| 11026 | LaneBitmask(0x0000000000100008), |
| 11027 | 0, |
| 11028 | true, /* HasDisjunctSubRegs */ |
| 11029 | true, /* CoveredBySubRegs */ |
| 11030 | XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses, |
| 11031 | nullptr |
| 11032 | }; |
| 11033 | |
| 11034 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass = { |
| 11035 | &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64noipRegClassID], |
| 11036 | XSeqPairsClass_with_subo64_in_GPR64noipSubClassMask, |
| 11037 | SuperRegIdxSeqs + 84, |
| 11038 | LaneBitmask(0x0000000000100008), |
| 11039 | 0, |
| 11040 | true, /* HasDisjunctSubRegs */ |
| 11041 | true, /* CoveredBySubRegs */ |
| 11042 | XSeqPairsClass_with_subo64_in_GPR64noipSuperclasses, |
| 11043 | nullptr |
| 11044 | }; |
| 11045 | |
| 11046 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass = { |
| 11047 | &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_GPR64noipRegClassID], |
| 11048 | XSeqPairsClass_with_sube64_in_GPR64noipSubClassMask, |
| 11049 | SuperRegIdxSeqs + 84, |
| 11050 | LaneBitmask(0x0000000000100008), |
| 11051 | 0, |
| 11052 | true, /* HasDisjunctSubRegs */ |
| 11053 | true, /* CoveredBySubRegs */ |
| 11054 | XSeqPairsClass_with_sube64_in_GPR64noipSuperclasses, |
| 11055 | nullptr |
| 11056 | }; |
| 11057 | |
| 11058 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = { |
| 11059 | &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_tcGPR64RegClassID], |
| 11060 | XSeqPairsClass_with_sube64_in_tcGPR64SubClassMask, |
| 11061 | SuperRegIdxSeqs + 84, |
| 11062 | LaneBitmask(0x0000000000100008), |
| 11063 | 0, |
| 11064 | true, /* HasDisjunctSubRegs */ |
| 11065 | true, /* CoveredBySubRegs */ |
| 11066 | XSeqPairsClass_with_sube64_in_tcGPR64Superclasses, |
| 11067 | nullptr |
| 11068 | }; |
| 11069 | |
| 11070 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass = { |
| 11071 | &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClassID], |
| 11072 | XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64SubClassMask, |
| 11073 | SuperRegIdxSeqs + 84, |
| 11074 | LaneBitmask(0x0000000000100008), |
| 11075 | 0, |
| 11076 | true, /* HasDisjunctSubRegs */ |
| 11077 | true, /* CoveredBySubRegs */ |
| 11078 | XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Superclasses, |
| 11079 | nullptr |
| 11080 | }; |
| 11081 | |
| 11082 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = { |
| 11083 | &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_tcGPR64RegClassID], |
| 11084 | XSeqPairsClass_with_subo64_in_tcGPR64SubClassMask, |
| 11085 | SuperRegIdxSeqs + 84, |
| 11086 | LaneBitmask(0x0000000000100008), |
| 11087 | 0, |
| 11088 | true, /* HasDisjunctSubRegs */ |
| 11089 | true, /* CoveredBySubRegs */ |
| 11090 | XSeqPairsClass_with_subo64_in_tcGPR64Superclasses, |
| 11091 | nullptr |
| 11092 | }; |
| 11093 | |
| 11094 | extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass = { |
| 11095 | &AArch64MCRegisterClasses[XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClassID], |
| 11096 | XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64SubClassMask, |
| 11097 | SuperRegIdxSeqs + 84, |
| 11098 | LaneBitmask(0x0000000000100008), |
| 11099 | 0, |
| 11100 | true, /* HasDisjunctSubRegs */ |
| 11101 | true, /* CoveredBySubRegs */ |
| 11102 | XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Superclasses, |
| 11103 | nullptr |
| 11104 | }; |
| 11105 | |
| 11106 | extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass = { |
| 11107 | &AArch64MCRegisterClasses[XSeqPairsClass_with_sub_32_in_GPR32argRegClassID], |
| 11108 | XSeqPairsClass_with_sub_32_in_GPR32argSubClassMask, |
| 11109 | SuperRegIdxSeqs + 84, |
| 11110 | LaneBitmask(0x0000000000100008), |
| 11111 | 0, |
| 11112 | true, /* HasDisjunctSubRegs */ |
| 11113 | true, /* CoveredBySubRegs */ |
| 11114 | XSeqPairsClass_with_sub_32_in_GPR32argSuperclasses, |
| 11115 | nullptr |
| 11116 | }; |
| 11117 | |
| 11118 | extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass = { |
| 11119 | &AArch64MCRegisterClasses[XSeqPairsClass_with_sube64_in_rtcGPR64RegClassID], |
| 11120 | XSeqPairsClass_with_sube64_in_rtcGPR64SubClassMask, |
| 11121 | SuperRegIdxSeqs + 84, |
| 11122 | LaneBitmask(0x0000000000100008), |
| 11123 | 0, |
| 11124 | true, /* HasDisjunctSubRegs */ |
| 11125 | true, /* CoveredBySubRegs */ |
| 11126 | XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses, |
| 11127 | nullptr |
| 11128 | }; |
| 11129 | |
| 11130 | extern const TargetRegisterClass FPR128RegClass = { |
| 11131 | &AArch64MCRegisterClasses[FPR128RegClassID], |
| 11132 | FPR128SubClassMask, |
| 11133 | SuperRegIdxSeqs + 75, |
| 11134 | LaneBitmask(0x0000000000000001), |
| 11135 | 0, |
| 11136 | false, /* HasDisjunctSubRegs */ |
| 11137 | false, /* CoveredBySubRegs */ |
| 11138 | NullRegClasses, |
| 11139 | nullptr |
| 11140 | }; |
| 11141 | |
| 11142 | extern const TargetRegisterClass ZPRRegClass = { |
| 11143 | &AArch64MCRegisterClasses[ZPRRegClassID], |
| 11144 | ZPRSubClassMask, |
| 11145 | SuperRegIdxSeqs + 13, |
| 11146 | LaneBitmask(0x0000000000000041), |
| 11147 | 0, |
| 11148 | true, /* HasDisjunctSubRegs */ |
| 11149 | false, /* CoveredBySubRegs */ |
| 11150 | NullRegClasses, |
| 11151 | nullptr |
| 11152 | }; |
| 11153 | |
| 11154 | extern const TargetRegisterClass FPR128_loRegClass = { |
| 11155 | &AArch64MCRegisterClasses[FPR128_loRegClassID], |
| 11156 | FPR128_loSubClassMask, |
| 11157 | SuperRegIdxSeqs + 75, |
| 11158 | LaneBitmask(0x0000000000000001), |
| 11159 | 0, |
| 11160 | false, /* HasDisjunctSubRegs */ |
| 11161 | false, /* CoveredBySubRegs */ |
| 11162 | FPR128_loSuperclasses, |
| 11163 | nullptr |
| 11164 | }; |
| 11165 | |
| 11166 | extern const TargetRegisterClass ZPR_4bRegClass = { |
| 11167 | &AArch64MCRegisterClasses[ZPR_4bRegClassID], |
| 11168 | ZPR_4bSubClassMask, |
| 11169 | SuperRegIdxSeqs + 13, |
| 11170 | LaneBitmask(0x0000000000000041), |
| 11171 | 0, |
| 11172 | true, /* HasDisjunctSubRegs */ |
| 11173 | false, /* CoveredBySubRegs */ |
| 11174 | ZPR_4bSuperclasses, |
| 11175 | nullptr |
| 11176 | }; |
| 11177 | |
| 11178 | extern const TargetRegisterClass ZPR_3bRegClass = { |
| 11179 | &AArch64MCRegisterClasses[ZPR_3bRegClassID], |
| 11180 | ZPR_3bSubClassMask, |
| 11181 | SuperRegIdxSeqs + 13, |
| 11182 | LaneBitmask(0x0000000000000041), |
| 11183 | 0, |
| 11184 | true, /* HasDisjunctSubRegs */ |
| 11185 | false, /* CoveredBySubRegs */ |
| 11186 | ZPR_3bSuperclasses, |
| 11187 | nullptr |
| 11188 | }; |
| 11189 | |
| 11190 | extern const TargetRegisterClass DDDRegClass = { |
| 11191 | &AArch64MCRegisterClasses[DDDRegClassID], |
| 11192 | DDDSubClassMask, |
| 11193 | SuperRegIdxSeqs + 107, |
| 11194 | LaneBitmask(0x0000000000000281), |
| 11195 | 0, |
| 11196 | true, /* HasDisjunctSubRegs */ |
| 11197 | true, /* CoveredBySubRegs */ |
| 11198 | NullRegClasses, |
| 11199 | nullptr |
| 11200 | }; |
| 11201 | |
| 11202 | extern const TargetRegisterClass DDD_with_dsub0_in_FPR64_loRegClass = { |
| 11203 | &AArch64MCRegisterClasses[DDD_with_dsub0_in_FPR64_loRegClassID], |
| 11204 | DDD_with_dsub0_in_FPR64_loSubClassMask, |
| 11205 | SuperRegIdxSeqs + 107, |
| 11206 | LaneBitmask(0x0000000000000281), |
| 11207 | 0, |
| 11208 | true, /* HasDisjunctSubRegs */ |
| 11209 | true, /* CoveredBySubRegs */ |
| 11210 | DDD_with_dsub0_in_FPR64_loSuperclasses, |
| 11211 | nullptr |
| 11212 | }; |
| 11213 | |
| 11214 | extern const TargetRegisterClass DDD_with_dsub1_in_FPR64_loRegClass = { |
| 11215 | &AArch64MCRegisterClasses[DDD_with_dsub1_in_FPR64_loRegClassID], |
| 11216 | DDD_with_dsub1_in_FPR64_loSubClassMask, |
| 11217 | SuperRegIdxSeqs + 107, |
| 11218 | LaneBitmask(0x0000000000000281), |
| 11219 | 0, |
| 11220 | true, /* HasDisjunctSubRegs */ |
| 11221 | true, /* CoveredBySubRegs */ |
| 11222 | DDD_with_dsub1_in_FPR64_loSuperclasses, |
| 11223 | nullptr |
| 11224 | }; |
| 11225 | |
| 11226 | extern const TargetRegisterClass DDD_with_dsub2_in_FPR64_loRegClass = { |
| 11227 | &AArch64MCRegisterClasses[DDD_with_dsub2_in_FPR64_loRegClassID], |
| 11228 | DDD_with_dsub2_in_FPR64_loSubClassMask, |
| 11229 | SuperRegIdxSeqs + 107, |
| 11230 | LaneBitmask(0x0000000000000281), |
| 11231 | 0, |
| 11232 | true, /* HasDisjunctSubRegs */ |
| 11233 | true, /* CoveredBySubRegs */ |
| 11234 | DDD_with_dsub2_in_FPR64_loSuperclasses, |
| 11235 | nullptr |
| 11236 | }; |
| 11237 | |
| 11238 | extern const TargetRegisterClass DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClass = { |
| 11239 | &AArch64MCRegisterClasses[DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClassID], |
| 11240 | DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loSubClassMask, |
| 11241 | SuperRegIdxSeqs + 107, |
| 11242 | LaneBitmask(0x0000000000000281), |
| 11243 | 0, |
| 11244 | true, /* HasDisjunctSubRegs */ |
| 11245 | true, /* CoveredBySubRegs */ |
| 11246 | DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loSuperclasses, |
| 11247 | nullptr |
| 11248 | }; |
| 11249 | |
| 11250 | extern const TargetRegisterClass DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass = { |
| 11251 | &AArch64MCRegisterClasses[DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID], |
| 11252 | DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSubClassMask, |
| 11253 | SuperRegIdxSeqs + 107, |
| 11254 | LaneBitmask(0x0000000000000281), |
| 11255 | 0, |
| 11256 | true, /* HasDisjunctSubRegs */ |
| 11257 | true, /* CoveredBySubRegs */ |
| 11258 | DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSuperclasses, |
| 11259 | nullptr |
| 11260 | }; |
| 11261 | |
| 11262 | extern const TargetRegisterClass DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass = { |
| 11263 | &AArch64MCRegisterClasses[DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClassID], |
| 11264 | DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSubClassMask, |
| 11265 | SuperRegIdxSeqs + 107, |
| 11266 | LaneBitmask(0x0000000000000281), |
| 11267 | 0, |
| 11268 | true, /* HasDisjunctSubRegs */ |
| 11269 | true, /* CoveredBySubRegs */ |
| 11270 | DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loSuperclasses, |
| 11271 | nullptr |
| 11272 | }; |
| 11273 | |
| 11274 | extern const TargetRegisterClass DDDDRegClass = { |
| 11275 | &AArch64MCRegisterClasses[DDDDRegClassID], |
| 11276 | DDDDSubClassMask, |
| 11277 | SuperRegIdxSeqs + 95, |
| 11278 | LaneBitmask(0x0000000000000381), |
| 11279 | 0, |
| 11280 | true, /* HasDisjunctSubRegs */ |
| 11281 | true, /* CoveredBySubRegs */ |
| 11282 | NullRegClasses, |
| 11283 | nullptr |
| 11284 | }; |
| 11285 | |
| 11286 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_loRegClass = { |
| 11287 | &AArch64MCRegisterClasses[DDDD_with_dsub0_in_FPR64_loRegClassID], |
| 11288 | DDDD_with_dsub0_in_FPR64_loSubClassMask, |
| 11289 | SuperRegIdxSeqs + 95, |
| 11290 | LaneBitmask(0x0000000000000381), |
| 11291 | 0, |
| 11292 | true, /* HasDisjunctSubRegs */ |
| 11293 | true, /* CoveredBySubRegs */ |
| 11294 | DDDD_with_dsub0_in_FPR64_loSuperclasses, |
| 11295 | nullptr |
| 11296 | }; |
| 11297 | |
| 11298 | extern const TargetRegisterClass DDDD_with_dsub1_in_FPR64_loRegClass = { |
| 11299 | &AArch64MCRegisterClasses[DDDD_with_dsub1_in_FPR64_loRegClassID], |
| 11300 | DDDD_with_dsub1_in_FPR64_loSubClassMask, |
| 11301 | SuperRegIdxSeqs + 95, |
| 11302 | LaneBitmask(0x0000000000000381), |
| 11303 | 0, |
| 11304 | true, /* HasDisjunctSubRegs */ |
| 11305 | true, /* CoveredBySubRegs */ |
| 11306 | DDDD_with_dsub1_in_FPR64_loSuperclasses, |
| 11307 | nullptr |
| 11308 | }; |
| 11309 | |
| 11310 | extern const TargetRegisterClass DDDD_with_dsub2_in_FPR64_loRegClass = { |
| 11311 | &AArch64MCRegisterClasses[DDDD_with_dsub2_in_FPR64_loRegClassID], |
| 11312 | DDDD_with_dsub2_in_FPR64_loSubClassMask, |
| 11313 | SuperRegIdxSeqs + 95, |
| 11314 | LaneBitmask(0x0000000000000381), |
| 11315 | 0, |
| 11316 | true, /* HasDisjunctSubRegs */ |
| 11317 | true, /* CoveredBySubRegs */ |
| 11318 | DDDD_with_dsub2_in_FPR64_loSuperclasses, |
| 11319 | nullptr |
| 11320 | }; |
| 11321 | |
| 11322 | extern const TargetRegisterClass DDDD_with_dsub3_in_FPR64_loRegClass = { |
| 11323 | &AArch64MCRegisterClasses[DDDD_with_dsub3_in_FPR64_loRegClassID], |
| 11324 | DDDD_with_dsub3_in_FPR64_loSubClassMask, |
| 11325 | SuperRegIdxSeqs + 95, |
| 11326 | LaneBitmask(0x0000000000000381), |
| 11327 | 0, |
| 11328 | true, /* HasDisjunctSubRegs */ |
| 11329 | true, /* CoveredBySubRegs */ |
| 11330 | DDDD_with_dsub3_in_FPR64_loSuperclasses, |
| 11331 | nullptr |
| 11332 | }; |
| 11333 | |
| 11334 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClass = { |
| 11335 | &AArch64MCRegisterClasses[DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClassID], |
| 11336 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loSubClassMask, |
| 11337 | SuperRegIdxSeqs + 95, |
| 11338 | LaneBitmask(0x0000000000000381), |
| 11339 | 0, |
| 11340 | true, /* HasDisjunctSubRegs */ |
| 11341 | true, /* CoveredBySubRegs */ |
| 11342 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loSuperclasses, |
| 11343 | nullptr |
| 11344 | }; |
| 11345 | |
| 11346 | extern const TargetRegisterClass DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass = { |
| 11347 | &AArch64MCRegisterClasses[DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID], |
| 11348 | DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSubClassMask, |
| 11349 | SuperRegIdxSeqs + 95, |
| 11350 | LaneBitmask(0x0000000000000381), |
| 11351 | 0, |
| 11352 | true, /* HasDisjunctSubRegs */ |
| 11353 | true, /* CoveredBySubRegs */ |
| 11354 | DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSuperclasses, |
| 11355 | nullptr |
| 11356 | }; |
| 11357 | |
| 11358 | extern const TargetRegisterClass DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass = { |
| 11359 | &AArch64MCRegisterClasses[DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID], |
| 11360 | DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSubClassMask, |
| 11361 | SuperRegIdxSeqs + 95, |
| 11362 | LaneBitmask(0x0000000000000381), |
| 11363 | 0, |
| 11364 | true, /* HasDisjunctSubRegs */ |
| 11365 | true, /* CoveredBySubRegs */ |
| 11366 | DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSuperclasses, |
| 11367 | nullptr |
| 11368 | }; |
| 11369 | |
| 11370 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass = { |
| 11371 | &AArch64MCRegisterClasses[DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClassID], |
| 11372 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSubClassMask, |
| 11373 | SuperRegIdxSeqs + 95, |
| 11374 | LaneBitmask(0x0000000000000381), |
| 11375 | 0, |
| 11376 | true, /* HasDisjunctSubRegs */ |
| 11377 | true, /* CoveredBySubRegs */ |
| 11378 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loSuperclasses, |
| 11379 | nullptr |
| 11380 | }; |
| 11381 | |
| 11382 | extern const TargetRegisterClass DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass = { |
| 11383 | &AArch64MCRegisterClasses[DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID], |
| 11384 | DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSubClassMask, |
| 11385 | SuperRegIdxSeqs + 95, |
| 11386 | LaneBitmask(0x0000000000000381), |
| 11387 | 0, |
| 11388 | true, /* HasDisjunctSubRegs */ |
| 11389 | true, /* CoveredBySubRegs */ |
| 11390 | DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSuperclasses, |
| 11391 | nullptr |
| 11392 | }; |
| 11393 | |
| 11394 | extern const TargetRegisterClass DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass = { |
| 11395 | &AArch64MCRegisterClasses[DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClassID], |
| 11396 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSubClassMask, |
| 11397 | SuperRegIdxSeqs + 95, |
| 11398 | LaneBitmask(0x0000000000000381), |
| 11399 | 0, |
| 11400 | true, /* HasDisjunctSubRegs */ |
| 11401 | true, /* CoveredBySubRegs */ |
| 11402 | DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loSuperclasses, |
| 11403 | nullptr |
| 11404 | }; |
| 11405 | |
| 11406 | extern const TargetRegisterClass QQRegClass = { |
| 11407 | &AArch64MCRegisterClasses[QQRegClassID], |
| 11408 | QQSubClassMask, |
| 11409 | SuperRegIdxSeqs + 129, |
| 11410 | LaneBitmask(0x0000000000000401), |
| 11411 | 0, |
| 11412 | true, /* HasDisjunctSubRegs */ |
| 11413 | true, /* CoveredBySubRegs */ |
| 11414 | NullRegClasses, |
| 11415 | nullptr |
| 11416 | }; |
| 11417 | |
| 11418 | extern const TargetRegisterClass ZPR2RegClass = { |
| 11419 | &AArch64MCRegisterClasses[ZPR2RegClassID], |
| 11420 | ZPR2SubClassMask, |
| 11421 | SuperRegIdxSeqs + 103, |
| 11422 | LaneBitmask(0x0000000000600041), |
| 11423 | 0, |
| 11424 | true, /* HasDisjunctSubRegs */ |
| 11425 | true, /* CoveredBySubRegs */ |
| 11426 | NullRegClasses, |
| 11427 | nullptr |
| 11428 | }; |
| 11429 | |
| 11430 | extern const TargetRegisterClass QQ_with_dsub_in_FPR64_loRegClass = { |
| 11431 | &AArch64MCRegisterClasses[QQ_with_dsub_in_FPR64_loRegClassID], |
| 11432 | QQ_with_dsub_in_FPR64_loSubClassMask, |
| 11433 | SuperRegIdxSeqs + 129, |
| 11434 | LaneBitmask(0x0000000000000401), |
| 11435 | 0, |
| 11436 | true, /* HasDisjunctSubRegs */ |
| 11437 | true, /* CoveredBySubRegs */ |
| 11438 | QQ_with_dsub_in_FPR64_loSuperclasses, |
| 11439 | nullptr |
| 11440 | }; |
| 11441 | |
| 11442 | extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = { |
| 11443 | &AArch64MCRegisterClasses[QQ_with_qsub1_in_FPR128_loRegClassID], |
| 11444 | QQ_with_qsub1_in_FPR128_loSubClassMask, |
| 11445 | SuperRegIdxSeqs + 129, |
| 11446 | LaneBitmask(0x0000000000000401), |
| 11447 | 0, |
| 11448 | true, /* HasDisjunctSubRegs */ |
| 11449 | true, /* CoveredBySubRegs */ |
| 11450 | QQ_with_qsub1_in_FPR128_loSuperclasses, |
| 11451 | nullptr |
| 11452 | }; |
| 11453 | |
| 11454 | extern const TargetRegisterClass ZPR2_with_dsub_in_FPR64_loRegClass = { |
| 11455 | &AArch64MCRegisterClasses[ZPR2_with_dsub_in_FPR64_loRegClassID], |
| 11456 | ZPR2_with_dsub_in_FPR64_loSubClassMask, |
| 11457 | SuperRegIdxSeqs + 103, |
| 11458 | LaneBitmask(0x0000000000600041), |
| 11459 | 0, |
| 11460 | true, /* HasDisjunctSubRegs */ |
| 11461 | true, /* CoveredBySubRegs */ |
| 11462 | ZPR2_with_dsub_in_FPR64_loSuperclasses, |
| 11463 | nullptr |
| 11464 | }; |
| 11465 | |
| 11466 | extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass = { |
| 11467 | &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_4bRegClassID], |
| 11468 | ZPR2_with_zsub1_in_ZPR_4bSubClassMask, |
| 11469 | SuperRegIdxSeqs + 103, |
| 11470 | LaneBitmask(0x0000000000600041), |
| 11471 | 0, |
| 11472 | true, /* HasDisjunctSubRegs */ |
| 11473 | true, /* CoveredBySubRegs */ |
| 11474 | ZPR2_with_zsub1_in_ZPR_4bSuperclasses, |
| 11475 | nullptr |
| 11476 | }; |
| 11477 | |
| 11478 | extern const TargetRegisterClass QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = { |
| 11479 | &AArch64MCRegisterClasses[QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID], |
| 11480 | QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loSubClassMask, |
| 11481 | SuperRegIdxSeqs + 129, |
| 11482 | LaneBitmask(0x0000000000000401), |
| 11483 | 0, |
| 11484 | true, /* HasDisjunctSubRegs */ |
| 11485 | true, /* CoveredBySubRegs */ |
| 11486 | QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses, |
| 11487 | nullptr |
| 11488 | }; |
| 11489 | |
| 11490 | extern const TargetRegisterClass ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass = { |
| 11491 | &AArch64MCRegisterClasses[ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClassID], |
| 11492 | ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bSubClassMask, |
| 11493 | SuperRegIdxSeqs + 103, |
| 11494 | LaneBitmask(0x0000000000600041), |
| 11495 | 0, |
| 11496 | true, /* HasDisjunctSubRegs */ |
| 11497 | true, /* CoveredBySubRegs */ |
| 11498 | ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses, |
| 11499 | nullptr |
| 11500 | }; |
| 11501 | |
| 11502 | extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass = { |
| 11503 | &AArch64MCRegisterClasses[ZPR2_with_zsub0_in_ZPR_3bRegClassID], |
| 11504 | ZPR2_with_zsub0_in_ZPR_3bSubClassMask, |
| 11505 | SuperRegIdxSeqs + 103, |
| 11506 | LaneBitmask(0x0000000000600041), |
| 11507 | 0, |
| 11508 | true, /* HasDisjunctSubRegs */ |
| 11509 | true, /* CoveredBySubRegs */ |
| 11510 | ZPR2_with_zsub0_in_ZPR_3bSuperclasses, |
| 11511 | nullptr |
| 11512 | }; |
| 11513 | |
| 11514 | extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass = { |
| 11515 | &AArch64MCRegisterClasses[ZPR2_with_zsub1_in_ZPR_3bRegClassID], |
| 11516 | ZPR2_with_zsub1_in_ZPR_3bSubClassMask, |
| 11517 | SuperRegIdxSeqs + 103, |
| 11518 | LaneBitmask(0x0000000000600041), |
| 11519 | 0, |
| 11520 | true, /* HasDisjunctSubRegs */ |
| 11521 | true, /* CoveredBySubRegs */ |
| 11522 | ZPR2_with_zsub1_in_ZPR_3bSuperclasses, |
| 11523 | nullptr |
| 11524 | }; |
| 11525 | |
| 11526 | extern const TargetRegisterClass ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass = { |
| 11527 | &AArch64MCRegisterClasses[ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClassID], |
| 11528 | ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bSubClassMask, |
| 11529 | SuperRegIdxSeqs + 103, |
| 11530 | LaneBitmask(0x0000000000600041), |
| 11531 | 0, |
| 11532 | true, /* HasDisjunctSubRegs */ |
| 11533 | true, /* CoveredBySubRegs */ |
| 11534 | ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses, |
| 11535 | nullptr |
| 11536 | }; |
| 11537 | |
| 11538 | extern const TargetRegisterClass QQQRegClass = { |
| 11539 | &AArch64MCRegisterClasses[QQQRegClassID], |
| 11540 | QQQSubClassMask, |
| 11541 | SuperRegIdxSeqs + 114, |
| 11542 | LaneBitmask(0x0000000000001401), |
| 11543 | 0, |
| 11544 | true, /* HasDisjunctSubRegs */ |
| 11545 | true, /* CoveredBySubRegs */ |
| 11546 | NullRegClasses, |
| 11547 | nullptr |
| 11548 | }; |
| 11549 | |
| 11550 | extern const TargetRegisterClass ZPR3RegClass = { |
| 11551 | &AArch64MCRegisterClasses[ZPR3RegClassID], |
| 11552 | ZPR3SubClassMask, |
| 11553 | SuperRegIdxSeqs + 100, |
| 11554 | LaneBitmask(0x0000000006600041), |
| 11555 | 0, |
| 11556 | true, /* HasDisjunctSubRegs */ |
| 11557 | true, /* CoveredBySubRegs */ |
| 11558 | NullRegClasses, |
| 11559 | nullptr |
| 11560 | }; |
| 11561 | |
| 11562 | extern const TargetRegisterClass QQQ_with_dsub_in_FPR64_loRegClass = { |
| 11563 | &AArch64MCRegisterClasses[QQQ_with_dsub_in_FPR64_loRegClassID], |
| 11564 | QQQ_with_dsub_in_FPR64_loSubClassMask, |
| 11565 | SuperRegIdxSeqs + 114, |
| 11566 | LaneBitmask(0x0000000000001401), |
| 11567 | 0, |
| 11568 | true, /* HasDisjunctSubRegs */ |
| 11569 | true, /* CoveredBySubRegs */ |
| 11570 | QQQ_with_dsub_in_FPR64_loSuperclasses, |
| 11571 | nullptr |
| 11572 | }; |
| 11573 | |
| 11574 | extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = { |
| 11575 | &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_loRegClassID], |
| 11576 | QQQ_with_qsub1_in_FPR128_loSubClassMask, |
| 11577 | SuperRegIdxSeqs + 114, |
| 11578 | LaneBitmask(0x0000000000001401), |
| 11579 | 0, |
| 11580 | true, /* HasDisjunctSubRegs */ |
| 11581 | true, /* CoveredBySubRegs */ |
| 11582 | QQQ_with_qsub1_in_FPR128_loSuperclasses, |
| 11583 | nullptr |
| 11584 | }; |
| 11585 | |
| 11586 | extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = { |
| 11587 | &AArch64MCRegisterClasses[QQQ_with_qsub2_in_FPR128_loRegClassID], |
| 11588 | QQQ_with_qsub2_in_FPR128_loSubClassMask, |
| 11589 | SuperRegIdxSeqs + 114, |
| 11590 | LaneBitmask(0x0000000000001401), |
| 11591 | 0, |
| 11592 | true, /* HasDisjunctSubRegs */ |
| 11593 | true, /* CoveredBySubRegs */ |
| 11594 | QQQ_with_qsub2_in_FPR128_loSuperclasses, |
| 11595 | nullptr |
| 11596 | }; |
| 11597 | |
| 11598 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_loRegClass = { |
| 11599 | &AArch64MCRegisterClasses[ZPR3_with_dsub_in_FPR64_loRegClassID], |
| 11600 | ZPR3_with_dsub_in_FPR64_loSubClassMask, |
| 11601 | SuperRegIdxSeqs + 100, |
| 11602 | LaneBitmask(0x0000000006600041), |
| 11603 | 0, |
| 11604 | true, /* HasDisjunctSubRegs */ |
| 11605 | true, /* CoveredBySubRegs */ |
| 11606 | ZPR3_with_dsub_in_FPR64_loSuperclasses, |
| 11607 | nullptr |
| 11608 | }; |
| 11609 | |
| 11610 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass = { |
| 11611 | &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4bRegClassID], |
| 11612 | ZPR3_with_zsub1_in_ZPR_4bSubClassMask, |
| 11613 | SuperRegIdxSeqs + 100, |
| 11614 | LaneBitmask(0x0000000006600041), |
| 11615 | 0, |
| 11616 | true, /* HasDisjunctSubRegs */ |
| 11617 | true, /* CoveredBySubRegs */ |
| 11618 | ZPR3_with_zsub1_in_ZPR_4bSuperclasses, |
| 11619 | nullptr |
| 11620 | }; |
| 11621 | |
| 11622 | extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass = { |
| 11623 | &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_4bRegClassID], |
| 11624 | ZPR3_with_zsub2_in_ZPR_4bSubClassMask, |
| 11625 | SuperRegIdxSeqs + 100, |
| 11626 | LaneBitmask(0x0000000006600041), |
| 11627 | 0, |
| 11628 | true, /* HasDisjunctSubRegs */ |
| 11629 | true, /* CoveredBySubRegs */ |
| 11630 | ZPR3_with_zsub2_in_ZPR_4bSuperclasses, |
| 11631 | nullptr |
| 11632 | }; |
| 11633 | |
| 11634 | extern const TargetRegisterClass QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = { |
| 11635 | &AArch64MCRegisterClasses[QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID], |
| 11636 | QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loSubClassMask, |
| 11637 | SuperRegIdxSeqs + 114, |
| 11638 | LaneBitmask(0x0000000000001401), |
| 11639 | 0, |
| 11640 | true, /* HasDisjunctSubRegs */ |
| 11641 | true, /* CoveredBySubRegs */ |
| 11642 | QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses, |
| 11643 | nullptr |
| 11644 | }; |
| 11645 | |
| 11646 | extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = { |
| 11647 | &AArch64MCRegisterClasses[QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID], |
| 11648 | QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask, |
| 11649 | SuperRegIdxSeqs + 114, |
| 11650 | LaneBitmask(0x0000000000001401), |
| 11651 | 0, |
| 11652 | true, /* HasDisjunctSubRegs */ |
| 11653 | true, /* CoveredBySubRegs */ |
| 11654 | QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses, |
| 11655 | nullptr |
| 11656 | }; |
| 11657 | |
| 11658 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass = { |
| 11659 | &AArch64MCRegisterClasses[ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClassID], |
| 11660 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bSubClassMask, |
| 11661 | SuperRegIdxSeqs + 100, |
| 11662 | LaneBitmask(0x0000000006600041), |
| 11663 | 0, |
| 11664 | true, /* HasDisjunctSubRegs */ |
| 11665 | true, /* CoveredBySubRegs */ |
| 11666 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses, |
| 11667 | nullptr |
| 11668 | }; |
| 11669 | |
| 11670 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = { |
| 11671 | &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID], |
| 11672 | ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask, |
| 11673 | SuperRegIdxSeqs + 100, |
| 11674 | LaneBitmask(0x0000000006600041), |
| 11675 | 0, |
| 11676 | true, /* HasDisjunctSubRegs */ |
| 11677 | true, /* CoveredBySubRegs */ |
| 11678 | ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses, |
| 11679 | nullptr |
| 11680 | }; |
| 11681 | |
| 11682 | extern const TargetRegisterClass QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = { |
| 11683 | &AArch64MCRegisterClasses[QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID], |
| 11684 | QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loSubClassMask, |
| 11685 | SuperRegIdxSeqs + 114, |
| 11686 | LaneBitmask(0x0000000000001401), |
| 11687 | 0, |
| 11688 | true, /* HasDisjunctSubRegs */ |
| 11689 | true, /* CoveredBySubRegs */ |
| 11690 | QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses, |
| 11691 | nullptr |
| 11692 | }; |
| 11693 | |
| 11694 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = { |
| 11695 | &AArch64MCRegisterClasses[ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClassID], |
| 11696 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bSubClassMask, |
| 11697 | SuperRegIdxSeqs + 100, |
| 11698 | LaneBitmask(0x0000000006600041), |
| 11699 | 0, |
| 11700 | true, /* HasDisjunctSubRegs */ |
| 11701 | true, /* CoveredBySubRegs */ |
| 11702 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses, |
| 11703 | nullptr |
| 11704 | }; |
| 11705 | |
| 11706 | extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass = { |
| 11707 | &AArch64MCRegisterClasses[ZPR3_with_zsub0_in_ZPR_3bRegClassID], |
| 11708 | ZPR3_with_zsub0_in_ZPR_3bSubClassMask, |
| 11709 | SuperRegIdxSeqs + 100, |
| 11710 | LaneBitmask(0x0000000006600041), |
| 11711 | 0, |
| 11712 | true, /* HasDisjunctSubRegs */ |
| 11713 | true, /* CoveredBySubRegs */ |
| 11714 | ZPR3_with_zsub0_in_ZPR_3bSuperclasses, |
| 11715 | nullptr |
| 11716 | }; |
| 11717 | |
| 11718 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass = { |
| 11719 | &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3bRegClassID], |
| 11720 | ZPR3_with_zsub1_in_ZPR_3bSubClassMask, |
| 11721 | SuperRegIdxSeqs + 100, |
| 11722 | LaneBitmask(0x0000000006600041), |
| 11723 | 0, |
| 11724 | true, /* HasDisjunctSubRegs */ |
| 11725 | true, /* CoveredBySubRegs */ |
| 11726 | ZPR3_with_zsub1_in_ZPR_3bSuperclasses, |
| 11727 | nullptr |
| 11728 | }; |
| 11729 | |
| 11730 | extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass = { |
| 11731 | &AArch64MCRegisterClasses[ZPR3_with_zsub2_in_ZPR_3bRegClassID], |
| 11732 | ZPR3_with_zsub2_in_ZPR_3bSubClassMask, |
| 11733 | SuperRegIdxSeqs + 100, |
| 11734 | LaneBitmask(0x0000000006600041), |
| 11735 | 0, |
| 11736 | true, /* HasDisjunctSubRegs */ |
| 11737 | true, /* CoveredBySubRegs */ |
| 11738 | ZPR3_with_zsub2_in_ZPR_3bSuperclasses, |
| 11739 | nullptr |
| 11740 | }; |
| 11741 | |
| 11742 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass = { |
| 11743 | &AArch64MCRegisterClasses[ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClassID], |
| 11744 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bSubClassMask, |
| 11745 | SuperRegIdxSeqs + 100, |
| 11746 | LaneBitmask(0x0000000006600041), |
| 11747 | 0, |
| 11748 | true, /* HasDisjunctSubRegs */ |
| 11749 | true, /* CoveredBySubRegs */ |
| 11750 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses, |
| 11751 | nullptr |
| 11752 | }; |
| 11753 | |
| 11754 | extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = { |
| 11755 | &AArch64MCRegisterClasses[ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID], |
| 11756 | ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask, |
| 11757 | SuperRegIdxSeqs + 100, |
| 11758 | LaneBitmask(0x0000000006600041), |
| 11759 | 0, |
| 11760 | true, /* HasDisjunctSubRegs */ |
| 11761 | true, /* CoveredBySubRegs */ |
| 11762 | ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses, |
| 11763 | nullptr |
| 11764 | }; |
| 11765 | |
| 11766 | extern const TargetRegisterClass ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = { |
| 11767 | &AArch64MCRegisterClasses[ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClassID], |
| 11768 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bSubClassMask, |
| 11769 | SuperRegIdxSeqs + 100, |
| 11770 | LaneBitmask(0x0000000006600041), |
| 11771 | 0, |
| 11772 | true, /* HasDisjunctSubRegs */ |
| 11773 | true, /* CoveredBySubRegs */ |
| 11774 | ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses, |
| 11775 | nullptr |
| 11776 | }; |
| 11777 | |
| 11778 | extern const TargetRegisterClass QQQQRegClass = { |
| 11779 | &AArch64MCRegisterClasses[QQQQRegClassID], |
| 11780 | QQQQSubClassMask, |
| 11781 | SuperRegIdxSeqs + 98, |
| 11782 | LaneBitmask(0x0000000000001C01), |
| 11783 | 0, |
| 11784 | true, /* HasDisjunctSubRegs */ |
| 11785 | true, /* CoveredBySubRegs */ |
| 11786 | NullRegClasses, |
| 11787 | nullptr |
| 11788 | }; |
| 11789 | |
| 11790 | extern const TargetRegisterClass ZPR4RegClass = { |
| 11791 | &AArch64MCRegisterClasses[ZPR4RegClassID], |
| 11792 | ZPR4SubClassMask, |
| 11793 | SuperRegIdxSeqs + 1, |
| 11794 | LaneBitmask(0x0000000007E00041), |
| 11795 | 0, |
| 11796 | true, /* HasDisjunctSubRegs */ |
| 11797 | true, /* CoveredBySubRegs */ |
| 11798 | NullRegClasses, |
| 11799 | nullptr |
| 11800 | }; |
| 11801 | |
| 11802 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_loRegClass = { |
| 11803 | &AArch64MCRegisterClasses[QQQQ_with_dsub_in_FPR64_loRegClassID], |
| 11804 | QQQQ_with_dsub_in_FPR64_loSubClassMask, |
| 11805 | SuperRegIdxSeqs + 98, |
| 11806 | LaneBitmask(0x0000000000001C01), |
| 11807 | 0, |
| 11808 | true, /* HasDisjunctSubRegs */ |
| 11809 | true, /* CoveredBySubRegs */ |
| 11810 | QQQQ_with_dsub_in_FPR64_loSuperclasses, |
| 11811 | nullptr |
| 11812 | }; |
| 11813 | |
| 11814 | extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = { |
| 11815 | &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_loRegClassID], |
| 11816 | QQQQ_with_qsub1_in_FPR128_loSubClassMask, |
| 11817 | SuperRegIdxSeqs + 98, |
| 11818 | LaneBitmask(0x0000000000001C01), |
| 11819 | 0, |
| 11820 | true, /* HasDisjunctSubRegs */ |
| 11821 | true, /* CoveredBySubRegs */ |
| 11822 | QQQQ_with_qsub1_in_FPR128_loSuperclasses, |
| 11823 | nullptr |
| 11824 | }; |
| 11825 | |
| 11826 | extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = { |
| 11827 | &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_loRegClassID], |
| 11828 | QQQQ_with_qsub2_in_FPR128_loSubClassMask, |
| 11829 | SuperRegIdxSeqs + 98, |
| 11830 | LaneBitmask(0x0000000000001C01), |
| 11831 | 0, |
| 11832 | true, /* HasDisjunctSubRegs */ |
| 11833 | true, /* CoveredBySubRegs */ |
| 11834 | QQQQ_with_qsub2_in_FPR128_loSuperclasses, |
| 11835 | nullptr |
| 11836 | }; |
| 11837 | |
| 11838 | extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = { |
| 11839 | &AArch64MCRegisterClasses[QQQQ_with_qsub3_in_FPR128_loRegClassID], |
| 11840 | QQQQ_with_qsub3_in_FPR128_loSubClassMask, |
| 11841 | SuperRegIdxSeqs + 98, |
| 11842 | LaneBitmask(0x0000000000001C01), |
| 11843 | 0, |
| 11844 | true, /* HasDisjunctSubRegs */ |
| 11845 | true, /* CoveredBySubRegs */ |
| 11846 | QQQQ_with_qsub3_in_FPR128_loSuperclasses, |
| 11847 | nullptr |
| 11848 | }; |
| 11849 | |
| 11850 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_loRegClass = { |
| 11851 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_loRegClassID], |
| 11852 | ZPR4_with_dsub_in_FPR64_loSubClassMask, |
| 11853 | SuperRegIdxSeqs + 1, |
| 11854 | LaneBitmask(0x0000000007E00041), |
| 11855 | 0, |
| 11856 | true, /* HasDisjunctSubRegs */ |
| 11857 | true, /* CoveredBySubRegs */ |
| 11858 | ZPR4_with_dsub_in_FPR64_loSuperclasses, |
| 11859 | nullptr |
| 11860 | }; |
| 11861 | |
| 11862 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass = { |
| 11863 | &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4bRegClassID], |
| 11864 | ZPR4_with_zsub1_in_ZPR_4bSubClassMask, |
| 11865 | SuperRegIdxSeqs + 1, |
| 11866 | LaneBitmask(0x0000000007E00041), |
| 11867 | 0, |
| 11868 | true, /* HasDisjunctSubRegs */ |
| 11869 | true, /* CoveredBySubRegs */ |
| 11870 | ZPR4_with_zsub1_in_ZPR_4bSuperclasses, |
| 11871 | nullptr |
| 11872 | }; |
| 11873 | |
| 11874 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass = { |
| 11875 | &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4bRegClassID], |
| 11876 | ZPR4_with_zsub2_in_ZPR_4bSubClassMask, |
| 11877 | SuperRegIdxSeqs + 1, |
| 11878 | LaneBitmask(0x0000000007E00041), |
| 11879 | 0, |
| 11880 | true, /* HasDisjunctSubRegs */ |
| 11881 | true, /* CoveredBySubRegs */ |
| 11882 | ZPR4_with_zsub2_in_ZPR_4bSuperclasses, |
| 11883 | nullptr |
| 11884 | }; |
| 11885 | |
| 11886 | extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass = { |
| 11887 | &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_4bRegClassID], |
| 11888 | ZPR4_with_zsub3_in_ZPR_4bSubClassMask, |
| 11889 | SuperRegIdxSeqs + 1, |
| 11890 | LaneBitmask(0x0000000007E00041), |
| 11891 | 0, |
| 11892 | true, /* HasDisjunctSubRegs */ |
| 11893 | true, /* CoveredBySubRegs */ |
| 11894 | ZPR4_with_zsub3_in_ZPR_4bSuperclasses, |
| 11895 | nullptr |
| 11896 | }; |
| 11897 | |
| 11898 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = { |
| 11899 | &AArch64MCRegisterClasses[QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID], |
| 11900 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loSubClassMask, |
| 11901 | SuperRegIdxSeqs + 98, |
| 11902 | LaneBitmask(0x0000000000001C01), |
| 11903 | 0, |
| 11904 | true, /* HasDisjunctSubRegs */ |
| 11905 | true, /* CoveredBySubRegs */ |
| 11906 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses, |
| 11907 | nullptr |
| 11908 | }; |
| 11909 | |
| 11910 | extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = { |
| 11911 | &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID], |
| 11912 | QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask, |
| 11913 | SuperRegIdxSeqs + 98, |
| 11914 | LaneBitmask(0x0000000000001C01), |
| 11915 | 0, |
| 11916 | true, /* HasDisjunctSubRegs */ |
| 11917 | true, /* CoveredBySubRegs */ |
| 11918 | QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses, |
| 11919 | nullptr |
| 11920 | }; |
| 11921 | |
| 11922 | extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = { |
| 11923 | &AArch64MCRegisterClasses[QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID], |
| 11924 | QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask, |
| 11925 | SuperRegIdxSeqs + 98, |
| 11926 | LaneBitmask(0x0000000000001C01), |
| 11927 | 0, |
| 11928 | true, /* HasDisjunctSubRegs */ |
| 11929 | true, /* CoveredBySubRegs */ |
| 11930 | QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses, |
| 11931 | nullptr |
| 11932 | }; |
| 11933 | |
| 11934 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass = { |
| 11935 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClassID], |
| 11936 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bSubClassMask, |
| 11937 | SuperRegIdxSeqs + 1, |
| 11938 | LaneBitmask(0x0000000007E00041), |
| 11939 | 0, |
| 11940 | true, /* HasDisjunctSubRegs */ |
| 11941 | true, /* CoveredBySubRegs */ |
| 11942 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses, |
| 11943 | nullptr |
| 11944 | }; |
| 11945 | |
| 11946 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = { |
| 11947 | &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID], |
| 11948 | ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask, |
| 11949 | SuperRegIdxSeqs + 1, |
| 11950 | LaneBitmask(0x0000000007E00041), |
| 11951 | 0, |
| 11952 | true, /* HasDisjunctSubRegs */ |
| 11953 | true, /* CoveredBySubRegs */ |
| 11954 | ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses, |
| 11955 | nullptr |
| 11956 | }; |
| 11957 | |
| 11958 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = { |
| 11959 | &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID], |
| 11960 | ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask, |
| 11961 | SuperRegIdxSeqs + 1, |
| 11962 | LaneBitmask(0x0000000007E00041), |
| 11963 | 0, |
| 11964 | true, /* HasDisjunctSubRegs */ |
| 11965 | true, /* CoveredBySubRegs */ |
| 11966 | ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses, |
| 11967 | nullptr |
| 11968 | }; |
| 11969 | |
| 11970 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = { |
| 11971 | &AArch64MCRegisterClasses[QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID], |
| 11972 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loSubClassMask, |
| 11973 | SuperRegIdxSeqs + 98, |
| 11974 | LaneBitmask(0x0000000000001C01), |
| 11975 | 0, |
| 11976 | true, /* HasDisjunctSubRegs */ |
| 11977 | true, /* CoveredBySubRegs */ |
| 11978 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses, |
| 11979 | nullptr |
| 11980 | }; |
| 11981 | |
| 11982 | extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = { |
| 11983 | &AArch64MCRegisterClasses[QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID], |
| 11984 | QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask, |
| 11985 | SuperRegIdxSeqs + 98, |
| 11986 | LaneBitmask(0x0000000000001C01), |
| 11987 | 0, |
| 11988 | true, /* HasDisjunctSubRegs */ |
| 11989 | true, /* CoveredBySubRegs */ |
| 11990 | QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses, |
| 11991 | nullptr |
| 11992 | }; |
| 11993 | |
| 11994 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = { |
| 11995 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClassID], |
| 11996 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bSubClassMask, |
| 11997 | SuperRegIdxSeqs + 1, |
| 11998 | LaneBitmask(0x0000000007E00041), |
| 11999 | 0, |
| 12000 | true, /* HasDisjunctSubRegs */ |
| 12001 | true, /* CoveredBySubRegs */ |
| 12002 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses, |
| 12003 | nullptr |
| 12004 | }; |
| 12005 | |
| 12006 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = { |
| 12007 | &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID], |
| 12008 | ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask, |
| 12009 | SuperRegIdxSeqs + 1, |
| 12010 | LaneBitmask(0x0000000007E00041), |
| 12011 | 0, |
| 12012 | true, /* HasDisjunctSubRegs */ |
| 12013 | true, /* CoveredBySubRegs */ |
| 12014 | ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses, |
| 12015 | nullptr |
| 12016 | }; |
| 12017 | |
| 12018 | extern const TargetRegisterClass QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = { |
| 12019 | &AArch64MCRegisterClasses[QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID], |
| 12020 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loSubClassMask, |
| 12021 | SuperRegIdxSeqs + 98, |
| 12022 | LaneBitmask(0x0000000000001C01), |
| 12023 | 0, |
| 12024 | true, /* HasDisjunctSubRegs */ |
| 12025 | true, /* CoveredBySubRegs */ |
| 12026 | QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses, |
| 12027 | nullptr |
| 12028 | }; |
| 12029 | |
| 12030 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = { |
| 12031 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClassID], |
| 12032 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bSubClassMask, |
| 12033 | SuperRegIdxSeqs + 1, |
| 12034 | LaneBitmask(0x0000000007E00041), |
| 12035 | 0, |
| 12036 | true, /* HasDisjunctSubRegs */ |
| 12037 | true, /* CoveredBySubRegs */ |
| 12038 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses, |
| 12039 | nullptr |
| 12040 | }; |
| 12041 | |
| 12042 | extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass = { |
| 12043 | &AArch64MCRegisterClasses[ZPR4_with_zsub0_in_ZPR_3bRegClassID], |
| 12044 | ZPR4_with_zsub0_in_ZPR_3bSubClassMask, |
| 12045 | SuperRegIdxSeqs + 1, |
| 12046 | LaneBitmask(0x0000000007E00041), |
| 12047 | 0, |
| 12048 | true, /* HasDisjunctSubRegs */ |
| 12049 | true, /* CoveredBySubRegs */ |
| 12050 | ZPR4_with_zsub0_in_ZPR_3bSuperclasses, |
| 12051 | nullptr |
| 12052 | }; |
| 12053 | |
| 12054 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass = { |
| 12055 | &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3bRegClassID], |
| 12056 | ZPR4_with_zsub1_in_ZPR_3bSubClassMask, |
| 12057 | SuperRegIdxSeqs + 1, |
| 12058 | LaneBitmask(0x0000000007E00041), |
| 12059 | 0, |
| 12060 | true, /* HasDisjunctSubRegs */ |
| 12061 | true, /* CoveredBySubRegs */ |
| 12062 | ZPR4_with_zsub1_in_ZPR_3bSuperclasses, |
| 12063 | nullptr |
| 12064 | }; |
| 12065 | |
| 12066 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass = { |
| 12067 | &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3bRegClassID], |
| 12068 | ZPR4_with_zsub2_in_ZPR_3bSubClassMask, |
| 12069 | SuperRegIdxSeqs + 1, |
| 12070 | LaneBitmask(0x0000000007E00041), |
| 12071 | 0, |
| 12072 | true, /* HasDisjunctSubRegs */ |
| 12073 | true, /* CoveredBySubRegs */ |
| 12074 | ZPR4_with_zsub2_in_ZPR_3bSuperclasses, |
| 12075 | nullptr |
| 12076 | }; |
| 12077 | |
| 12078 | extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass = { |
| 12079 | &AArch64MCRegisterClasses[ZPR4_with_zsub3_in_ZPR_3bRegClassID], |
| 12080 | ZPR4_with_zsub3_in_ZPR_3bSubClassMask, |
| 12081 | SuperRegIdxSeqs + 1, |
| 12082 | LaneBitmask(0x0000000007E00041), |
| 12083 | 0, |
| 12084 | true, /* HasDisjunctSubRegs */ |
| 12085 | true, /* CoveredBySubRegs */ |
| 12086 | ZPR4_with_zsub3_in_ZPR_3bSuperclasses, |
| 12087 | nullptr |
| 12088 | }; |
| 12089 | |
| 12090 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass = { |
| 12091 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClassID], |
| 12092 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bSubClassMask, |
| 12093 | SuperRegIdxSeqs + 1, |
| 12094 | LaneBitmask(0x0000000007E00041), |
| 12095 | 0, |
| 12096 | true, /* HasDisjunctSubRegs */ |
| 12097 | true, /* CoveredBySubRegs */ |
| 12098 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses, |
| 12099 | nullptr |
| 12100 | }; |
| 12101 | |
| 12102 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = { |
| 12103 | &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID], |
| 12104 | ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask, |
| 12105 | SuperRegIdxSeqs + 1, |
| 12106 | LaneBitmask(0x0000000007E00041), |
| 12107 | 0, |
| 12108 | true, /* HasDisjunctSubRegs */ |
| 12109 | true, /* CoveredBySubRegs */ |
| 12110 | ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses, |
| 12111 | nullptr |
| 12112 | }; |
| 12113 | |
| 12114 | extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = { |
| 12115 | &AArch64MCRegisterClasses[ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID], |
| 12116 | ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask, |
| 12117 | SuperRegIdxSeqs + 1, |
| 12118 | LaneBitmask(0x0000000007E00041), |
| 12119 | 0, |
| 12120 | true, /* HasDisjunctSubRegs */ |
| 12121 | true, /* CoveredBySubRegs */ |
| 12122 | ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses, |
| 12123 | nullptr |
| 12124 | }; |
| 12125 | |
| 12126 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = { |
| 12127 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClassID], |
| 12128 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bSubClassMask, |
| 12129 | SuperRegIdxSeqs + 1, |
| 12130 | LaneBitmask(0x0000000007E00041), |
| 12131 | 0, |
| 12132 | true, /* HasDisjunctSubRegs */ |
| 12133 | true, /* CoveredBySubRegs */ |
| 12134 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses, |
| 12135 | nullptr |
| 12136 | }; |
| 12137 | |
| 12138 | extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = { |
| 12139 | &AArch64MCRegisterClasses[ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID], |
| 12140 | ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask, |
| 12141 | SuperRegIdxSeqs + 1, |
| 12142 | LaneBitmask(0x0000000007E00041), |
| 12143 | 0, |
| 12144 | true, /* HasDisjunctSubRegs */ |
| 12145 | true, /* CoveredBySubRegs */ |
| 12146 | ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses, |
| 12147 | nullptr |
| 12148 | }; |
| 12149 | |
| 12150 | extern const TargetRegisterClass ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = { |
| 12151 | &AArch64MCRegisterClasses[ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClassID], |
| 12152 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bSubClassMask, |
| 12153 | SuperRegIdxSeqs + 1, |
| 12154 | LaneBitmask(0x0000000007E00041), |
| 12155 | 0, |
| 12156 | true, /* HasDisjunctSubRegs */ |
| 12157 | true, /* CoveredBySubRegs */ |
| 12158 | ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses, |
| 12159 | nullptr |
| 12160 | }; |
| 12161 | |
| 12162 | } // end namespace AArch64 |
| 12163 | |
| 12164 | namespace { |
| 12165 | const TargetRegisterClass *const RegisterClasses[] = { |
| 12166 | &AArch64::FPR8RegClass, |
| 12167 | &AArch64::FPR16RegClass, |
| 12168 | &AArch64::FPR16_loRegClass, |
| 12169 | &AArch64::PPRRegClass, |
| 12170 | &AArch64::PPR_3bRegClass, |
| 12171 | &AArch64::GPR32allRegClass, |
| 12172 | &AArch64::FPR32RegClass, |
| 12173 | &AArch64::GPR32RegClass, |
| 12174 | &AArch64::GPR32spRegClass, |
| 12175 | &AArch64::GPR32commonRegClass, |
| 12176 | &AArch64::FPR32_with_hsub_in_FPR16_loRegClass, |
| 12177 | &AArch64::GPR32argRegClass, |
| 12178 | &AArch64::CCRRegClass, |
| 12179 | &AArch64::GPR32sponlyRegClass, |
| 12180 | &AArch64::WSeqPairsClassRegClass, |
| 12181 | &AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClass, |
| 12182 | &AArch64::WSeqPairsClass_with_sube32_in_GPR32argRegClass, |
| 12183 | &AArch64::GPR64allRegClass, |
| 12184 | &AArch64::FPR64RegClass, |
| 12185 | &AArch64::GPR64RegClass, |
| 12186 | &AArch64::GPR64spRegClass, |
| 12187 | &AArch64::GPR64commonRegClass, |
| 12188 | &AArch64::GPR64noipRegClass, |
| 12189 | &AArch64::GPR64common_and_GPR64noipRegClass, |
| 12190 | &AArch64::tcGPR64RegClass, |
| 12191 | &AArch64::GPR64noip_and_tcGPR64RegClass, |
| 12192 | &AArch64::FPR64_loRegClass, |
| 12193 | &AArch64::GPR64x8ClassRegClass, |
| 12194 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noipRegClass, |
| 12195 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 12196 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12197 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12198 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 12199 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12200 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12201 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64RegClass, |
| 12202 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12203 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12204 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12205 | &AArch64::GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64RegClass, |
| 12206 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 12207 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12208 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12209 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64RegClass, |
| 12210 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12211 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12212 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12213 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12214 | &AArch64::GPR64argRegClass, |
| 12215 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noipRegClass, |
| 12216 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12217 | &AArch64::GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12218 | &AArch64::GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64RegClass, |
| 12219 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12220 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12221 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12222 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12223 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64RegClass, |
| 12224 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12225 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12226 | &AArch64::GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12227 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12228 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12229 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noipRegClass, |
| 12230 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12231 | &AArch64::GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64RegClass, |
| 12232 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12233 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12234 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12235 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64RegClass, |
| 12236 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12237 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12238 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noipRegClass, |
| 12239 | &AArch64::GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64RegClass, |
| 12240 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64RegClass, |
| 12241 | &AArch64::GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64RegClass, |
| 12242 | &AArch64::GPR64x8Class_with_sub_32_in_GPR32argRegClass, |
| 12243 | &AArch64::GPR64x8Class_with_x8sub_2_in_GPR64argRegClass, |
| 12244 | &AArch64::GPR64x8Class_with_x8sub_4_in_GPR64argRegClass, |
| 12245 | &AArch64::rtcGPR64RegClass, |
| 12246 | &AArch64::GPR64sponlyRegClass, |
| 12247 | &AArch64::GPR64x8Class_with_x8sub_0_in_rtcGPR64RegClass, |
| 12248 | &AArch64::GPR64x8Class_with_x8sub_2_in_rtcGPR64RegClass, |
| 12249 | &AArch64::GPR64x8Class_with_x8sub_4_in_rtcGPR64RegClass, |
| 12250 | &AArch64::GPR64x8Class_with_x8sub_6_in_GPR64argRegClass, |
| 12251 | &AArch64::GPR64x8Class_with_x8sub_6_in_rtcGPR64RegClass, |
| 12252 | &AArch64::DDRegClass, |
| 12253 | &AArch64::DD_with_dsub0_in_FPR64_loRegClass, |
| 12254 | &AArch64::DD_with_dsub1_in_FPR64_loRegClass, |
| 12255 | &AArch64::XSeqPairsClassRegClass, |
| 12256 | &AArch64::DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_loRegClass, |
| 12257 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClass, |
| 12258 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noipRegClass, |
| 12259 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noipRegClass, |
| 12260 | &AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClass, |
| 12261 | &AArch64::XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass, |
| 12262 | &AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClass, |
| 12263 | &AArch64::XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass, |
| 12264 | &AArch64::XSeqPairsClass_with_sub_32_in_GPR32argRegClass, |
| 12265 | &AArch64::XSeqPairsClass_with_sube64_in_rtcGPR64RegClass, |
| 12266 | &AArch64::FPR128RegClass, |
| 12267 | &AArch64::ZPRRegClass, |
| 12268 | &AArch64::FPR128_loRegClass, |
| 12269 | &AArch64::ZPR_4bRegClass, |
| 12270 | &AArch64::ZPR_3bRegClass, |
| 12271 | &AArch64::DDDRegClass, |
| 12272 | &AArch64::DDD_with_dsub0_in_FPR64_loRegClass, |
| 12273 | &AArch64::DDD_with_dsub1_in_FPR64_loRegClass, |
| 12274 | &AArch64::DDD_with_dsub2_in_FPR64_loRegClass, |
| 12275 | &AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_loRegClass, |
| 12276 | &AArch64::DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass, |
| 12277 | &AArch64::DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_loRegClass, |
| 12278 | &AArch64::DDDDRegClass, |
| 12279 | &AArch64::DDDD_with_dsub0_in_FPR64_loRegClass, |
| 12280 | &AArch64::DDDD_with_dsub1_in_FPR64_loRegClass, |
| 12281 | &AArch64::DDDD_with_dsub2_in_FPR64_loRegClass, |
| 12282 | &AArch64::DDDD_with_dsub3_in_FPR64_loRegClass, |
| 12283 | &AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_loRegClass, |
| 12284 | &AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass, |
| 12285 | &AArch64::DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass, |
| 12286 | &AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_loRegClass, |
| 12287 | &AArch64::DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass, |
| 12288 | &AArch64::DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_loRegClass, |
| 12289 | &AArch64::QQRegClass, |
| 12290 | &AArch64::ZPR2RegClass, |
| 12291 | &AArch64::QQ_with_dsub_in_FPR64_loRegClass, |
| 12292 | &AArch64::QQ_with_qsub1_in_FPR128_loRegClass, |
| 12293 | &AArch64::ZPR2_with_dsub_in_FPR64_loRegClass, |
| 12294 | &AArch64::ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 12295 | &AArch64::QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_loRegClass, |
| 12296 | &AArch64::ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass, |
| 12297 | &AArch64::ZPR2_with_zsub0_in_ZPR_3bRegClass, |
| 12298 | &AArch64::ZPR2_with_zsub1_in_ZPR_3bRegClass, |
| 12299 | &AArch64::ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass, |
| 12300 | &AArch64::QQQRegClass, |
| 12301 | &AArch64::ZPR3RegClass, |
| 12302 | &AArch64::QQQ_with_dsub_in_FPR64_loRegClass, |
| 12303 | &AArch64::QQQ_with_qsub1_in_FPR128_loRegClass, |
| 12304 | &AArch64::QQQ_with_qsub2_in_FPR128_loRegClass, |
| 12305 | &AArch64::ZPR3_with_dsub_in_FPR64_loRegClass, |
| 12306 | &AArch64::ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 12307 | &AArch64::ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 12308 | &AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass, |
| 12309 | &AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass, |
| 12310 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass, |
| 12311 | &AArch64::ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 12312 | &AArch64::QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass, |
| 12313 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass, |
| 12314 | &AArch64::ZPR3_with_zsub0_in_ZPR_3bRegClass, |
| 12315 | &AArch64::ZPR3_with_zsub1_in_ZPR_3bRegClass, |
| 12316 | &AArch64::ZPR3_with_zsub2_in_ZPR_3bRegClass, |
| 12317 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass, |
| 12318 | &AArch64::ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass, |
| 12319 | &AArch64::ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass, |
| 12320 | &AArch64::QQQQRegClass, |
| 12321 | &AArch64::ZPR4RegClass, |
| 12322 | &AArch64::QQQQ_with_dsub_in_FPR64_loRegClass, |
| 12323 | &AArch64::QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 12324 | &AArch64::QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 12325 | &AArch64::QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 12326 | &AArch64::ZPR4_with_dsub_in_FPR64_loRegClass, |
| 12327 | &AArch64::ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 12328 | &AArch64::ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 12329 | &AArch64::ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 12330 | &AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass, |
| 12331 | &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 12332 | &AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 12333 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass, |
| 12334 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 12335 | &AArch64::ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 12336 | &AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass, |
| 12337 | &AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 12338 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass, |
| 12339 | &AArch64::ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 12340 | &AArch64::QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass, |
| 12341 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass, |
| 12342 | &AArch64::ZPR4_with_zsub0_in_ZPR_3bRegClass, |
| 12343 | &AArch64::ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 12344 | &AArch64::ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 12345 | &AArch64::ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 12346 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass, |
| 12347 | &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 12348 | &AArch64::ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 12349 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass, |
| 12350 | &AArch64::ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 12351 | &AArch64::ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass, |
| 12352 | }; |
| 12353 | } // end anonymous namespace |
| 12354 | |
| 12355 | static const TargetRegisterInfoDesc AArch64RegInfoDesc[] = { // Extra Descriptors |
| 12356 | { 0, false }, |
| 12357 | { 0, false }, |
| 12358 | { 0, true }, |
| 12359 | { 0, true }, |
| 12360 | { 0, false }, |
| 12361 | { 0, true }, |
| 12362 | { 0, false }, |
| 12363 | { 0, true }, |
| 12364 | { 0, true }, |
| 12365 | { 0, true }, |
| 12366 | { 0, true }, |
| 12367 | { 0, true }, |
| 12368 | { 0, true }, |
| 12369 | { 0, true }, |
| 12370 | { 0, true }, |
| 12371 | { 0, true }, |
| 12372 | { 0, true }, |
| 12373 | { 0, true }, |
| 12374 | { 0, true }, |
| 12375 | { 0, true }, |
| 12376 | { 0, true }, |
| 12377 | { 0, true }, |
| 12378 | { 0, true }, |
| 12379 | { 0, true }, |
| 12380 | { 0, true }, |
| 12381 | { 0, true }, |
| 12382 | { 0, true }, |
| 12383 | { 0, true }, |
| 12384 | { 0, true }, |
| 12385 | { 0, true }, |
| 12386 | { 0, true }, |
| 12387 | { 0, true }, |
| 12388 | { 0, true }, |
| 12389 | { 0, true }, |
| 12390 | { 0, true }, |
| 12391 | { 0, true }, |
| 12392 | { 0, true }, |
| 12393 | { 0, true }, |
| 12394 | { 0, true }, |
| 12395 | { 0, true }, |
| 12396 | { 0, true }, |
| 12397 | { 0, true }, |
| 12398 | { 0, true }, |
| 12399 | { 0, true }, |
| 12400 | { 0, true }, |
| 12401 | { 0, true }, |
| 12402 | { 0, true }, |
| 12403 | { 0, true }, |
| 12404 | { 0, true }, |
| 12405 | { 0, true }, |
| 12406 | { 0, true }, |
| 12407 | { 0, true }, |
| 12408 | { 0, true }, |
| 12409 | { 0, true }, |
| 12410 | { 0, true }, |
| 12411 | { 0, true }, |
| 12412 | { 0, true }, |
| 12413 | { 0, true }, |
| 12414 | { 0, true }, |
| 12415 | { 0, true }, |
| 12416 | { 0, true }, |
| 12417 | { 0, true }, |
| 12418 | { 0, true }, |
| 12419 | { 0, true }, |
| 12420 | { 0, true }, |
| 12421 | { 0, true }, |
| 12422 | { 0, true }, |
| 12423 | { 0, true }, |
| 12424 | { 0, true }, |
| 12425 | { 0, true }, |
| 12426 | { 0, true }, |
| 12427 | { 0, true }, |
| 12428 | { 0, true }, |
| 12429 | { 0, true }, |
| 12430 | { 0, true }, |
| 12431 | { 0, true }, |
| 12432 | { 0, true }, |
| 12433 | { 0, true }, |
| 12434 | { 0, true }, |
| 12435 | { 0, true }, |
| 12436 | { 0, true }, |
| 12437 | { 0, true }, |
| 12438 | { 0, true }, |
| 12439 | { 0, true }, |
| 12440 | { 0, true }, |
| 12441 | { 0, true }, |
| 12442 | { 0, true }, |
| 12443 | { 0, true }, |
| 12444 | { 0, true }, |
| 12445 | { 0, true }, |
| 12446 | { 0, true }, |
| 12447 | { 0, true }, |
| 12448 | { 0, true }, |
| 12449 | { 0, true }, |
| 12450 | { 0, true }, |
| 12451 | { 0, true }, |
| 12452 | { 0, true }, |
| 12453 | { 0, true }, |
| 12454 | { 0, true }, |
| 12455 | { 0, true }, |
| 12456 | { 0, true }, |
| 12457 | { 0, true }, |
| 12458 | { 0, true }, |
| 12459 | { 0, true }, |
| 12460 | { 0, true }, |
| 12461 | { 0, true }, |
| 12462 | { 0, true }, |
| 12463 | { 0, true }, |
| 12464 | { 0, true }, |
| 12465 | { 0, true }, |
| 12466 | { 0, true }, |
| 12467 | { 0, true }, |
| 12468 | { 0, true }, |
| 12469 | { 0, true }, |
| 12470 | { 0, true }, |
| 12471 | { 0, true }, |
| 12472 | { 0, true }, |
| 12473 | { 0, true }, |
| 12474 | { 0, true }, |
| 12475 | { 0, true }, |
| 12476 | { 0, true }, |
| 12477 | { 0, true }, |
| 12478 | { 0, true }, |
| 12479 | { 0, true }, |
| 12480 | { 0, true }, |
| 12481 | { 0, true }, |
| 12482 | { 0, true }, |
| 12483 | { 0, true }, |
| 12484 | { 0, true }, |
| 12485 | { 0, true }, |
| 12486 | { 0, true }, |
| 12487 | { 0, true }, |
| 12488 | { 0, true }, |
| 12489 | { 0, true }, |
| 12490 | { 0, true }, |
| 12491 | { 0, true }, |
| 12492 | { 0, true }, |
| 12493 | { 0, true }, |
| 12494 | { 0, true }, |
| 12495 | { 0, true }, |
| 12496 | { 0, true }, |
| 12497 | { 0, true }, |
| 12498 | { 0, true }, |
| 12499 | { 0, true }, |
| 12500 | { 0, true }, |
| 12501 | { 0, true }, |
| 12502 | { 0, true }, |
| 12503 | { 0, true }, |
| 12504 | { 0, true }, |
| 12505 | { 0, true }, |
| 12506 | { 0, true }, |
| 12507 | { 0, true }, |
| 12508 | { 0, true }, |
| 12509 | { 0, true }, |
| 12510 | { 0, true }, |
| 12511 | { 0, true }, |
| 12512 | { 0, true }, |
| 12513 | { 0, true }, |
| 12514 | { 0, true }, |
| 12515 | { 0, true }, |
| 12516 | { 0, true }, |
| 12517 | { 0, true }, |
| 12518 | { 0, true }, |
| 12519 | { 0, true }, |
| 12520 | { 0, true }, |
| 12521 | { 0, true }, |
| 12522 | { 0, true }, |
| 12523 | { 0, true }, |
| 12524 | { 0, true }, |
| 12525 | { 0, true }, |
| 12526 | { 0, true }, |
| 12527 | { 0, true }, |
| 12528 | { 0, true }, |
| 12529 | { 0, true }, |
| 12530 | { 0, true }, |
| 12531 | { 0, true }, |
| 12532 | { 0, true }, |
| 12533 | { 0, true }, |
| 12534 | { 0, true }, |
| 12535 | { 0, true }, |
| 12536 | { 0, true }, |
| 12537 | { 0, true }, |
| 12538 | { 0, true }, |
| 12539 | { 0, true }, |
| 12540 | { 0, true }, |
| 12541 | { 0, true }, |
| 12542 | { 0, true }, |
| 12543 | { 0, true }, |
| 12544 | { 0, true }, |
| 12545 | { 0, true }, |
| 12546 | { 0, true }, |
| 12547 | { 0, true }, |
| 12548 | { 0, true }, |
| 12549 | { 0, true }, |
| 12550 | { 0, true }, |
| 12551 | { 0, true }, |
| 12552 | { 0, true }, |
| 12553 | { 0, true }, |
| 12554 | { 0, true }, |
| 12555 | { 0, true }, |
| 12556 | { 0, true }, |
| 12557 | { 0, true }, |
| 12558 | { 0, true }, |
| 12559 | { 0, true }, |
| 12560 | { 0, true }, |
| 12561 | { 0, true }, |
| 12562 | { 0, true }, |
| 12563 | { 0, true }, |
| 12564 | { 0, true }, |
| 12565 | { 0, true }, |
| 12566 | { 0, true }, |
| 12567 | { 0, true }, |
| 12568 | { 0, true }, |
| 12569 | { 0, true }, |
| 12570 | { 0, true }, |
| 12571 | { 0, true }, |
| 12572 | { 0, true }, |
| 12573 | { 0, true }, |
| 12574 | { 0, true }, |
| 12575 | { 0, true }, |
| 12576 | { 0, true }, |
| 12577 | { 0, true }, |
| 12578 | { 0, true }, |
| 12579 | { 0, true }, |
| 12580 | { 0, true }, |
| 12581 | { 0, true }, |
| 12582 | { 0, true }, |
| 12583 | { 0, true }, |
| 12584 | { 0, true }, |
| 12585 | { 0, true }, |
| 12586 | { 0, true }, |
| 12587 | { 0, true }, |
| 12588 | { 0, true }, |
| 12589 | { 0, true }, |
| 12590 | { 0, true }, |
| 12591 | { 0, true }, |
| 12592 | { 0, true }, |
| 12593 | { 0, true }, |
| 12594 | { 0, true }, |
| 12595 | { 0, true }, |
| 12596 | { 0, true }, |
| 12597 | { 0, true }, |
| 12598 | { 0, true }, |
| 12599 | { 0, true }, |
| 12600 | { 0, true }, |
| 12601 | { 0, true }, |
| 12602 | { 0, true }, |
| 12603 | { 0, true }, |
| 12604 | { 0, true }, |
| 12605 | { 0, true }, |
| 12606 | { 0, true }, |
| 12607 | { 0, true }, |
| 12608 | { 0, true }, |
| 12609 | { 0, true }, |
| 12610 | { 0, true }, |
| 12611 | { 0, true }, |
| 12612 | { 0, true }, |
| 12613 | { 0, true }, |
| 12614 | { 0, true }, |
| 12615 | { 0, true }, |
| 12616 | { 0, true }, |
| 12617 | { 0, true }, |
| 12618 | { 0, true }, |
| 12619 | { 0, true }, |
| 12620 | { 0, true }, |
| 12621 | { 0, true }, |
| 12622 | { 0, true }, |
| 12623 | { 0, true }, |
| 12624 | { 0, true }, |
| 12625 | { 0, true }, |
| 12626 | { 0, true }, |
| 12627 | { 0, true }, |
| 12628 | { 0, true }, |
| 12629 | { 0, true }, |
| 12630 | { 0, true }, |
| 12631 | { 0, true }, |
| 12632 | { 0, true }, |
| 12633 | { 0, true }, |
| 12634 | { 0, false }, |
| 12635 | { 0, false }, |
| 12636 | { 0, false }, |
| 12637 | { 0, false }, |
| 12638 | { 0, false }, |
| 12639 | { 0, false }, |
| 12640 | { 0, false }, |
| 12641 | { 0, false }, |
| 12642 | { 0, false }, |
| 12643 | { 0, false }, |
| 12644 | { 0, false }, |
| 12645 | { 0, false }, |
| 12646 | { 0, false }, |
| 12647 | { 0, false }, |
| 12648 | { 0, false }, |
| 12649 | { 0, false }, |
| 12650 | { 0, false }, |
| 12651 | { 0, false }, |
| 12652 | { 0, false }, |
| 12653 | { 0, false }, |
| 12654 | { 0, false }, |
| 12655 | { 0, false }, |
| 12656 | { 0, false }, |
| 12657 | { 0, false }, |
| 12658 | { 0, false }, |
| 12659 | { 0, false }, |
| 12660 | { 0, false }, |
| 12661 | { 0, false }, |
| 12662 | { 0, false }, |
| 12663 | { 0, false }, |
| 12664 | { 0, false }, |
| 12665 | { 0, false }, |
| 12666 | { 0, true }, |
| 12667 | { 0, true }, |
| 12668 | { 0, true }, |
| 12669 | { 0, true }, |
| 12670 | { 0, true }, |
| 12671 | { 0, true }, |
| 12672 | { 0, true }, |
| 12673 | { 0, true }, |
| 12674 | { 0, true }, |
| 12675 | { 0, true }, |
| 12676 | { 0, true }, |
| 12677 | { 0, true }, |
| 12678 | { 0, true }, |
| 12679 | { 0, true }, |
| 12680 | { 0, true }, |
| 12681 | { 0, true }, |
| 12682 | { 0, true }, |
| 12683 | { 0, true }, |
| 12684 | { 0, true }, |
| 12685 | { 0, true }, |
| 12686 | { 0, true }, |
| 12687 | { 0, true }, |
| 12688 | { 0, true }, |
| 12689 | { 0, true }, |
| 12690 | { 0, true }, |
| 12691 | { 0, true }, |
| 12692 | { 0, true }, |
| 12693 | { 0, true }, |
| 12694 | { 0, true }, |
| 12695 | { 0, true }, |
| 12696 | { 0, true }, |
| 12697 | { 0, true }, |
| 12698 | { 0, true }, |
| 12699 | { 0, true }, |
| 12700 | { 0, true }, |
| 12701 | { 0, true }, |
| 12702 | { 0, true }, |
| 12703 | { 0, true }, |
| 12704 | { 0, true }, |
| 12705 | { 0, true }, |
| 12706 | { 0, true }, |
| 12707 | { 0, true }, |
| 12708 | { 0, true }, |
| 12709 | { 0, true }, |
| 12710 | { 0, true }, |
| 12711 | { 0, true }, |
| 12712 | { 0, true }, |
| 12713 | { 0, true }, |
| 12714 | { 0, true }, |
| 12715 | { 0, true }, |
| 12716 | { 0, true }, |
| 12717 | { 0, true }, |
| 12718 | { 0, true }, |
| 12719 | { 0, true }, |
| 12720 | { 0, true }, |
| 12721 | { 0, true }, |
| 12722 | { 0, true }, |
| 12723 | { 0, true }, |
| 12724 | { 0, true }, |
| 12725 | { 0, true }, |
| 12726 | { 0, true }, |
| 12727 | { 0, true }, |
| 12728 | { 0, true }, |
| 12729 | { 0, true }, |
| 12730 | { 0, true }, |
| 12731 | { 0, true }, |
| 12732 | { 0, true }, |
| 12733 | { 0, true }, |
| 12734 | { 0, true }, |
| 12735 | { 0, true }, |
| 12736 | { 0, true }, |
| 12737 | { 0, true }, |
| 12738 | { 0, true }, |
| 12739 | { 0, true }, |
| 12740 | { 0, true }, |
| 12741 | { 0, true }, |
| 12742 | { 0, true }, |
| 12743 | { 0, true }, |
| 12744 | { 0, true }, |
| 12745 | { 0, true }, |
| 12746 | { 0, true }, |
| 12747 | { 0, true }, |
| 12748 | { 0, true }, |
| 12749 | { 0, true }, |
| 12750 | { 0, true }, |
| 12751 | { 0, true }, |
| 12752 | { 0, true }, |
| 12753 | { 0, true }, |
| 12754 | { 0, true }, |
| 12755 | { 0, true }, |
| 12756 | { 0, true }, |
| 12757 | { 0, true }, |
| 12758 | { 0, true }, |
| 12759 | { 0, true }, |
| 12760 | { 0, true }, |
| 12761 | { 0, true }, |
| 12762 | { 0, true }, |
| 12763 | { 0, true }, |
| 12764 | { 0, true }, |
| 12765 | { 0, true }, |
| 12766 | { 0, true }, |
| 12767 | { 0, true }, |
| 12768 | { 0, true }, |
| 12769 | { 0, true }, |
| 12770 | { 0, true }, |
| 12771 | { 0, true }, |
| 12772 | { 0, true }, |
| 12773 | { 0, true }, |
| 12774 | { 0, true }, |
| 12775 | { 0, true }, |
| 12776 | { 0, true }, |
| 12777 | { 0, true }, |
| 12778 | { 0, true }, |
| 12779 | { 0, true }, |
| 12780 | { 0, true }, |
| 12781 | { 0, true }, |
| 12782 | { 0, true }, |
| 12783 | { 0, true }, |
| 12784 | { 0, true }, |
| 12785 | { 0, true }, |
| 12786 | { 0, true }, |
| 12787 | { 0, true }, |
| 12788 | { 0, true }, |
| 12789 | { 0, true }, |
| 12790 | { 0, true }, |
| 12791 | { 0, true }, |
| 12792 | { 0, true }, |
| 12793 | { 0, true }, |
| 12794 | { 0, true }, |
| 12795 | { 0, true }, |
| 12796 | { 0, true }, |
| 12797 | { 0, true }, |
| 12798 | { 0, true }, |
| 12799 | { 0, true }, |
| 12800 | { 0, true }, |
| 12801 | { 0, true }, |
| 12802 | { 0, true }, |
| 12803 | { 0, true }, |
| 12804 | { 0, true }, |
| 12805 | { 0, true }, |
| 12806 | { 0, true }, |
| 12807 | { 0, true }, |
| 12808 | { 0, true }, |
| 12809 | { 0, true }, |
| 12810 | { 0, true }, |
| 12811 | { 0, true }, |
| 12812 | { 0, true }, |
| 12813 | { 0, true }, |
| 12814 | { 0, true }, |
| 12815 | { 0, true }, |
| 12816 | { 0, true }, |
| 12817 | { 0, true }, |
| 12818 | { 0, true }, |
| 12819 | { 0, true }, |
| 12820 | { 0, true }, |
| 12821 | { 0, true }, |
| 12822 | { 0, true }, |
| 12823 | { 0, true }, |
| 12824 | { 0, true }, |
| 12825 | { 0, true }, |
| 12826 | { 0, true }, |
| 12827 | { 0, true }, |
| 12828 | { 0, true }, |
| 12829 | { 0, true }, |
| 12830 | { 0, true }, |
| 12831 | { 0, true }, |
| 12832 | { 0, true }, |
| 12833 | { 0, true }, |
| 12834 | { 0, true }, |
| 12835 | { 0, true }, |
| 12836 | { 0, true }, |
| 12837 | { 0, true }, |
| 12838 | { 0, true }, |
| 12839 | { 0, true }, |
| 12840 | { 0, true }, |
| 12841 | { 0, true }, |
| 12842 | { 0, true }, |
| 12843 | { 0, true }, |
| 12844 | { 0, true }, |
| 12845 | { 0, true }, |
| 12846 | { 0, true }, |
| 12847 | { 0, true }, |
| 12848 | { 0, true }, |
| 12849 | { 0, true }, |
| 12850 | { 0, true }, |
| 12851 | { 0, true }, |
| 12852 | { 0, true }, |
| 12853 | { 0, true }, |
| 12854 | { 0, true }, |
| 12855 | { 0, true }, |
| 12856 | { 0, true }, |
| 12857 | { 0, true }, |
| 12858 | { 0, true }, |
| 12859 | { 0, true }, |
| 12860 | { 0, true }, |
| 12861 | { 0, true }, |
| 12862 | { 0, true }, |
| 12863 | { 0, true }, |
| 12864 | { 0, true }, |
| 12865 | { 0, true }, |
| 12866 | { 0, true }, |
| 12867 | { 0, true }, |
| 12868 | { 0, true }, |
| 12869 | { 0, true }, |
| 12870 | { 0, true }, |
| 12871 | { 0, true }, |
| 12872 | { 0, true }, |
| 12873 | { 0, true }, |
| 12874 | { 0, true }, |
| 12875 | { 0, true }, |
| 12876 | { 0, true }, |
| 12877 | { 0, true }, |
| 12878 | { 0, true }, |
| 12879 | { 0, true }, |
| 12880 | { 0, true }, |
| 12881 | { 0, true }, |
| 12882 | { 0, true }, |
| 12883 | { 0, true }, |
| 12884 | { 0, true }, |
| 12885 | { 0, true }, |
| 12886 | { 0, true }, |
| 12887 | { 0, true }, |
| 12888 | { 0, true }, |
| 12889 | { 0, true }, |
| 12890 | { 0, true }, |
| 12891 | { 0, true }, |
| 12892 | { 0, true }, |
| 12893 | { 0, true }, |
| 12894 | { 0, true }, |
| 12895 | { 0, true }, |
| 12896 | { 0, true }, |
| 12897 | { 0, true }, |
| 12898 | { 0, true }, |
| 12899 | { 0, true }, |
| 12900 | { 0, true }, |
| 12901 | { 0, true }, |
| 12902 | { 0, true }, |
| 12903 | { 0, true }, |
| 12904 | { 0, true }, |
| 12905 | { 0, true }, |
| 12906 | { 0, true }, |
| 12907 | { 0, true }, |
| 12908 | { 0, true }, |
| 12909 | { 0, true }, |
| 12910 | { 0, true }, |
| 12911 | { 0, true }, |
| 12912 | { 0, true }, |
| 12913 | { 0, true }, |
| 12914 | { 0, true }, |
| 12915 | { 0, true }, |
| 12916 | { 0, true }, |
| 12917 | { 0, true }, |
| 12918 | { 0, true }, |
| 12919 | { 0, true }, |
| 12920 | { 0, true }, |
| 12921 | { 0, true }, |
| 12922 | { 0, true }, |
| 12923 | { 0, true }, |
| 12924 | { 0, true }, |
| 12925 | { 0, true }, |
| 12926 | { 0, true }, |
| 12927 | { 0, true }, |
| 12928 | { 0, true }, |
| 12929 | { 0, true }, |
| 12930 | { 0, true }, |
| 12931 | { 0, true }, |
| 12932 | { 0, true }, |
| 12933 | { 0, true }, |
| 12934 | { 0, true }, |
| 12935 | { 0, true }, |
| 12936 | { 0, true }, |
| 12937 | { 0, true }, |
| 12938 | { 0, true }, |
| 12939 | { 0, true }, |
| 12940 | { 0, true }, |
| 12941 | { 0, true }, |
| 12942 | { 0, true }, |
| 12943 | { 0, true }, |
| 12944 | { 0, true }, |
| 12945 | { 0, true }, |
| 12946 | { 0, true }, |
| 12947 | { 0, true }, |
| 12948 | { 0, true }, |
| 12949 | { 0, true }, |
| 12950 | { 0, true }, |
| 12951 | { 0, true }, |
| 12952 | { 0, true }, |
| 12953 | { 0, true }, |
| 12954 | { 0, true }, |
| 12955 | { 0, true }, |
| 12956 | { 0, true }, |
| 12957 | { 0, true }, |
| 12958 | { 0, true }, |
| 12959 | { 0, true }, |
| 12960 | { 0, true }, |
| 12961 | { 0, true }, |
| 12962 | { 0, true }, |
| 12963 | { 0, true }, |
| 12964 | { 0, true }, |
| 12965 | { 0, true }, |
| 12966 | { 0, true }, |
| 12967 | { 0, true }, |
| 12968 | { 0, true }, |
| 12969 | { 0, true }, |
| 12970 | { 0, true }, |
| 12971 | { 0, true }, |
| 12972 | { 0, true }, |
| 12973 | { 0, true }, |
| 12974 | { 0, true }, |
| 12975 | { 0, true }, |
| 12976 | { 0, true }, |
| 12977 | { 0, true }, |
| 12978 | { 0, true }, |
| 12979 | { 0, true }, |
| 12980 | { 0, true }, |
| 12981 | { 0, true }, |
| 12982 | { 0, true }, |
| 12983 | { 0, true }, |
| 12984 | { 0, true }, |
| 12985 | { 0, true }, |
| 12986 | { 0, true }, |
| 12987 | { 0, true }, |
| 12988 | { 0, true }, |
| 12989 | { 0, true }, |
| 12990 | { 0, true }, |
| 12991 | { 0, true }, |
| 12992 | { 0, true }, |
| 12993 | { 0, true }, |
| 12994 | { 0, true }, |
| 12995 | { 0, true }, |
| 12996 | { 0, true }, |
| 12997 | { 0, true }, |
| 12998 | }; |
| 12999 | unsigned AArch64GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
| 13000 | static const uint8_t RowMap[122] = { |
| 13001 | 0, 0, 0, 1, 2, 3, 0, 0, 0, 0, 4, 5, 6, 0, 0, 0, 0, 0, 1, 0, 2, 3, 4, 5, 6, 7, 8, 0, 0, 7, 8, 9, 0, 0, 1, 1, 0, 3, 3, 0, 2, 2, 0, 4, 4, 4, 0, 6, 6, 6, 0, 5, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 7, 7, 0, 0, 9, 9, 9, 9, 0, 0, 8, 8, 8, 8, 0, 0, 0, 1, 1, 2, 10, 10, 10, 0, 0, 4, 4, 5, 4, 4, 5, 0, 0, 3, 5, 7, 1, 2, 3, 4, 11, 10, 11, 11, 10, 10, 0, 0, 7, 7, 8, 7, 7, 7, 7, 8, 8, |
| 13002 | }; |
| 13003 | static const uint8_t Rows[12][122] = { |
| 13004 | { AArch64::bsub, AArch64::dsub, AArch64::dsub0, AArch64::dsub1, AArch64::dsub2, 0, AArch64::hsub, 0, 0, AArch64::qsub0, AArch64::qsub1, AArch64::qsub2, 0, AArch64::ssub, AArch64::sub_32, AArch64::sub_32, AArch64::x8sub_0, AArch64::x8sub_1_then_sub_32, AArch64::x8sub_1, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub, AArch64::zsub0, AArch64::zsub1, AArch64::zsub2, 0, AArch64::zsub_hi, AArch64::dsub1_then_bsub, AArch64::dsub1_then_hsub, AArch64::dsub1_then_ssub, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_1_then_sub_32, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub1_then_zsub, AArch64::zsub1_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, AArch64::dsub0_dsub1, 0, AArch64::dsub1_dsub2, 0, 0, AArch64::dsub_qsub1_then_dsub, 0, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub0_qsub1, 0, AArch64::qsub1_qsub2, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::sub_32_x8sub_1_then_sub_32, AArch64::dsub_zsub1_then_dsub, AArch64::zsub_zsub1_then_zsub, 0, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub0_zsub1, 0, AArch64::zsub1_zsub2, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, 0, 0, }, |
| 13005 | { AArch64::dsub1_then_bsub, 0, AArch64::dsub1, AArch64::dsub2, AArch64::dsub3, 0, AArch64::dsub1_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::dsub1_then_ssub, AArch64::subo64_then_sub_32, AArch64::x8sub_6_then_sub_32, 0, AArch64::x8sub_7_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub2_then_bsub, AArch64::dsub2_then_hsub, AArch64::dsub2_then_ssub, 0, 0, 0, AArch64::dsub3_then_bsub, AArch64::dsub3_then_hsub, AArch64::dsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub1_dsub2, 0, AArch64::dsub2_dsub3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13006 | { AArch64::dsub2_then_bsub, 0, AArch64::dsub2, AArch64::dsub3, 0, 0, AArch64::dsub2_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::dsub2_then_ssub, AArch64::x8sub_1_then_sub_32, AArch64::x8sub_4_then_sub_32, 0, AArch64::x8sub_5_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub3_then_bsub, AArch64::dsub3_then_hsub, AArch64::dsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13007 | { AArch64::dsub3_then_bsub, 0, 0, 0, 0, 0, AArch64::dsub3_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::dsub3_then_ssub, AArch64::x8sub_2_then_sub_32, AArch64::x8sub_2_then_sub_32, AArch64::x8sub_2, AArch64::x8sub_3_then_sub_32, AArch64::x8sub_3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_3_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_2_then_sub_32_x8sub_3_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13008 | { AArch64::qsub1_then_bsub, AArch64::qsub1_then_dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, 0, AArch64::qsub1_then_hsub, 0, 0, AArch64::qsub1, AArch64::qsub2, AArch64::qsub3, 0, AArch64::qsub1_then_ssub, AArch64::x8sub_3_then_sub_32, AArch64::sub_32, 0, AArch64::subo64_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub2_then_bsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, 0, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_dsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, AArch64::qsub2_then_dsub_qsub3_then_dsub, 0, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub, 0, AArch64::qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, AArch64::qsub1_qsub2, 0, AArch64::qsub2_qsub3, 0, 0, AArch64::qsub2_then_dsub_qsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13009 | { AArch64::qsub2_then_bsub, AArch64::qsub2_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, 0, 0, AArch64::qsub2_then_hsub, 0, 0, AArch64::qsub2, AArch64::qsub3, 0, 0, AArch64::qsub2_then_ssub, AArch64::x8sub_4_then_sub_32, 0, AArch64::x8sub_4, 0, AArch64::x8sub_5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, AArch64::qsub3_then_bsub, AArch64::qsub3_then_dsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_5_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub2_then_dsub_qsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_4_then_sub_32_x8sub_5_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13010 | { AArch64::qsub3_then_bsub, AArch64::qsub3_then_dsub, 0, 0, 0, 0, AArch64::qsub3_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::qsub3_then_ssub, AArch64::x8sub_5_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13011 | { AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, 0, AArch64::zsub1_then_hsub, 0, 0, AArch64::zsub1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, 0, AArch64::zsub1_then_ssub, AArch64::x8sub_6_then_sub_32, 0, AArch64::x8sub_6, 0, AArch64::x8sub_7, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub1_then_zsub, AArch64::zsub1, AArch64::zsub2, AArch64::zsub3, 0, AArch64::zsub1_then_zsub_hi, AArch64::zsub2_then_bsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_7_then_sub_32, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, AArch64::zsub2_then_zsub, AArch64::zsub2_then_zsub_hi, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub3_then_zsub, AArch64::zsub3_then_zsub_hi, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, AArch64::zsub2_then_zsub_zsub3_then_zsub, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::x8sub_6_then_sub_32_x8sub_7_then_sub_32, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, 0, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, 0, AArch64::zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub1_zsub2, 0, AArch64::zsub2_zsub3, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, AArch64::zsub2_then_zsub_zsub3_then_zsub, 0, 0, 0, }, |
| 13012 | { AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, 0, 0, AArch64::zsub2_then_hsub, 0, 0, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, 0, 0, AArch64::zsub2_then_ssub, AArch64::x8sub_7_then_sub_32, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_zsub, AArch64::zsub2, AArch64::zsub3, 0, 0, AArch64::zsub2_then_zsub_hi, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub3_then_zsub, AArch64::zsub3_then_zsub_hi, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_zsub_zsub3_then_zsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13013 | { AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, 0, 0, 0, 0, AArch64::zsub3_then_hsub, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub3_then_zsub, 0, 0, 0, 0, AArch64::zsub3_then_zsub_hi, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13014 | { AArch64::bsub, AArch64::dsub, AArch64::dsub, AArch64::qsub1_then_dsub, AArch64::qsub2_then_dsub, AArch64::qsub3_then_dsub, AArch64::hsub, 0, 0, AArch64::zsub, AArch64::zsub1_then_zsub, AArch64::zsub2_then_zsub, AArch64::zsub3_then_zsub, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::qsub1_then_bsub, AArch64::qsub1_then_hsub, AArch64::qsub1_then_ssub, AArch64::qsub3_then_bsub, AArch64::qsub3_then_hsub, AArch64::qsub3_then_ssub, AArch64::qsub2_then_bsub, AArch64::qsub2_then_hsub, AArch64::qsub2_then_ssub, AArch64::zsub1_then_bsub, AArch64::zsub1_then_dsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_dsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_dsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_qsub1_then_dsub, AArch64::dsub_qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub, AArch64::qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, AArch64::qsub2_then_dsub_qsub3_then_dsub, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub_zsub1_then_zsub, AArch64::zsub_zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub, AArch64::zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub2_then_zsub_zsub3_then_zsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13015 | { AArch64::bsub, 0, AArch64::dsub, AArch64::zsub1_then_dsub, AArch64::zsub2_then_dsub, AArch64::zsub3_then_dsub, AArch64::hsub, 0, 0, 0, 0, 0, 0, AArch64::ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::zsub1_then_bsub, AArch64::zsub1_then_hsub, AArch64::zsub1_then_ssub, AArch64::zsub3_then_bsub, AArch64::zsub3_then_hsub, AArch64::zsub3_then_ssub, AArch64::zsub2_then_bsub, AArch64::zsub2_then_hsub, AArch64::zsub2_then_ssub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, AArch64::dsub_zsub1_then_dsub, AArch64::dsub_zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub, AArch64::zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub, AArch64::zsub2_then_dsub_zsub3_then_dsub, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }, |
| 13016 | }; |
| 13017 | |
| 13018 | --IdxA; assert(IdxA < 122); |
| 13019 | --IdxB; assert(IdxB < 122); |
| 13020 | return Rows[RowMap[IdxA]][IdxB]; |
| 13021 | } |
| 13022 | |
| 13023 | struct MaskRolOp { |
| 13024 | LaneBitmask Mask; |
| 13025 | uint8_t RotateLeft; |
| 13026 | }; |
| 13027 | static const MaskRolOp LaneMaskComposeSequences[] = { |
| 13028 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 |
| 13029 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 |
| 13030 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 |
| 13031 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 |
| 13032 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 |
| 13033 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 |
| 13034 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 12 |
| 13035 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 14 |
| 13036 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 16 |
| 13037 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 18 |
| 13038 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 20 |
| 13039 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 22 |
| 13040 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }, // Sequence 24 |
| 13041 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 26 |
| 13042 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 28 |
| 13043 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 30 |
| 13044 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 32 |
| 13045 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000040), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 34 |
| 13046 | { LaneBitmask(0x0000000000000001), 25 }, { LaneBitmask(0x0000000000000040), 20 }, { LaneBitmask::getNone(), 0 }, // Sequence 37 |
| 13047 | { LaneBitmask(0x0000000000000001), 23 }, { LaneBitmask(0x0000000000000040), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 40 |
| 13048 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 43 |
| 13049 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 45 |
| 13050 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 }, // Sequence 47 |
| 13051 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 20 }, { LaneBitmask::getNone(), 0 }, // Sequence 49 |
| 13052 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 21 }, { LaneBitmask::getNone(), 0 }, // Sequence 51 |
| 13053 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 22 }, { LaneBitmask::getNone(), 0 }, // Sequence 53 |
| 13054 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 23 }, { LaneBitmask::getNone(), 0 }, // Sequence 55 |
| 13055 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 24 }, { LaneBitmask::getNone(), 0 }, // Sequence 57 |
| 13056 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 25 }, { LaneBitmask::getNone(), 0 }, // Sequence 59 |
| 13057 | { LaneBitmask(0xFFFFFFFFFFFFFFFF), 26 }, { LaneBitmask::getNone(), 0 }, // Sequence 61 |
| 13058 | { LaneBitmask(0x0000000000000001), 7 }, { LaneBitmask(0x0000000000000080), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 63 |
| 13059 | { LaneBitmask(0x0000000000000001), 7 }, { LaneBitmask(0x0000000000000080), 2 }, { LaneBitmask(0x0000000000000200), 63 }, { LaneBitmask::getNone(), 0 }, // Sequence 66 |
| 13060 | { LaneBitmask(0x0000000000000001), 9 }, { LaneBitmask(0x0000000000000080), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 70 |
| 13061 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000080), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 73 |
| 13062 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000380), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 76 |
| 13063 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000280), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 79 |
| 13064 | { LaneBitmask(0x0000000000000001), 10 }, { LaneBitmask(0x0000000000000400), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 82 |
| 13065 | { LaneBitmask(0x0000000000000001), 10 }, { LaneBitmask(0x0000000000000400), 2 }, { LaneBitmask(0x0000000000001000), 63 }, { LaneBitmask::getNone(), 0 }, // Sequence 85 |
| 13066 | { LaneBitmask(0x0000000000000001), 12 }, { LaneBitmask(0x0000000000000400), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 89 |
| 13067 | { LaneBitmask(0x0000000000000001), 10 }, { LaneBitmask(0x0000000000000080), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 92 |
| 13068 | { LaneBitmask(0x0000000000000001), 10 }, { LaneBitmask(0x0000000000000080), 5 }, { LaneBitmask(0x0000000000000200), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 95 |
| 13069 | { LaneBitmask(0x0000000000000001), 12 }, { LaneBitmask(0x0000000000000080), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 99 |
| 13070 | { LaneBitmask(0x0000000000000010), 63 }, { LaneBitmask(0x0000000000000020), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 102 |
| 13071 | { LaneBitmask(0x0000000000000008), 0 }, { LaneBitmask(0x0000000000100000), 63 }, { LaneBitmask::getNone(), 0 }, // Sequence 105 |
| 13072 | { LaneBitmask(0x0000000000000008), 15 }, { LaneBitmask(0x0000000000100000), 61 }, { LaneBitmask::getNone(), 0 }, // Sequence 108 |
| 13073 | { LaneBitmask(0x0000000000000008), 13 }, { LaneBitmask(0x0000000000100000), 59 }, { LaneBitmask::getNone(), 0 }, // Sequence 111 |
| 13074 | { LaneBitmask(0x0000000000000008), 11 }, { LaneBitmask(0x0000000000100000), 57 }, { LaneBitmask::getNone(), 0 }, // Sequence 114 |
| 13075 | { LaneBitmask(0x0000000000000010), 10 }, { LaneBitmask(0x0000000000000020), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 117 |
| 13076 | { LaneBitmask(0x0000000000000010), 12 }, { LaneBitmask(0x0000000000000020), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 120 |
| 13077 | { LaneBitmask(0x0000000000000010), 14 }, { LaneBitmask(0x0000000000000020), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 123 |
| 13078 | { LaneBitmask(0x0000000000000010), 63 }, { LaneBitmask(0x0000000000000020), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 126 |
| 13079 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000080), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 129 |
| 13080 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000400), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 132 |
| 13081 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000080), 14 }, { LaneBitmask(0x0000000000000100), 15 }, { LaneBitmask(0x0000000000000200), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 135 |
| 13082 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000080), 14 }, { LaneBitmask(0x0000000000000200), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 140 |
| 13083 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000400), 11 }, { LaneBitmask(0x0000000000000800), 12 }, { LaneBitmask(0x0000000000001000), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 144 |
| 13084 | { LaneBitmask(0x0000000000000001), 0 }, { LaneBitmask(0x0000000000000400), 11 }, { LaneBitmask(0x0000000000001000), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 149 |
| 13085 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000040), 16 }, { LaneBitmask(0x0000000000600000), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 153 |
| 13086 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000040), 16 }, { LaneBitmask(0x0000000000600000), 4 }, { LaneBitmask(0x0000000006000000), 62 }, { LaneBitmask::getNone(), 0 }, // Sequence 157 |
| 13087 | { LaneBitmask(0x0000000000000001), 25 }, { LaneBitmask(0x0000000000000040), 20 }, { LaneBitmask(0x0000000000600000), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 162 |
| 13088 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000080), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 166 |
| 13089 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000080), 18 }, { LaneBitmask(0x0000000000000200), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 169 |
| 13090 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000400), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 173 |
| 13091 | { LaneBitmask(0x0000000000000001), 21 }, { LaneBitmask(0x0000000000000400), 15 }, { LaneBitmask(0x0000000000001000), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 176 |
| 13092 | { LaneBitmask(0x0000000000000001), 25 }, { LaneBitmask(0x0000000000000080), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 180 |
| 13093 | { LaneBitmask(0x0000000000000001), 25 }, { LaneBitmask(0x0000000000000400), 13 }, { LaneBitmask::getNone(), 0 } // Sequence 183 |
| 13094 | }; |
| 13095 | static const MaskRolOp *const CompositeSequences[] = { |
| 13096 | &LaneMaskComposeSequences[0], // to bsub |
| 13097 | &LaneMaskComposeSequences[0], // to dsub |
| 13098 | &LaneMaskComposeSequences[0], // to dsub0 |
| 13099 | &LaneMaskComposeSequences[2], // to dsub1 |
| 13100 | &LaneMaskComposeSequences[4], // to dsub2 |
| 13101 | &LaneMaskComposeSequences[6], // to dsub3 |
| 13102 | &LaneMaskComposeSequences[0], // to hsub |
| 13103 | &LaneMaskComposeSequences[8], // to qhisub |
| 13104 | &LaneMaskComposeSequences[10], // to qsub |
| 13105 | &LaneMaskComposeSequences[0], // to qsub0 |
| 13106 | &LaneMaskComposeSequences[12], // to qsub1 |
| 13107 | &LaneMaskComposeSequences[14], // to qsub2 |
| 13108 | &LaneMaskComposeSequences[16], // to qsub3 |
| 13109 | &LaneMaskComposeSequences[0], // to ssub |
| 13110 | &LaneMaskComposeSequences[18], // to sub_32 |
| 13111 | &LaneMaskComposeSequences[20], // to sube32 |
| 13112 | &LaneMaskComposeSequences[0], // to sube64 |
| 13113 | &LaneMaskComposeSequences[22], // to subo32 |
| 13114 | &LaneMaskComposeSequences[24], // to subo64 |
| 13115 | &LaneMaskComposeSequences[0], // to x8sub_0 |
| 13116 | &LaneMaskComposeSequences[26], // to x8sub_1 |
| 13117 | &LaneMaskComposeSequences[28], // to x8sub_2 |
| 13118 | &LaneMaskComposeSequences[30], // to x8sub_3 |
| 13119 | &LaneMaskComposeSequences[32], // to x8sub_4 |
| 13120 | &LaneMaskComposeSequences[14], // to x8sub_5 |
| 13121 | &LaneMaskComposeSequences[16], // to x8sub_6 |
| 13122 | &LaneMaskComposeSequences[12], // to x8sub_7 |
| 13123 | &LaneMaskComposeSequences[0], // to zsub |
| 13124 | &LaneMaskComposeSequences[0], // to zsub0 |
| 13125 | &LaneMaskComposeSequences[34], // to zsub1 |
| 13126 | &LaneMaskComposeSequences[37], // to zsub2 |
| 13127 | &LaneMaskComposeSequences[40], // to zsub3 |
| 13128 | &LaneMaskComposeSequences[43], // to zsub_hi |
| 13129 | &LaneMaskComposeSequences[2], // to dsub1_then_bsub |
| 13130 | &LaneMaskComposeSequences[2], // to dsub1_then_hsub |
| 13131 | &LaneMaskComposeSequences[2], // to dsub1_then_ssub |
| 13132 | &LaneMaskComposeSequences[6], // to dsub3_then_bsub |
| 13133 | &LaneMaskComposeSequences[6], // to dsub3_then_hsub |
| 13134 | &LaneMaskComposeSequences[6], // to dsub3_then_ssub |
| 13135 | &LaneMaskComposeSequences[4], // to dsub2_then_bsub |
| 13136 | &LaneMaskComposeSequences[4], // to dsub2_then_hsub |
| 13137 | &LaneMaskComposeSequences[4], // to dsub2_then_ssub |
| 13138 | &LaneMaskComposeSequences[12], // to qsub1_then_bsub |
| 13139 | &LaneMaskComposeSequences[12], // to qsub1_then_dsub |
| 13140 | &LaneMaskComposeSequences[12], // to qsub1_then_hsub |
| 13141 | &LaneMaskComposeSequences[12], // to qsub1_then_ssub |
| 13142 | &LaneMaskComposeSequences[16], // to qsub3_then_bsub |
| 13143 | &LaneMaskComposeSequences[16], // to qsub3_then_dsub |
| 13144 | &LaneMaskComposeSequences[16], // to qsub3_then_hsub |
| 13145 | &LaneMaskComposeSequences[16], // to qsub3_then_ssub |
| 13146 | &LaneMaskComposeSequences[14], // to qsub2_then_bsub |
| 13147 | &LaneMaskComposeSequences[14], // to qsub2_then_dsub |
| 13148 | &LaneMaskComposeSequences[14], // to qsub2_then_hsub |
| 13149 | &LaneMaskComposeSequences[14], // to qsub2_then_ssub |
| 13150 | &LaneMaskComposeSequences[32], // to x8sub_7_then_sub_32 |
| 13151 | &LaneMaskComposeSequences[30], // to x8sub_6_then_sub_32 |
| 13152 | &LaneMaskComposeSequences[28], // to x8sub_5_then_sub_32 |
| 13153 | &LaneMaskComposeSequences[26], // to x8sub_4_then_sub_32 |
| 13154 | &LaneMaskComposeSequences[24], // to x8sub_3_then_sub_32 |
| 13155 | &LaneMaskComposeSequences[45], // to x8sub_2_then_sub_32 |
| 13156 | &LaneMaskComposeSequences[47], // to x8sub_1_then_sub_32 |
| 13157 | &LaneMaskComposeSequences[49], // to subo64_then_sub_32 |
| 13158 | &LaneMaskComposeSequences[51], // to zsub1_then_bsub |
| 13159 | &LaneMaskComposeSequences[51], // to zsub1_then_dsub |
| 13160 | &LaneMaskComposeSequences[51], // to zsub1_then_hsub |
| 13161 | &LaneMaskComposeSequences[51], // to zsub1_then_ssub |
| 13162 | &LaneMaskComposeSequences[51], // to zsub1_then_zsub |
| 13163 | &LaneMaskComposeSequences[53], // to zsub1_then_zsub_hi |
| 13164 | &LaneMaskComposeSequences[55], // to zsub3_then_bsub |
| 13165 | &LaneMaskComposeSequences[55], // to zsub3_then_dsub |
| 13166 | &LaneMaskComposeSequences[55], // to zsub3_then_hsub |
| 13167 | &LaneMaskComposeSequences[55], // to zsub3_then_ssub |
| 13168 | &LaneMaskComposeSequences[55], // to zsub3_then_zsub |
| 13169 | &LaneMaskComposeSequences[57], // to zsub3_then_zsub_hi |
| 13170 | &LaneMaskComposeSequences[59], // to zsub2_then_bsub |
| 13171 | &LaneMaskComposeSequences[59], // to zsub2_then_dsub |
| 13172 | &LaneMaskComposeSequences[59], // to zsub2_then_hsub |
| 13173 | &LaneMaskComposeSequences[59], // to zsub2_then_ssub |
| 13174 | &LaneMaskComposeSequences[59], // to zsub2_then_zsub |
| 13175 | &LaneMaskComposeSequences[61], // to zsub2_then_zsub_hi |
| 13176 | &LaneMaskComposeSequences[0], // to dsub0_dsub1 |
| 13177 | &LaneMaskComposeSequences[0], // to dsub0_dsub1_dsub2 |
| 13178 | &LaneMaskComposeSequences[63], // to dsub1_dsub2 |
| 13179 | &LaneMaskComposeSequences[66], // to dsub1_dsub2_dsub3 |
| 13180 | &LaneMaskComposeSequences[70], // to dsub2_dsub3 |
| 13181 | &LaneMaskComposeSequences[73], // to dsub_qsub1_then_dsub |
| 13182 | &LaneMaskComposeSequences[76], // to dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13183 | &LaneMaskComposeSequences[79], // to dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13184 | &LaneMaskComposeSequences[0], // to qsub0_qsub1 |
| 13185 | &LaneMaskComposeSequences[0], // to qsub0_qsub1_qsub2 |
| 13186 | &LaneMaskComposeSequences[82], // to qsub1_qsub2 |
| 13187 | &LaneMaskComposeSequences[85], // to qsub1_qsub2_qsub3 |
| 13188 | &LaneMaskComposeSequences[89], // to qsub2_qsub3 |
| 13189 | &LaneMaskComposeSequences[92], // to qsub1_then_dsub_qsub2_then_dsub |
| 13190 | &LaneMaskComposeSequences[95], // to qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13191 | &LaneMaskComposeSequences[99], // to qsub2_then_dsub_qsub3_then_dsub |
| 13192 | &LaneMaskComposeSequences[102], // to sub_32_x8sub_1_then_sub_32 |
| 13193 | &LaneMaskComposeSequences[105], // to x8sub_0_x8sub_1 |
| 13194 | &LaneMaskComposeSequences[108], // to x8sub_2_x8sub_3 |
| 13195 | &LaneMaskComposeSequences[111], // to x8sub_4_x8sub_5 |
| 13196 | &LaneMaskComposeSequences[114], // to x8sub_6_x8sub_7 |
| 13197 | &LaneMaskComposeSequences[117], // to x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13198 | &LaneMaskComposeSequences[120], // to x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13199 | &LaneMaskComposeSequences[123], // to x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13200 | &LaneMaskComposeSequences[126], // to sub_32_subo64_then_sub_32 |
| 13201 | &LaneMaskComposeSequences[129], // to dsub_zsub1_then_dsub |
| 13202 | &LaneMaskComposeSequences[132], // to zsub_zsub1_then_zsub |
| 13203 | &LaneMaskComposeSequences[135], // to dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13204 | &LaneMaskComposeSequences[140], // to dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13205 | &LaneMaskComposeSequences[144], // to zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13206 | &LaneMaskComposeSequences[149], // to zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13207 | &LaneMaskComposeSequences[0], // to zsub0_zsub1 |
| 13208 | &LaneMaskComposeSequences[0], // to zsub0_zsub1_zsub2 |
| 13209 | &LaneMaskComposeSequences[153], // to zsub1_zsub2 |
| 13210 | &LaneMaskComposeSequences[157], // to zsub1_zsub2_zsub3 |
| 13211 | &LaneMaskComposeSequences[162], // to zsub2_zsub3 |
| 13212 | &LaneMaskComposeSequences[166], // to zsub1_then_dsub_zsub2_then_dsub |
| 13213 | &LaneMaskComposeSequences[169], // to zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13214 | &LaneMaskComposeSequences[173], // to zsub1_then_zsub_zsub2_then_zsub |
| 13215 | &LaneMaskComposeSequences[176], // to zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13216 | &LaneMaskComposeSequences[180], // to zsub2_then_dsub_zsub3_then_dsub |
| 13217 | &LaneMaskComposeSequences[183] // to zsub2_then_zsub_zsub3_then_zsub |
| 13218 | }; |
| 13219 | |
| 13220 | LaneBitmask AArch64GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| 13221 | --IdxA; assert(IdxA < 122 && "Subregister index out of bounds" ); |
| 13222 | LaneBitmask Result; |
| 13223 | for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| 13224 | LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
| 13225 | if (unsigned S = Ops->RotateLeft) |
| 13226 | Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
| 13227 | else |
| 13228 | Result |= LaneBitmask(M); |
| 13229 | } |
| 13230 | return Result; |
| 13231 | } |
| 13232 | |
| 13233 | LaneBitmask AArch64GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| 13234 | LaneMask &= getSubRegIndexLaneMask(IdxA); |
| 13235 | --IdxA; assert(IdxA < 122 && "Subregister index out of bounds" ); |
| 13236 | LaneBitmask Result; |
| 13237 | for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| 13238 | LaneBitmask::Type M = LaneMask.getAsInteger(); |
| 13239 | if (unsigned S = Ops->RotateLeft) |
| 13240 | Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
| 13241 | else |
| 13242 | Result |= LaneBitmask(M); |
| 13243 | } |
| 13244 | return Result; |
| 13245 | } |
| 13246 | |
| 13247 | const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
| 13248 | static const uint8_t Table[186][122] = { |
| 13249 | { // FPR8 |
| 13250 | 0, // bsub |
| 13251 | 0, // dsub |
| 13252 | 0, // dsub0 |
| 13253 | 0, // dsub1 |
| 13254 | 0, // dsub2 |
| 13255 | 0, // dsub3 |
| 13256 | 0, // hsub |
| 13257 | 0, // qhisub |
| 13258 | 0, // qsub |
| 13259 | 0, // qsub0 |
| 13260 | 0, // qsub1 |
| 13261 | 0, // qsub2 |
| 13262 | 0, // qsub3 |
| 13263 | 0, // ssub |
| 13264 | 0, // sub_32 |
| 13265 | 0, // sube32 |
| 13266 | 0, // sube64 |
| 13267 | 0, // subo32 |
| 13268 | 0, // subo64 |
| 13269 | 0, // x8sub_0 |
| 13270 | 0, // x8sub_1 |
| 13271 | 0, // x8sub_2 |
| 13272 | 0, // x8sub_3 |
| 13273 | 0, // x8sub_4 |
| 13274 | 0, // x8sub_5 |
| 13275 | 0, // x8sub_6 |
| 13276 | 0, // x8sub_7 |
| 13277 | 0, // zsub |
| 13278 | 0, // zsub0 |
| 13279 | 0, // zsub1 |
| 13280 | 0, // zsub2 |
| 13281 | 0, // zsub3 |
| 13282 | 0, // zsub_hi |
| 13283 | 0, // dsub1_then_bsub |
| 13284 | 0, // dsub1_then_hsub |
| 13285 | 0, // dsub1_then_ssub |
| 13286 | 0, // dsub3_then_bsub |
| 13287 | 0, // dsub3_then_hsub |
| 13288 | 0, // dsub3_then_ssub |
| 13289 | 0, // dsub2_then_bsub |
| 13290 | 0, // dsub2_then_hsub |
| 13291 | 0, // dsub2_then_ssub |
| 13292 | 0, // qsub1_then_bsub |
| 13293 | 0, // qsub1_then_dsub |
| 13294 | 0, // qsub1_then_hsub |
| 13295 | 0, // qsub1_then_ssub |
| 13296 | 0, // qsub3_then_bsub |
| 13297 | 0, // qsub3_then_dsub |
| 13298 | 0, // qsub3_then_hsub |
| 13299 | 0, // qsub3_then_ssub |
| 13300 | 0, // qsub2_then_bsub |
| 13301 | 0, // qsub2_then_dsub |
| 13302 | 0, // qsub2_then_hsub |
| 13303 | 0, // qsub2_then_ssub |
| 13304 | 0, // x8sub_7_then_sub_32 |
| 13305 | 0, // x8sub_6_then_sub_32 |
| 13306 | 0, // x8sub_5_then_sub_32 |
| 13307 | 0, // x8sub_4_then_sub_32 |
| 13308 | 0, // x8sub_3_then_sub_32 |
| 13309 | 0, // x8sub_2_then_sub_32 |
| 13310 | 0, // x8sub_1_then_sub_32 |
| 13311 | 0, // subo64_then_sub_32 |
| 13312 | 0, // zsub1_then_bsub |
| 13313 | 0, // zsub1_then_dsub |
| 13314 | 0, // zsub1_then_hsub |
| 13315 | 0, // zsub1_then_ssub |
| 13316 | 0, // zsub1_then_zsub |
| 13317 | 0, // zsub1_then_zsub_hi |
| 13318 | 0, // zsub3_then_bsub |
| 13319 | 0, // zsub3_then_dsub |
| 13320 | 0, // zsub3_then_hsub |
| 13321 | 0, // zsub3_then_ssub |
| 13322 | 0, // zsub3_then_zsub |
| 13323 | 0, // zsub3_then_zsub_hi |
| 13324 | 0, // zsub2_then_bsub |
| 13325 | 0, // zsub2_then_dsub |
| 13326 | 0, // zsub2_then_hsub |
| 13327 | 0, // zsub2_then_ssub |
| 13328 | 0, // zsub2_then_zsub |
| 13329 | 0, // zsub2_then_zsub_hi |
| 13330 | 0, // dsub0_dsub1 |
| 13331 | 0, // dsub0_dsub1_dsub2 |
| 13332 | 0, // dsub1_dsub2 |
| 13333 | 0, // dsub1_dsub2_dsub3 |
| 13334 | 0, // dsub2_dsub3 |
| 13335 | 0, // dsub_qsub1_then_dsub |
| 13336 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13337 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13338 | 0, // qsub0_qsub1 |
| 13339 | 0, // qsub0_qsub1_qsub2 |
| 13340 | 0, // qsub1_qsub2 |
| 13341 | 0, // qsub1_qsub2_qsub3 |
| 13342 | 0, // qsub2_qsub3 |
| 13343 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 13344 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13345 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 13346 | 0, // sub_32_x8sub_1_then_sub_32 |
| 13347 | 0, // x8sub_0_x8sub_1 |
| 13348 | 0, // x8sub_2_x8sub_3 |
| 13349 | 0, // x8sub_4_x8sub_5 |
| 13350 | 0, // x8sub_6_x8sub_7 |
| 13351 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13352 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13353 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13354 | 0, // sub_32_subo64_then_sub_32 |
| 13355 | 0, // dsub_zsub1_then_dsub |
| 13356 | 0, // zsub_zsub1_then_zsub |
| 13357 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13358 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13359 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13360 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13361 | 0, // zsub0_zsub1 |
| 13362 | 0, // zsub0_zsub1_zsub2 |
| 13363 | 0, // zsub1_zsub2 |
| 13364 | 0, // zsub1_zsub2_zsub3 |
| 13365 | 0, // zsub2_zsub3 |
| 13366 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 13367 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13368 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 13369 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13370 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 13371 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 13372 | }, |
| 13373 | { // FPR16 |
| 13374 | 2, // bsub -> FPR16 |
| 13375 | 0, // dsub |
| 13376 | 0, // dsub0 |
| 13377 | 0, // dsub1 |
| 13378 | 0, // dsub2 |
| 13379 | 0, // dsub3 |
| 13380 | 0, // hsub |
| 13381 | 0, // qhisub |
| 13382 | 0, // qsub |
| 13383 | 0, // qsub0 |
| 13384 | 0, // qsub1 |
| 13385 | 0, // qsub2 |
| 13386 | 0, // qsub3 |
| 13387 | 0, // ssub |
| 13388 | 0, // sub_32 |
| 13389 | 0, // sube32 |
| 13390 | 0, // sube64 |
| 13391 | 0, // subo32 |
| 13392 | 0, // subo64 |
| 13393 | 0, // x8sub_0 |
| 13394 | 0, // x8sub_1 |
| 13395 | 0, // x8sub_2 |
| 13396 | 0, // x8sub_3 |
| 13397 | 0, // x8sub_4 |
| 13398 | 0, // x8sub_5 |
| 13399 | 0, // x8sub_6 |
| 13400 | 0, // x8sub_7 |
| 13401 | 0, // zsub |
| 13402 | 0, // zsub0 |
| 13403 | 0, // zsub1 |
| 13404 | 0, // zsub2 |
| 13405 | 0, // zsub3 |
| 13406 | 0, // zsub_hi |
| 13407 | 0, // dsub1_then_bsub |
| 13408 | 0, // dsub1_then_hsub |
| 13409 | 0, // dsub1_then_ssub |
| 13410 | 0, // dsub3_then_bsub |
| 13411 | 0, // dsub3_then_hsub |
| 13412 | 0, // dsub3_then_ssub |
| 13413 | 0, // dsub2_then_bsub |
| 13414 | 0, // dsub2_then_hsub |
| 13415 | 0, // dsub2_then_ssub |
| 13416 | 0, // qsub1_then_bsub |
| 13417 | 0, // qsub1_then_dsub |
| 13418 | 0, // qsub1_then_hsub |
| 13419 | 0, // qsub1_then_ssub |
| 13420 | 0, // qsub3_then_bsub |
| 13421 | 0, // qsub3_then_dsub |
| 13422 | 0, // qsub3_then_hsub |
| 13423 | 0, // qsub3_then_ssub |
| 13424 | 0, // qsub2_then_bsub |
| 13425 | 0, // qsub2_then_dsub |
| 13426 | 0, // qsub2_then_hsub |
| 13427 | 0, // qsub2_then_ssub |
| 13428 | 0, // x8sub_7_then_sub_32 |
| 13429 | 0, // x8sub_6_then_sub_32 |
| 13430 | 0, // x8sub_5_then_sub_32 |
| 13431 | 0, // x8sub_4_then_sub_32 |
| 13432 | 0, // x8sub_3_then_sub_32 |
| 13433 | 0, // x8sub_2_then_sub_32 |
| 13434 | 0, // x8sub_1_then_sub_32 |
| 13435 | 0, // subo64_then_sub_32 |
| 13436 | 0, // zsub1_then_bsub |
| 13437 | 0, // zsub1_then_dsub |
| 13438 | 0, // zsub1_then_hsub |
| 13439 | 0, // zsub1_then_ssub |
| 13440 | 0, // zsub1_then_zsub |
| 13441 | 0, // zsub1_then_zsub_hi |
| 13442 | 0, // zsub3_then_bsub |
| 13443 | 0, // zsub3_then_dsub |
| 13444 | 0, // zsub3_then_hsub |
| 13445 | 0, // zsub3_then_ssub |
| 13446 | 0, // zsub3_then_zsub |
| 13447 | 0, // zsub3_then_zsub_hi |
| 13448 | 0, // zsub2_then_bsub |
| 13449 | 0, // zsub2_then_dsub |
| 13450 | 0, // zsub2_then_hsub |
| 13451 | 0, // zsub2_then_ssub |
| 13452 | 0, // zsub2_then_zsub |
| 13453 | 0, // zsub2_then_zsub_hi |
| 13454 | 0, // dsub0_dsub1 |
| 13455 | 0, // dsub0_dsub1_dsub2 |
| 13456 | 0, // dsub1_dsub2 |
| 13457 | 0, // dsub1_dsub2_dsub3 |
| 13458 | 0, // dsub2_dsub3 |
| 13459 | 0, // dsub_qsub1_then_dsub |
| 13460 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13461 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13462 | 0, // qsub0_qsub1 |
| 13463 | 0, // qsub0_qsub1_qsub2 |
| 13464 | 0, // qsub1_qsub2 |
| 13465 | 0, // qsub1_qsub2_qsub3 |
| 13466 | 0, // qsub2_qsub3 |
| 13467 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 13468 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13469 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 13470 | 0, // sub_32_x8sub_1_then_sub_32 |
| 13471 | 0, // x8sub_0_x8sub_1 |
| 13472 | 0, // x8sub_2_x8sub_3 |
| 13473 | 0, // x8sub_4_x8sub_5 |
| 13474 | 0, // x8sub_6_x8sub_7 |
| 13475 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13476 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13477 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13478 | 0, // sub_32_subo64_then_sub_32 |
| 13479 | 0, // dsub_zsub1_then_dsub |
| 13480 | 0, // zsub_zsub1_then_zsub |
| 13481 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13482 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13483 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13484 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13485 | 0, // zsub0_zsub1 |
| 13486 | 0, // zsub0_zsub1_zsub2 |
| 13487 | 0, // zsub1_zsub2 |
| 13488 | 0, // zsub1_zsub2_zsub3 |
| 13489 | 0, // zsub2_zsub3 |
| 13490 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 13491 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13492 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 13493 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13494 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 13495 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 13496 | }, |
| 13497 | { // FPR16_lo |
| 13498 | 3, // bsub -> FPR16_lo |
| 13499 | 0, // dsub |
| 13500 | 0, // dsub0 |
| 13501 | 0, // dsub1 |
| 13502 | 0, // dsub2 |
| 13503 | 0, // dsub3 |
| 13504 | 0, // hsub |
| 13505 | 0, // qhisub |
| 13506 | 0, // qsub |
| 13507 | 0, // qsub0 |
| 13508 | 0, // qsub1 |
| 13509 | 0, // qsub2 |
| 13510 | 0, // qsub3 |
| 13511 | 0, // ssub |
| 13512 | 0, // sub_32 |
| 13513 | 0, // sube32 |
| 13514 | 0, // sube64 |
| 13515 | 0, // subo32 |
| 13516 | 0, // subo64 |
| 13517 | 0, // x8sub_0 |
| 13518 | 0, // x8sub_1 |
| 13519 | 0, // x8sub_2 |
| 13520 | 0, // x8sub_3 |
| 13521 | 0, // x8sub_4 |
| 13522 | 0, // x8sub_5 |
| 13523 | 0, // x8sub_6 |
| 13524 | 0, // x8sub_7 |
| 13525 | 0, // zsub |
| 13526 | 0, // zsub0 |
| 13527 | 0, // zsub1 |
| 13528 | 0, // zsub2 |
| 13529 | 0, // zsub3 |
| 13530 | 0, // zsub_hi |
| 13531 | 0, // dsub1_then_bsub |
| 13532 | 0, // dsub1_then_hsub |
| 13533 | 0, // dsub1_then_ssub |
| 13534 | 0, // dsub3_then_bsub |
| 13535 | 0, // dsub3_then_hsub |
| 13536 | 0, // dsub3_then_ssub |
| 13537 | 0, // dsub2_then_bsub |
| 13538 | 0, // dsub2_then_hsub |
| 13539 | 0, // dsub2_then_ssub |
| 13540 | 0, // qsub1_then_bsub |
| 13541 | 0, // qsub1_then_dsub |
| 13542 | 0, // qsub1_then_hsub |
| 13543 | 0, // qsub1_then_ssub |
| 13544 | 0, // qsub3_then_bsub |
| 13545 | 0, // qsub3_then_dsub |
| 13546 | 0, // qsub3_then_hsub |
| 13547 | 0, // qsub3_then_ssub |
| 13548 | 0, // qsub2_then_bsub |
| 13549 | 0, // qsub2_then_dsub |
| 13550 | 0, // qsub2_then_hsub |
| 13551 | 0, // qsub2_then_ssub |
| 13552 | 0, // x8sub_7_then_sub_32 |
| 13553 | 0, // x8sub_6_then_sub_32 |
| 13554 | 0, // x8sub_5_then_sub_32 |
| 13555 | 0, // x8sub_4_then_sub_32 |
| 13556 | 0, // x8sub_3_then_sub_32 |
| 13557 | 0, // x8sub_2_then_sub_32 |
| 13558 | 0, // x8sub_1_then_sub_32 |
| 13559 | 0, // subo64_then_sub_32 |
| 13560 | 0, // zsub1_then_bsub |
| 13561 | 0, // zsub1_then_dsub |
| 13562 | 0, // zsub1_then_hsub |
| 13563 | 0, // zsub1_then_ssub |
| 13564 | 0, // zsub1_then_zsub |
| 13565 | 0, // zsub1_then_zsub_hi |
| 13566 | 0, // zsub3_then_bsub |
| 13567 | 0, // zsub3_then_dsub |
| 13568 | 0, // zsub3_then_hsub |
| 13569 | 0, // zsub3_then_ssub |
| 13570 | 0, // zsub3_then_zsub |
| 13571 | 0, // zsub3_then_zsub_hi |
| 13572 | 0, // zsub2_then_bsub |
| 13573 | 0, // zsub2_then_dsub |
| 13574 | 0, // zsub2_then_hsub |
| 13575 | 0, // zsub2_then_ssub |
| 13576 | 0, // zsub2_then_zsub |
| 13577 | 0, // zsub2_then_zsub_hi |
| 13578 | 0, // dsub0_dsub1 |
| 13579 | 0, // dsub0_dsub1_dsub2 |
| 13580 | 0, // dsub1_dsub2 |
| 13581 | 0, // dsub1_dsub2_dsub3 |
| 13582 | 0, // dsub2_dsub3 |
| 13583 | 0, // dsub_qsub1_then_dsub |
| 13584 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13585 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13586 | 0, // qsub0_qsub1 |
| 13587 | 0, // qsub0_qsub1_qsub2 |
| 13588 | 0, // qsub1_qsub2 |
| 13589 | 0, // qsub1_qsub2_qsub3 |
| 13590 | 0, // qsub2_qsub3 |
| 13591 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 13592 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13593 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 13594 | 0, // sub_32_x8sub_1_then_sub_32 |
| 13595 | 0, // x8sub_0_x8sub_1 |
| 13596 | 0, // x8sub_2_x8sub_3 |
| 13597 | 0, // x8sub_4_x8sub_5 |
| 13598 | 0, // x8sub_6_x8sub_7 |
| 13599 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13600 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13601 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13602 | 0, // sub_32_subo64_then_sub_32 |
| 13603 | 0, // dsub_zsub1_then_dsub |
| 13604 | 0, // zsub_zsub1_then_zsub |
| 13605 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13606 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13607 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13608 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13609 | 0, // zsub0_zsub1 |
| 13610 | 0, // zsub0_zsub1_zsub2 |
| 13611 | 0, // zsub1_zsub2 |
| 13612 | 0, // zsub1_zsub2_zsub3 |
| 13613 | 0, // zsub2_zsub3 |
| 13614 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 13615 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13616 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 13617 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13618 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 13619 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 13620 | }, |
| 13621 | { // PPR |
| 13622 | 0, // bsub |
| 13623 | 0, // dsub |
| 13624 | 0, // dsub0 |
| 13625 | 0, // dsub1 |
| 13626 | 0, // dsub2 |
| 13627 | 0, // dsub3 |
| 13628 | 0, // hsub |
| 13629 | 0, // qhisub |
| 13630 | 0, // qsub |
| 13631 | 0, // qsub0 |
| 13632 | 0, // qsub1 |
| 13633 | 0, // qsub2 |
| 13634 | 0, // qsub3 |
| 13635 | 0, // ssub |
| 13636 | 0, // sub_32 |
| 13637 | 0, // sube32 |
| 13638 | 0, // sube64 |
| 13639 | 0, // subo32 |
| 13640 | 0, // subo64 |
| 13641 | 0, // x8sub_0 |
| 13642 | 0, // x8sub_1 |
| 13643 | 0, // x8sub_2 |
| 13644 | 0, // x8sub_3 |
| 13645 | 0, // x8sub_4 |
| 13646 | 0, // x8sub_5 |
| 13647 | 0, // x8sub_6 |
| 13648 | 0, // x8sub_7 |
| 13649 | 0, // zsub |
| 13650 | 0, // zsub0 |
| 13651 | 0, // zsub1 |
| 13652 | 0, // zsub2 |
| 13653 | 0, // zsub3 |
| 13654 | 0, // zsub_hi |
| 13655 | 0, // dsub1_then_bsub |
| 13656 | 0, // dsub1_then_hsub |
| 13657 | 0, // dsub1_then_ssub |
| 13658 | 0, // dsub3_then_bsub |
| 13659 | 0, // dsub3_then_hsub |
| 13660 | 0, // dsub3_then_ssub |
| 13661 | 0, // dsub2_then_bsub |
| 13662 | 0, // dsub2_then_hsub |
| 13663 | 0, // dsub2_then_ssub |
| 13664 | 0, // qsub1_then_bsub |
| 13665 | 0, // qsub1_then_dsub |
| 13666 | 0, // qsub1_then_hsub |
| 13667 | 0, // qsub1_then_ssub |
| 13668 | 0, // qsub3_then_bsub |
| 13669 | 0, // qsub3_then_dsub |
| 13670 | 0, // qsub3_then_hsub |
| 13671 | 0, // qsub3_then_ssub |
| 13672 | 0, // qsub2_then_bsub |
| 13673 | 0, // qsub2_then_dsub |
| 13674 | 0, // qsub2_then_hsub |
| 13675 | 0, // qsub2_then_ssub |
| 13676 | 0, // x8sub_7_then_sub_32 |
| 13677 | 0, // x8sub_6_then_sub_32 |
| 13678 | 0, // x8sub_5_then_sub_32 |
| 13679 | 0, // x8sub_4_then_sub_32 |
| 13680 | 0, // x8sub_3_then_sub_32 |
| 13681 | 0, // x8sub_2_then_sub_32 |
| 13682 | 0, // x8sub_1_then_sub_32 |
| 13683 | 0, // subo64_then_sub_32 |
| 13684 | 0, // zsub1_then_bsub |
| 13685 | 0, // zsub1_then_dsub |
| 13686 | 0, // zsub1_then_hsub |
| 13687 | 0, // zsub1_then_ssub |
| 13688 | 0, // zsub1_then_zsub |
| 13689 | 0, // zsub1_then_zsub_hi |
| 13690 | 0, // zsub3_then_bsub |
| 13691 | 0, // zsub3_then_dsub |
| 13692 | 0, // zsub3_then_hsub |
| 13693 | 0, // zsub3_then_ssub |
| 13694 | 0, // zsub3_then_zsub |
| 13695 | 0, // zsub3_then_zsub_hi |
| 13696 | 0, // zsub2_then_bsub |
| 13697 | 0, // zsub2_then_dsub |
| 13698 | 0, // zsub2_then_hsub |
| 13699 | 0, // zsub2_then_ssub |
| 13700 | 0, // zsub2_then_zsub |
| 13701 | 0, // zsub2_then_zsub_hi |
| 13702 | 0, // dsub0_dsub1 |
| 13703 | 0, // dsub0_dsub1_dsub2 |
| 13704 | 0, // dsub1_dsub2 |
| 13705 | 0, // dsub1_dsub2_dsub3 |
| 13706 | 0, // dsub2_dsub3 |
| 13707 | 0, // dsub_qsub1_then_dsub |
| 13708 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13709 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13710 | 0, // qsub0_qsub1 |
| 13711 | 0, // qsub0_qsub1_qsub2 |
| 13712 | 0, // qsub1_qsub2 |
| 13713 | 0, // qsub1_qsub2_qsub3 |
| 13714 | 0, // qsub2_qsub3 |
| 13715 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 13716 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13717 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 13718 | 0, // sub_32_x8sub_1_then_sub_32 |
| 13719 | 0, // x8sub_0_x8sub_1 |
| 13720 | 0, // x8sub_2_x8sub_3 |
| 13721 | 0, // x8sub_4_x8sub_5 |
| 13722 | 0, // x8sub_6_x8sub_7 |
| 13723 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13724 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13725 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13726 | 0, // sub_32_subo64_then_sub_32 |
| 13727 | 0, // dsub_zsub1_then_dsub |
| 13728 | 0, // zsub_zsub1_then_zsub |
| 13729 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13730 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13731 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13732 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13733 | 0, // zsub0_zsub1 |
| 13734 | 0, // zsub0_zsub1_zsub2 |
| 13735 | 0, // zsub1_zsub2 |
| 13736 | 0, // zsub1_zsub2_zsub3 |
| 13737 | 0, // zsub2_zsub3 |
| 13738 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 13739 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13740 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 13741 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13742 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 13743 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 13744 | }, |
| 13745 | { // PPR_3b |
| 13746 | 0, // bsub |
| 13747 | 0, // dsub |
| 13748 | 0, // dsub0 |
| 13749 | 0, // dsub1 |
| 13750 | 0, // dsub2 |
| 13751 | 0, // dsub3 |
| 13752 | 0, // hsub |
| 13753 | 0, // qhisub |
| 13754 | 0, // qsub |
| 13755 | 0, // qsub0 |
| 13756 | 0, // qsub1 |
| 13757 | 0, // qsub2 |
| 13758 | 0, // qsub3 |
| 13759 | 0, // ssub |
| 13760 | 0, // sub_32 |
| 13761 | 0, // sube32 |
| 13762 | 0, // sube64 |
| 13763 | 0, // subo32 |
| 13764 | 0, // subo64 |
| 13765 | 0, // x8sub_0 |
| 13766 | 0, // x8sub_1 |
| 13767 | 0, // x8sub_2 |
| 13768 | 0, // x8sub_3 |
| 13769 | 0, // x8sub_4 |
| 13770 | 0, // x8sub_5 |
| 13771 | 0, // x8sub_6 |
| 13772 | 0, // x8sub_7 |
| 13773 | 0, // zsub |
| 13774 | 0, // zsub0 |
| 13775 | 0, // zsub1 |
| 13776 | 0, // zsub2 |
| 13777 | 0, // zsub3 |
| 13778 | 0, // zsub_hi |
| 13779 | 0, // dsub1_then_bsub |
| 13780 | 0, // dsub1_then_hsub |
| 13781 | 0, // dsub1_then_ssub |
| 13782 | 0, // dsub3_then_bsub |
| 13783 | 0, // dsub3_then_hsub |
| 13784 | 0, // dsub3_then_ssub |
| 13785 | 0, // dsub2_then_bsub |
| 13786 | 0, // dsub2_then_hsub |
| 13787 | 0, // dsub2_then_ssub |
| 13788 | 0, // qsub1_then_bsub |
| 13789 | 0, // qsub1_then_dsub |
| 13790 | 0, // qsub1_then_hsub |
| 13791 | 0, // qsub1_then_ssub |
| 13792 | 0, // qsub3_then_bsub |
| 13793 | 0, // qsub3_then_dsub |
| 13794 | 0, // qsub3_then_hsub |
| 13795 | 0, // qsub3_then_ssub |
| 13796 | 0, // qsub2_then_bsub |
| 13797 | 0, // qsub2_then_dsub |
| 13798 | 0, // qsub2_then_hsub |
| 13799 | 0, // qsub2_then_ssub |
| 13800 | 0, // x8sub_7_then_sub_32 |
| 13801 | 0, // x8sub_6_then_sub_32 |
| 13802 | 0, // x8sub_5_then_sub_32 |
| 13803 | 0, // x8sub_4_then_sub_32 |
| 13804 | 0, // x8sub_3_then_sub_32 |
| 13805 | 0, // x8sub_2_then_sub_32 |
| 13806 | 0, // x8sub_1_then_sub_32 |
| 13807 | 0, // subo64_then_sub_32 |
| 13808 | 0, // zsub1_then_bsub |
| 13809 | 0, // zsub1_then_dsub |
| 13810 | 0, // zsub1_then_hsub |
| 13811 | 0, // zsub1_then_ssub |
| 13812 | 0, // zsub1_then_zsub |
| 13813 | 0, // zsub1_then_zsub_hi |
| 13814 | 0, // zsub3_then_bsub |
| 13815 | 0, // zsub3_then_dsub |
| 13816 | 0, // zsub3_then_hsub |
| 13817 | 0, // zsub3_then_ssub |
| 13818 | 0, // zsub3_then_zsub |
| 13819 | 0, // zsub3_then_zsub_hi |
| 13820 | 0, // zsub2_then_bsub |
| 13821 | 0, // zsub2_then_dsub |
| 13822 | 0, // zsub2_then_hsub |
| 13823 | 0, // zsub2_then_ssub |
| 13824 | 0, // zsub2_then_zsub |
| 13825 | 0, // zsub2_then_zsub_hi |
| 13826 | 0, // dsub0_dsub1 |
| 13827 | 0, // dsub0_dsub1_dsub2 |
| 13828 | 0, // dsub1_dsub2 |
| 13829 | 0, // dsub1_dsub2_dsub3 |
| 13830 | 0, // dsub2_dsub3 |
| 13831 | 0, // dsub_qsub1_then_dsub |
| 13832 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13833 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13834 | 0, // qsub0_qsub1 |
| 13835 | 0, // qsub0_qsub1_qsub2 |
| 13836 | 0, // qsub1_qsub2 |
| 13837 | 0, // qsub1_qsub2_qsub3 |
| 13838 | 0, // qsub2_qsub3 |
| 13839 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 13840 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13841 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 13842 | 0, // sub_32_x8sub_1_then_sub_32 |
| 13843 | 0, // x8sub_0_x8sub_1 |
| 13844 | 0, // x8sub_2_x8sub_3 |
| 13845 | 0, // x8sub_4_x8sub_5 |
| 13846 | 0, // x8sub_6_x8sub_7 |
| 13847 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13848 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13849 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13850 | 0, // sub_32_subo64_then_sub_32 |
| 13851 | 0, // dsub_zsub1_then_dsub |
| 13852 | 0, // zsub_zsub1_then_zsub |
| 13853 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13854 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13855 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13856 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13857 | 0, // zsub0_zsub1 |
| 13858 | 0, // zsub0_zsub1_zsub2 |
| 13859 | 0, // zsub1_zsub2 |
| 13860 | 0, // zsub1_zsub2_zsub3 |
| 13861 | 0, // zsub2_zsub3 |
| 13862 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 13863 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13864 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 13865 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13866 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 13867 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 13868 | }, |
| 13869 | { // GPR32all |
| 13870 | 0, // bsub |
| 13871 | 0, // dsub |
| 13872 | 0, // dsub0 |
| 13873 | 0, // dsub1 |
| 13874 | 0, // dsub2 |
| 13875 | 0, // dsub3 |
| 13876 | 0, // hsub |
| 13877 | 0, // qhisub |
| 13878 | 0, // qsub |
| 13879 | 0, // qsub0 |
| 13880 | 0, // qsub1 |
| 13881 | 0, // qsub2 |
| 13882 | 0, // qsub3 |
| 13883 | 0, // ssub |
| 13884 | 0, // sub_32 |
| 13885 | 0, // sube32 |
| 13886 | 0, // sube64 |
| 13887 | 0, // subo32 |
| 13888 | 0, // subo64 |
| 13889 | 0, // x8sub_0 |
| 13890 | 0, // x8sub_1 |
| 13891 | 0, // x8sub_2 |
| 13892 | 0, // x8sub_3 |
| 13893 | 0, // x8sub_4 |
| 13894 | 0, // x8sub_5 |
| 13895 | 0, // x8sub_6 |
| 13896 | 0, // x8sub_7 |
| 13897 | 0, // zsub |
| 13898 | 0, // zsub0 |
| 13899 | 0, // zsub1 |
| 13900 | 0, // zsub2 |
| 13901 | 0, // zsub3 |
| 13902 | 0, // zsub_hi |
| 13903 | 0, // dsub1_then_bsub |
| 13904 | 0, // dsub1_then_hsub |
| 13905 | 0, // dsub1_then_ssub |
| 13906 | 0, // dsub3_then_bsub |
| 13907 | 0, // dsub3_then_hsub |
| 13908 | 0, // dsub3_then_ssub |
| 13909 | 0, // dsub2_then_bsub |
| 13910 | 0, // dsub2_then_hsub |
| 13911 | 0, // dsub2_then_ssub |
| 13912 | 0, // qsub1_then_bsub |
| 13913 | 0, // qsub1_then_dsub |
| 13914 | 0, // qsub1_then_hsub |
| 13915 | 0, // qsub1_then_ssub |
| 13916 | 0, // qsub3_then_bsub |
| 13917 | 0, // qsub3_then_dsub |
| 13918 | 0, // qsub3_then_hsub |
| 13919 | 0, // qsub3_then_ssub |
| 13920 | 0, // qsub2_then_bsub |
| 13921 | 0, // qsub2_then_dsub |
| 13922 | 0, // qsub2_then_hsub |
| 13923 | 0, // qsub2_then_ssub |
| 13924 | 0, // x8sub_7_then_sub_32 |
| 13925 | 0, // x8sub_6_then_sub_32 |
| 13926 | 0, // x8sub_5_then_sub_32 |
| 13927 | 0, // x8sub_4_then_sub_32 |
| 13928 | 0, // x8sub_3_then_sub_32 |
| 13929 | 0, // x8sub_2_then_sub_32 |
| 13930 | 0, // x8sub_1_then_sub_32 |
| 13931 | 0, // subo64_then_sub_32 |
| 13932 | 0, // zsub1_then_bsub |
| 13933 | 0, // zsub1_then_dsub |
| 13934 | 0, // zsub1_then_hsub |
| 13935 | 0, // zsub1_then_ssub |
| 13936 | 0, // zsub1_then_zsub |
| 13937 | 0, // zsub1_then_zsub_hi |
| 13938 | 0, // zsub3_then_bsub |
| 13939 | 0, // zsub3_then_dsub |
| 13940 | 0, // zsub3_then_hsub |
| 13941 | 0, // zsub3_then_ssub |
| 13942 | 0, // zsub3_then_zsub |
| 13943 | 0, // zsub3_then_zsub_hi |
| 13944 | 0, // zsub2_then_bsub |
| 13945 | 0, // zsub2_then_dsub |
| 13946 | 0, // zsub2_then_hsub |
| 13947 | 0, // zsub2_then_ssub |
| 13948 | 0, // zsub2_then_zsub |
| 13949 | 0, // zsub2_then_zsub_hi |
| 13950 | 0, // dsub0_dsub1 |
| 13951 | 0, // dsub0_dsub1_dsub2 |
| 13952 | 0, // dsub1_dsub2 |
| 13953 | 0, // dsub1_dsub2_dsub3 |
| 13954 | 0, // dsub2_dsub3 |
| 13955 | 0, // dsub_qsub1_then_dsub |
| 13956 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13957 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 13958 | 0, // qsub0_qsub1 |
| 13959 | 0, // qsub0_qsub1_qsub2 |
| 13960 | 0, // qsub1_qsub2 |
| 13961 | 0, // qsub1_qsub2_qsub3 |
| 13962 | 0, // qsub2_qsub3 |
| 13963 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 13964 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 13965 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 13966 | 0, // sub_32_x8sub_1_then_sub_32 |
| 13967 | 0, // x8sub_0_x8sub_1 |
| 13968 | 0, // x8sub_2_x8sub_3 |
| 13969 | 0, // x8sub_4_x8sub_5 |
| 13970 | 0, // x8sub_6_x8sub_7 |
| 13971 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 13972 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 13973 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 13974 | 0, // sub_32_subo64_then_sub_32 |
| 13975 | 0, // dsub_zsub1_then_dsub |
| 13976 | 0, // zsub_zsub1_then_zsub |
| 13977 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13978 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 13979 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13980 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 13981 | 0, // zsub0_zsub1 |
| 13982 | 0, // zsub0_zsub1_zsub2 |
| 13983 | 0, // zsub1_zsub2 |
| 13984 | 0, // zsub1_zsub2_zsub3 |
| 13985 | 0, // zsub2_zsub3 |
| 13986 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 13987 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 13988 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 13989 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 13990 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 13991 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 13992 | }, |
| 13993 | { // FPR32 |
| 13994 | 7, // bsub -> FPR32 |
| 13995 | 0, // dsub |
| 13996 | 0, // dsub0 |
| 13997 | 0, // dsub1 |
| 13998 | 0, // dsub2 |
| 13999 | 0, // dsub3 |
| 14000 | 7, // hsub -> FPR32 |
| 14001 | 0, // qhisub |
| 14002 | 0, // qsub |
| 14003 | 0, // qsub0 |
| 14004 | 0, // qsub1 |
| 14005 | 0, // qsub2 |
| 14006 | 0, // qsub3 |
| 14007 | 0, // ssub |
| 14008 | 0, // sub_32 |
| 14009 | 0, // sube32 |
| 14010 | 0, // sube64 |
| 14011 | 0, // subo32 |
| 14012 | 0, // subo64 |
| 14013 | 0, // x8sub_0 |
| 14014 | 0, // x8sub_1 |
| 14015 | 0, // x8sub_2 |
| 14016 | 0, // x8sub_3 |
| 14017 | 0, // x8sub_4 |
| 14018 | 0, // x8sub_5 |
| 14019 | 0, // x8sub_6 |
| 14020 | 0, // x8sub_7 |
| 14021 | 0, // zsub |
| 14022 | 0, // zsub0 |
| 14023 | 0, // zsub1 |
| 14024 | 0, // zsub2 |
| 14025 | 0, // zsub3 |
| 14026 | 0, // zsub_hi |
| 14027 | 0, // dsub1_then_bsub |
| 14028 | 0, // dsub1_then_hsub |
| 14029 | 0, // dsub1_then_ssub |
| 14030 | 0, // dsub3_then_bsub |
| 14031 | 0, // dsub3_then_hsub |
| 14032 | 0, // dsub3_then_ssub |
| 14033 | 0, // dsub2_then_bsub |
| 14034 | 0, // dsub2_then_hsub |
| 14035 | 0, // dsub2_then_ssub |
| 14036 | 0, // qsub1_then_bsub |
| 14037 | 0, // qsub1_then_dsub |
| 14038 | 0, // qsub1_then_hsub |
| 14039 | 0, // qsub1_then_ssub |
| 14040 | 0, // qsub3_then_bsub |
| 14041 | 0, // qsub3_then_dsub |
| 14042 | 0, // qsub3_then_hsub |
| 14043 | 0, // qsub3_then_ssub |
| 14044 | 0, // qsub2_then_bsub |
| 14045 | 0, // qsub2_then_dsub |
| 14046 | 0, // qsub2_then_hsub |
| 14047 | 0, // qsub2_then_ssub |
| 14048 | 0, // x8sub_7_then_sub_32 |
| 14049 | 0, // x8sub_6_then_sub_32 |
| 14050 | 0, // x8sub_5_then_sub_32 |
| 14051 | 0, // x8sub_4_then_sub_32 |
| 14052 | 0, // x8sub_3_then_sub_32 |
| 14053 | 0, // x8sub_2_then_sub_32 |
| 14054 | 0, // x8sub_1_then_sub_32 |
| 14055 | 0, // subo64_then_sub_32 |
| 14056 | 0, // zsub1_then_bsub |
| 14057 | 0, // zsub1_then_dsub |
| 14058 | 0, // zsub1_then_hsub |
| 14059 | 0, // zsub1_then_ssub |
| 14060 | 0, // zsub1_then_zsub |
| 14061 | 0, // zsub1_then_zsub_hi |
| 14062 | 0, // zsub3_then_bsub |
| 14063 | 0, // zsub3_then_dsub |
| 14064 | 0, // zsub3_then_hsub |
| 14065 | 0, // zsub3_then_ssub |
| 14066 | 0, // zsub3_then_zsub |
| 14067 | 0, // zsub3_then_zsub_hi |
| 14068 | 0, // zsub2_then_bsub |
| 14069 | 0, // zsub2_then_dsub |
| 14070 | 0, // zsub2_then_hsub |
| 14071 | 0, // zsub2_then_ssub |
| 14072 | 0, // zsub2_then_zsub |
| 14073 | 0, // zsub2_then_zsub_hi |
| 14074 | 0, // dsub0_dsub1 |
| 14075 | 0, // dsub0_dsub1_dsub2 |
| 14076 | 0, // dsub1_dsub2 |
| 14077 | 0, // dsub1_dsub2_dsub3 |
| 14078 | 0, // dsub2_dsub3 |
| 14079 | 0, // dsub_qsub1_then_dsub |
| 14080 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14081 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14082 | 0, // qsub0_qsub1 |
| 14083 | 0, // qsub0_qsub1_qsub2 |
| 14084 | 0, // qsub1_qsub2 |
| 14085 | 0, // qsub1_qsub2_qsub3 |
| 14086 | 0, // qsub2_qsub3 |
| 14087 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14088 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14089 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14090 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14091 | 0, // x8sub_0_x8sub_1 |
| 14092 | 0, // x8sub_2_x8sub_3 |
| 14093 | 0, // x8sub_4_x8sub_5 |
| 14094 | 0, // x8sub_6_x8sub_7 |
| 14095 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14096 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14097 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14098 | 0, // sub_32_subo64_then_sub_32 |
| 14099 | 0, // dsub_zsub1_then_dsub |
| 14100 | 0, // zsub_zsub1_then_zsub |
| 14101 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14102 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14103 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14104 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14105 | 0, // zsub0_zsub1 |
| 14106 | 0, // zsub0_zsub1_zsub2 |
| 14107 | 0, // zsub1_zsub2 |
| 14108 | 0, // zsub1_zsub2_zsub3 |
| 14109 | 0, // zsub2_zsub3 |
| 14110 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14111 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14112 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14113 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14114 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14115 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14116 | }, |
| 14117 | { // GPR32 |
| 14118 | 0, // bsub |
| 14119 | 0, // dsub |
| 14120 | 0, // dsub0 |
| 14121 | 0, // dsub1 |
| 14122 | 0, // dsub2 |
| 14123 | 0, // dsub3 |
| 14124 | 0, // hsub |
| 14125 | 0, // qhisub |
| 14126 | 0, // qsub |
| 14127 | 0, // qsub0 |
| 14128 | 0, // qsub1 |
| 14129 | 0, // qsub2 |
| 14130 | 0, // qsub3 |
| 14131 | 0, // ssub |
| 14132 | 0, // sub_32 |
| 14133 | 0, // sube32 |
| 14134 | 0, // sube64 |
| 14135 | 0, // subo32 |
| 14136 | 0, // subo64 |
| 14137 | 0, // x8sub_0 |
| 14138 | 0, // x8sub_1 |
| 14139 | 0, // x8sub_2 |
| 14140 | 0, // x8sub_3 |
| 14141 | 0, // x8sub_4 |
| 14142 | 0, // x8sub_5 |
| 14143 | 0, // x8sub_6 |
| 14144 | 0, // x8sub_7 |
| 14145 | 0, // zsub |
| 14146 | 0, // zsub0 |
| 14147 | 0, // zsub1 |
| 14148 | 0, // zsub2 |
| 14149 | 0, // zsub3 |
| 14150 | 0, // zsub_hi |
| 14151 | 0, // dsub1_then_bsub |
| 14152 | 0, // dsub1_then_hsub |
| 14153 | 0, // dsub1_then_ssub |
| 14154 | 0, // dsub3_then_bsub |
| 14155 | 0, // dsub3_then_hsub |
| 14156 | 0, // dsub3_then_ssub |
| 14157 | 0, // dsub2_then_bsub |
| 14158 | 0, // dsub2_then_hsub |
| 14159 | 0, // dsub2_then_ssub |
| 14160 | 0, // qsub1_then_bsub |
| 14161 | 0, // qsub1_then_dsub |
| 14162 | 0, // qsub1_then_hsub |
| 14163 | 0, // qsub1_then_ssub |
| 14164 | 0, // qsub3_then_bsub |
| 14165 | 0, // qsub3_then_dsub |
| 14166 | 0, // qsub3_then_hsub |
| 14167 | 0, // qsub3_then_ssub |
| 14168 | 0, // qsub2_then_bsub |
| 14169 | 0, // qsub2_then_dsub |
| 14170 | 0, // qsub2_then_hsub |
| 14171 | 0, // qsub2_then_ssub |
| 14172 | 0, // x8sub_7_then_sub_32 |
| 14173 | 0, // x8sub_6_then_sub_32 |
| 14174 | 0, // x8sub_5_then_sub_32 |
| 14175 | 0, // x8sub_4_then_sub_32 |
| 14176 | 0, // x8sub_3_then_sub_32 |
| 14177 | 0, // x8sub_2_then_sub_32 |
| 14178 | 0, // x8sub_1_then_sub_32 |
| 14179 | 0, // subo64_then_sub_32 |
| 14180 | 0, // zsub1_then_bsub |
| 14181 | 0, // zsub1_then_dsub |
| 14182 | 0, // zsub1_then_hsub |
| 14183 | 0, // zsub1_then_ssub |
| 14184 | 0, // zsub1_then_zsub |
| 14185 | 0, // zsub1_then_zsub_hi |
| 14186 | 0, // zsub3_then_bsub |
| 14187 | 0, // zsub3_then_dsub |
| 14188 | 0, // zsub3_then_hsub |
| 14189 | 0, // zsub3_then_ssub |
| 14190 | 0, // zsub3_then_zsub |
| 14191 | 0, // zsub3_then_zsub_hi |
| 14192 | 0, // zsub2_then_bsub |
| 14193 | 0, // zsub2_then_dsub |
| 14194 | 0, // zsub2_then_hsub |
| 14195 | 0, // zsub2_then_ssub |
| 14196 | 0, // zsub2_then_zsub |
| 14197 | 0, // zsub2_then_zsub_hi |
| 14198 | 0, // dsub0_dsub1 |
| 14199 | 0, // dsub0_dsub1_dsub2 |
| 14200 | 0, // dsub1_dsub2 |
| 14201 | 0, // dsub1_dsub2_dsub3 |
| 14202 | 0, // dsub2_dsub3 |
| 14203 | 0, // dsub_qsub1_then_dsub |
| 14204 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14205 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14206 | 0, // qsub0_qsub1 |
| 14207 | 0, // qsub0_qsub1_qsub2 |
| 14208 | 0, // qsub1_qsub2 |
| 14209 | 0, // qsub1_qsub2_qsub3 |
| 14210 | 0, // qsub2_qsub3 |
| 14211 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14212 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14213 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14214 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14215 | 0, // x8sub_0_x8sub_1 |
| 14216 | 0, // x8sub_2_x8sub_3 |
| 14217 | 0, // x8sub_4_x8sub_5 |
| 14218 | 0, // x8sub_6_x8sub_7 |
| 14219 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14220 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14221 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14222 | 0, // sub_32_subo64_then_sub_32 |
| 14223 | 0, // dsub_zsub1_then_dsub |
| 14224 | 0, // zsub_zsub1_then_zsub |
| 14225 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14226 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14227 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14228 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14229 | 0, // zsub0_zsub1 |
| 14230 | 0, // zsub0_zsub1_zsub2 |
| 14231 | 0, // zsub1_zsub2 |
| 14232 | 0, // zsub1_zsub2_zsub3 |
| 14233 | 0, // zsub2_zsub3 |
| 14234 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14235 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14236 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14237 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14238 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14239 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14240 | }, |
| 14241 | { // GPR32sp |
| 14242 | 0, // bsub |
| 14243 | 0, // dsub |
| 14244 | 0, // dsub0 |
| 14245 | 0, // dsub1 |
| 14246 | 0, // dsub2 |
| 14247 | 0, // dsub3 |
| 14248 | 0, // hsub |
| 14249 | 0, // qhisub |
| 14250 | 0, // qsub |
| 14251 | 0, // qsub0 |
| 14252 | 0, // qsub1 |
| 14253 | 0, // qsub2 |
| 14254 | 0, // qsub3 |
| 14255 | 0, // ssub |
| 14256 | 0, // sub_32 |
| 14257 | 0, // sube32 |
| 14258 | 0, // sube64 |
| 14259 | 0, // subo32 |
| 14260 | 0, // subo64 |
| 14261 | 0, // x8sub_0 |
| 14262 | 0, // x8sub_1 |
| 14263 | 0, // x8sub_2 |
| 14264 | 0, // x8sub_3 |
| 14265 | 0, // x8sub_4 |
| 14266 | 0, // x8sub_5 |
| 14267 | 0, // x8sub_6 |
| 14268 | 0, // x8sub_7 |
| 14269 | 0, // zsub |
| 14270 | 0, // zsub0 |
| 14271 | 0, // zsub1 |
| 14272 | 0, // zsub2 |
| 14273 | 0, // zsub3 |
| 14274 | 0, // zsub_hi |
| 14275 | 0, // dsub1_then_bsub |
| 14276 | 0, // dsub1_then_hsub |
| 14277 | 0, // dsub1_then_ssub |
| 14278 | 0, // dsub3_then_bsub |
| 14279 | 0, // dsub3_then_hsub |
| 14280 | 0, // dsub3_then_ssub |
| 14281 | 0, // dsub2_then_bsub |
| 14282 | 0, // dsub2_then_hsub |
| 14283 | 0, // dsub2_then_ssub |
| 14284 | 0, // qsub1_then_bsub |
| 14285 | 0, // qsub1_then_dsub |
| 14286 | 0, // qsub1_then_hsub |
| 14287 | 0, // qsub1_then_ssub |
| 14288 | 0, // qsub3_then_bsub |
| 14289 | 0, // qsub3_then_dsub |
| 14290 | 0, // qsub3_then_hsub |
| 14291 | 0, // qsub3_then_ssub |
| 14292 | 0, // qsub2_then_bsub |
| 14293 | 0, // qsub2_then_dsub |
| 14294 | 0, // qsub2_then_hsub |
| 14295 | 0, // qsub2_then_ssub |
| 14296 | 0, // x8sub_7_then_sub_32 |
| 14297 | 0, // x8sub_6_then_sub_32 |
| 14298 | 0, // x8sub_5_then_sub_32 |
| 14299 | 0, // x8sub_4_then_sub_32 |
| 14300 | 0, // x8sub_3_then_sub_32 |
| 14301 | 0, // x8sub_2_then_sub_32 |
| 14302 | 0, // x8sub_1_then_sub_32 |
| 14303 | 0, // subo64_then_sub_32 |
| 14304 | 0, // zsub1_then_bsub |
| 14305 | 0, // zsub1_then_dsub |
| 14306 | 0, // zsub1_then_hsub |
| 14307 | 0, // zsub1_then_ssub |
| 14308 | 0, // zsub1_then_zsub |
| 14309 | 0, // zsub1_then_zsub_hi |
| 14310 | 0, // zsub3_then_bsub |
| 14311 | 0, // zsub3_then_dsub |
| 14312 | 0, // zsub3_then_hsub |
| 14313 | 0, // zsub3_then_ssub |
| 14314 | 0, // zsub3_then_zsub |
| 14315 | 0, // zsub3_then_zsub_hi |
| 14316 | 0, // zsub2_then_bsub |
| 14317 | 0, // zsub2_then_dsub |
| 14318 | 0, // zsub2_then_hsub |
| 14319 | 0, // zsub2_then_ssub |
| 14320 | 0, // zsub2_then_zsub |
| 14321 | 0, // zsub2_then_zsub_hi |
| 14322 | 0, // dsub0_dsub1 |
| 14323 | 0, // dsub0_dsub1_dsub2 |
| 14324 | 0, // dsub1_dsub2 |
| 14325 | 0, // dsub1_dsub2_dsub3 |
| 14326 | 0, // dsub2_dsub3 |
| 14327 | 0, // dsub_qsub1_then_dsub |
| 14328 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14329 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14330 | 0, // qsub0_qsub1 |
| 14331 | 0, // qsub0_qsub1_qsub2 |
| 14332 | 0, // qsub1_qsub2 |
| 14333 | 0, // qsub1_qsub2_qsub3 |
| 14334 | 0, // qsub2_qsub3 |
| 14335 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14336 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14337 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14338 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14339 | 0, // x8sub_0_x8sub_1 |
| 14340 | 0, // x8sub_2_x8sub_3 |
| 14341 | 0, // x8sub_4_x8sub_5 |
| 14342 | 0, // x8sub_6_x8sub_7 |
| 14343 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14344 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14345 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14346 | 0, // sub_32_subo64_then_sub_32 |
| 14347 | 0, // dsub_zsub1_then_dsub |
| 14348 | 0, // zsub_zsub1_then_zsub |
| 14349 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14350 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14351 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14352 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14353 | 0, // zsub0_zsub1 |
| 14354 | 0, // zsub0_zsub1_zsub2 |
| 14355 | 0, // zsub1_zsub2 |
| 14356 | 0, // zsub1_zsub2_zsub3 |
| 14357 | 0, // zsub2_zsub3 |
| 14358 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14359 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14360 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14361 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14362 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14363 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14364 | }, |
| 14365 | { // GPR32common |
| 14366 | 0, // bsub |
| 14367 | 0, // dsub |
| 14368 | 0, // dsub0 |
| 14369 | 0, // dsub1 |
| 14370 | 0, // dsub2 |
| 14371 | 0, // dsub3 |
| 14372 | 0, // hsub |
| 14373 | 0, // qhisub |
| 14374 | 0, // qsub |
| 14375 | 0, // qsub0 |
| 14376 | 0, // qsub1 |
| 14377 | 0, // qsub2 |
| 14378 | 0, // qsub3 |
| 14379 | 0, // ssub |
| 14380 | 0, // sub_32 |
| 14381 | 0, // sube32 |
| 14382 | 0, // sube64 |
| 14383 | 0, // subo32 |
| 14384 | 0, // subo64 |
| 14385 | 0, // x8sub_0 |
| 14386 | 0, // x8sub_1 |
| 14387 | 0, // x8sub_2 |
| 14388 | 0, // x8sub_3 |
| 14389 | 0, // x8sub_4 |
| 14390 | 0, // x8sub_5 |
| 14391 | 0, // x8sub_6 |
| 14392 | 0, // x8sub_7 |
| 14393 | 0, // zsub |
| 14394 | 0, // zsub0 |
| 14395 | 0, // zsub1 |
| 14396 | 0, // zsub2 |
| 14397 | 0, // zsub3 |
| 14398 | 0, // zsub_hi |
| 14399 | 0, // dsub1_then_bsub |
| 14400 | 0, // dsub1_then_hsub |
| 14401 | 0, // dsub1_then_ssub |
| 14402 | 0, // dsub3_then_bsub |
| 14403 | 0, // dsub3_then_hsub |
| 14404 | 0, // dsub3_then_ssub |
| 14405 | 0, // dsub2_then_bsub |
| 14406 | 0, // dsub2_then_hsub |
| 14407 | 0, // dsub2_then_ssub |
| 14408 | 0, // qsub1_then_bsub |
| 14409 | 0, // qsub1_then_dsub |
| 14410 | 0, // qsub1_then_hsub |
| 14411 | 0, // qsub1_then_ssub |
| 14412 | 0, // qsub3_then_bsub |
| 14413 | 0, // qsub3_then_dsub |
| 14414 | 0, // qsub3_then_hsub |
| 14415 | 0, // qsub3_then_ssub |
| 14416 | 0, // qsub2_then_bsub |
| 14417 | 0, // qsub2_then_dsub |
| 14418 | 0, // qsub2_then_hsub |
| 14419 | 0, // qsub2_then_ssub |
| 14420 | 0, // x8sub_7_then_sub_32 |
| 14421 | 0, // x8sub_6_then_sub_32 |
| 14422 | 0, // x8sub_5_then_sub_32 |
| 14423 | 0, // x8sub_4_then_sub_32 |
| 14424 | 0, // x8sub_3_then_sub_32 |
| 14425 | 0, // x8sub_2_then_sub_32 |
| 14426 | 0, // x8sub_1_then_sub_32 |
| 14427 | 0, // subo64_then_sub_32 |
| 14428 | 0, // zsub1_then_bsub |
| 14429 | 0, // zsub1_then_dsub |
| 14430 | 0, // zsub1_then_hsub |
| 14431 | 0, // zsub1_then_ssub |
| 14432 | 0, // zsub1_then_zsub |
| 14433 | 0, // zsub1_then_zsub_hi |
| 14434 | 0, // zsub3_then_bsub |
| 14435 | 0, // zsub3_then_dsub |
| 14436 | 0, // zsub3_then_hsub |
| 14437 | 0, // zsub3_then_ssub |
| 14438 | 0, // zsub3_then_zsub |
| 14439 | 0, // zsub3_then_zsub_hi |
| 14440 | 0, // zsub2_then_bsub |
| 14441 | 0, // zsub2_then_dsub |
| 14442 | 0, // zsub2_then_hsub |
| 14443 | 0, // zsub2_then_ssub |
| 14444 | 0, // zsub2_then_zsub |
| 14445 | 0, // zsub2_then_zsub_hi |
| 14446 | 0, // dsub0_dsub1 |
| 14447 | 0, // dsub0_dsub1_dsub2 |
| 14448 | 0, // dsub1_dsub2 |
| 14449 | 0, // dsub1_dsub2_dsub3 |
| 14450 | 0, // dsub2_dsub3 |
| 14451 | 0, // dsub_qsub1_then_dsub |
| 14452 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14453 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14454 | 0, // qsub0_qsub1 |
| 14455 | 0, // qsub0_qsub1_qsub2 |
| 14456 | 0, // qsub1_qsub2 |
| 14457 | 0, // qsub1_qsub2_qsub3 |
| 14458 | 0, // qsub2_qsub3 |
| 14459 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14460 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14461 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14462 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14463 | 0, // x8sub_0_x8sub_1 |
| 14464 | 0, // x8sub_2_x8sub_3 |
| 14465 | 0, // x8sub_4_x8sub_5 |
| 14466 | 0, // x8sub_6_x8sub_7 |
| 14467 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14468 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14469 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14470 | 0, // sub_32_subo64_then_sub_32 |
| 14471 | 0, // dsub_zsub1_then_dsub |
| 14472 | 0, // zsub_zsub1_then_zsub |
| 14473 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14474 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14475 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14476 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14477 | 0, // zsub0_zsub1 |
| 14478 | 0, // zsub0_zsub1_zsub2 |
| 14479 | 0, // zsub1_zsub2 |
| 14480 | 0, // zsub1_zsub2_zsub3 |
| 14481 | 0, // zsub2_zsub3 |
| 14482 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14483 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14484 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14485 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14486 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14487 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14488 | }, |
| 14489 | { // FPR32_with_hsub_in_FPR16_lo |
| 14490 | 11, // bsub -> FPR32_with_hsub_in_FPR16_lo |
| 14491 | 0, // dsub |
| 14492 | 0, // dsub0 |
| 14493 | 0, // dsub1 |
| 14494 | 0, // dsub2 |
| 14495 | 0, // dsub3 |
| 14496 | 11, // hsub -> FPR32_with_hsub_in_FPR16_lo |
| 14497 | 0, // qhisub |
| 14498 | 0, // qsub |
| 14499 | 0, // qsub0 |
| 14500 | 0, // qsub1 |
| 14501 | 0, // qsub2 |
| 14502 | 0, // qsub3 |
| 14503 | 0, // ssub |
| 14504 | 0, // sub_32 |
| 14505 | 0, // sube32 |
| 14506 | 0, // sube64 |
| 14507 | 0, // subo32 |
| 14508 | 0, // subo64 |
| 14509 | 0, // x8sub_0 |
| 14510 | 0, // x8sub_1 |
| 14511 | 0, // x8sub_2 |
| 14512 | 0, // x8sub_3 |
| 14513 | 0, // x8sub_4 |
| 14514 | 0, // x8sub_5 |
| 14515 | 0, // x8sub_6 |
| 14516 | 0, // x8sub_7 |
| 14517 | 0, // zsub |
| 14518 | 0, // zsub0 |
| 14519 | 0, // zsub1 |
| 14520 | 0, // zsub2 |
| 14521 | 0, // zsub3 |
| 14522 | 0, // zsub_hi |
| 14523 | 0, // dsub1_then_bsub |
| 14524 | 0, // dsub1_then_hsub |
| 14525 | 0, // dsub1_then_ssub |
| 14526 | 0, // dsub3_then_bsub |
| 14527 | 0, // dsub3_then_hsub |
| 14528 | 0, // dsub3_then_ssub |
| 14529 | 0, // dsub2_then_bsub |
| 14530 | 0, // dsub2_then_hsub |
| 14531 | 0, // dsub2_then_ssub |
| 14532 | 0, // qsub1_then_bsub |
| 14533 | 0, // qsub1_then_dsub |
| 14534 | 0, // qsub1_then_hsub |
| 14535 | 0, // qsub1_then_ssub |
| 14536 | 0, // qsub3_then_bsub |
| 14537 | 0, // qsub3_then_dsub |
| 14538 | 0, // qsub3_then_hsub |
| 14539 | 0, // qsub3_then_ssub |
| 14540 | 0, // qsub2_then_bsub |
| 14541 | 0, // qsub2_then_dsub |
| 14542 | 0, // qsub2_then_hsub |
| 14543 | 0, // qsub2_then_ssub |
| 14544 | 0, // x8sub_7_then_sub_32 |
| 14545 | 0, // x8sub_6_then_sub_32 |
| 14546 | 0, // x8sub_5_then_sub_32 |
| 14547 | 0, // x8sub_4_then_sub_32 |
| 14548 | 0, // x8sub_3_then_sub_32 |
| 14549 | 0, // x8sub_2_then_sub_32 |
| 14550 | 0, // x8sub_1_then_sub_32 |
| 14551 | 0, // subo64_then_sub_32 |
| 14552 | 0, // zsub1_then_bsub |
| 14553 | 0, // zsub1_then_dsub |
| 14554 | 0, // zsub1_then_hsub |
| 14555 | 0, // zsub1_then_ssub |
| 14556 | 0, // zsub1_then_zsub |
| 14557 | 0, // zsub1_then_zsub_hi |
| 14558 | 0, // zsub3_then_bsub |
| 14559 | 0, // zsub3_then_dsub |
| 14560 | 0, // zsub3_then_hsub |
| 14561 | 0, // zsub3_then_ssub |
| 14562 | 0, // zsub3_then_zsub |
| 14563 | 0, // zsub3_then_zsub_hi |
| 14564 | 0, // zsub2_then_bsub |
| 14565 | 0, // zsub2_then_dsub |
| 14566 | 0, // zsub2_then_hsub |
| 14567 | 0, // zsub2_then_ssub |
| 14568 | 0, // zsub2_then_zsub |
| 14569 | 0, // zsub2_then_zsub_hi |
| 14570 | 0, // dsub0_dsub1 |
| 14571 | 0, // dsub0_dsub1_dsub2 |
| 14572 | 0, // dsub1_dsub2 |
| 14573 | 0, // dsub1_dsub2_dsub3 |
| 14574 | 0, // dsub2_dsub3 |
| 14575 | 0, // dsub_qsub1_then_dsub |
| 14576 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14577 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14578 | 0, // qsub0_qsub1 |
| 14579 | 0, // qsub0_qsub1_qsub2 |
| 14580 | 0, // qsub1_qsub2 |
| 14581 | 0, // qsub1_qsub2_qsub3 |
| 14582 | 0, // qsub2_qsub3 |
| 14583 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14584 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14585 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14586 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14587 | 0, // x8sub_0_x8sub_1 |
| 14588 | 0, // x8sub_2_x8sub_3 |
| 14589 | 0, // x8sub_4_x8sub_5 |
| 14590 | 0, // x8sub_6_x8sub_7 |
| 14591 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14592 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14593 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14594 | 0, // sub_32_subo64_then_sub_32 |
| 14595 | 0, // dsub_zsub1_then_dsub |
| 14596 | 0, // zsub_zsub1_then_zsub |
| 14597 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14598 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14599 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14600 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14601 | 0, // zsub0_zsub1 |
| 14602 | 0, // zsub0_zsub1_zsub2 |
| 14603 | 0, // zsub1_zsub2 |
| 14604 | 0, // zsub1_zsub2_zsub3 |
| 14605 | 0, // zsub2_zsub3 |
| 14606 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14607 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14608 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14609 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14610 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14611 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14612 | }, |
| 14613 | { // GPR32arg |
| 14614 | 0, // bsub |
| 14615 | 0, // dsub |
| 14616 | 0, // dsub0 |
| 14617 | 0, // dsub1 |
| 14618 | 0, // dsub2 |
| 14619 | 0, // dsub3 |
| 14620 | 0, // hsub |
| 14621 | 0, // qhisub |
| 14622 | 0, // qsub |
| 14623 | 0, // qsub0 |
| 14624 | 0, // qsub1 |
| 14625 | 0, // qsub2 |
| 14626 | 0, // qsub3 |
| 14627 | 0, // ssub |
| 14628 | 0, // sub_32 |
| 14629 | 0, // sube32 |
| 14630 | 0, // sube64 |
| 14631 | 0, // subo32 |
| 14632 | 0, // subo64 |
| 14633 | 0, // x8sub_0 |
| 14634 | 0, // x8sub_1 |
| 14635 | 0, // x8sub_2 |
| 14636 | 0, // x8sub_3 |
| 14637 | 0, // x8sub_4 |
| 14638 | 0, // x8sub_5 |
| 14639 | 0, // x8sub_6 |
| 14640 | 0, // x8sub_7 |
| 14641 | 0, // zsub |
| 14642 | 0, // zsub0 |
| 14643 | 0, // zsub1 |
| 14644 | 0, // zsub2 |
| 14645 | 0, // zsub3 |
| 14646 | 0, // zsub_hi |
| 14647 | 0, // dsub1_then_bsub |
| 14648 | 0, // dsub1_then_hsub |
| 14649 | 0, // dsub1_then_ssub |
| 14650 | 0, // dsub3_then_bsub |
| 14651 | 0, // dsub3_then_hsub |
| 14652 | 0, // dsub3_then_ssub |
| 14653 | 0, // dsub2_then_bsub |
| 14654 | 0, // dsub2_then_hsub |
| 14655 | 0, // dsub2_then_ssub |
| 14656 | 0, // qsub1_then_bsub |
| 14657 | 0, // qsub1_then_dsub |
| 14658 | 0, // qsub1_then_hsub |
| 14659 | 0, // qsub1_then_ssub |
| 14660 | 0, // qsub3_then_bsub |
| 14661 | 0, // qsub3_then_dsub |
| 14662 | 0, // qsub3_then_hsub |
| 14663 | 0, // qsub3_then_ssub |
| 14664 | 0, // qsub2_then_bsub |
| 14665 | 0, // qsub2_then_dsub |
| 14666 | 0, // qsub2_then_hsub |
| 14667 | 0, // qsub2_then_ssub |
| 14668 | 0, // x8sub_7_then_sub_32 |
| 14669 | 0, // x8sub_6_then_sub_32 |
| 14670 | 0, // x8sub_5_then_sub_32 |
| 14671 | 0, // x8sub_4_then_sub_32 |
| 14672 | 0, // x8sub_3_then_sub_32 |
| 14673 | 0, // x8sub_2_then_sub_32 |
| 14674 | 0, // x8sub_1_then_sub_32 |
| 14675 | 0, // subo64_then_sub_32 |
| 14676 | 0, // zsub1_then_bsub |
| 14677 | 0, // zsub1_then_dsub |
| 14678 | 0, // zsub1_then_hsub |
| 14679 | 0, // zsub1_then_ssub |
| 14680 | 0, // zsub1_then_zsub |
| 14681 | 0, // zsub1_then_zsub_hi |
| 14682 | 0, // zsub3_then_bsub |
| 14683 | 0, // zsub3_then_dsub |
| 14684 | 0, // zsub3_then_hsub |
| 14685 | 0, // zsub3_then_ssub |
| 14686 | 0, // zsub3_then_zsub |
| 14687 | 0, // zsub3_then_zsub_hi |
| 14688 | 0, // zsub2_then_bsub |
| 14689 | 0, // zsub2_then_dsub |
| 14690 | 0, // zsub2_then_hsub |
| 14691 | 0, // zsub2_then_ssub |
| 14692 | 0, // zsub2_then_zsub |
| 14693 | 0, // zsub2_then_zsub_hi |
| 14694 | 0, // dsub0_dsub1 |
| 14695 | 0, // dsub0_dsub1_dsub2 |
| 14696 | 0, // dsub1_dsub2 |
| 14697 | 0, // dsub1_dsub2_dsub3 |
| 14698 | 0, // dsub2_dsub3 |
| 14699 | 0, // dsub_qsub1_then_dsub |
| 14700 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14701 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14702 | 0, // qsub0_qsub1 |
| 14703 | 0, // qsub0_qsub1_qsub2 |
| 14704 | 0, // qsub1_qsub2 |
| 14705 | 0, // qsub1_qsub2_qsub3 |
| 14706 | 0, // qsub2_qsub3 |
| 14707 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14708 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14709 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14710 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14711 | 0, // x8sub_0_x8sub_1 |
| 14712 | 0, // x8sub_2_x8sub_3 |
| 14713 | 0, // x8sub_4_x8sub_5 |
| 14714 | 0, // x8sub_6_x8sub_7 |
| 14715 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14716 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14717 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14718 | 0, // sub_32_subo64_then_sub_32 |
| 14719 | 0, // dsub_zsub1_then_dsub |
| 14720 | 0, // zsub_zsub1_then_zsub |
| 14721 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14722 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14723 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14724 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14725 | 0, // zsub0_zsub1 |
| 14726 | 0, // zsub0_zsub1_zsub2 |
| 14727 | 0, // zsub1_zsub2 |
| 14728 | 0, // zsub1_zsub2_zsub3 |
| 14729 | 0, // zsub2_zsub3 |
| 14730 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14731 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14732 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14733 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14734 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14735 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14736 | }, |
| 14737 | { // CCR |
| 14738 | 0, // bsub |
| 14739 | 0, // dsub |
| 14740 | 0, // dsub0 |
| 14741 | 0, // dsub1 |
| 14742 | 0, // dsub2 |
| 14743 | 0, // dsub3 |
| 14744 | 0, // hsub |
| 14745 | 0, // qhisub |
| 14746 | 0, // qsub |
| 14747 | 0, // qsub0 |
| 14748 | 0, // qsub1 |
| 14749 | 0, // qsub2 |
| 14750 | 0, // qsub3 |
| 14751 | 0, // ssub |
| 14752 | 0, // sub_32 |
| 14753 | 0, // sube32 |
| 14754 | 0, // sube64 |
| 14755 | 0, // subo32 |
| 14756 | 0, // subo64 |
| 14757 | 0, // x8sub_0 |
| 14758 | 0, // x8sub_1 |
| 14759 | 0, // x8sub_2 |
| 14760 | 0, // x8sub_3 |
| 14761 | 0, // x8sub_4 |
| 14762 | 0, // x8sub_5 |
| 14763 | 0, // x8sub_6 |
| 14764 | 0, // x8sub_7 |
| 14765 | 0, // zsub |
| 14766 | 0, // zsub0 |
| 14767 | 0, // zsub1 |
| 14768 | 0, // zsub2 |
| 14769 | 0, // zsub3 |
| 14770 | 0, // zsub_hi |
| 14771 | 0, // dsub1_then_bsub |
| 14772 | 0, // dsub1_then_hsub |
| 14773 | 0, // dsub1_then_ssub |
| 14774 | 0, // dsub3_then_bsub |
| 14775 | 0, // dsub3_then_hsub |
| 14776 | 0, // dsub3_then_ssub |
| 14777 | 0, // dsub2_then_bsub |
| 14778 | 0, // dsub2_then_hsub |
| 14779 | 0, // dsub2_then_ssub |
| 14780 | 0, // qsub1_then_bsub |
| 14781 | 0, // qsub1_then_dsub |
| 14782 | 0, // qsub1_then_hsub |
| 14783 | 0, // qsub1_then_ssub |
| 14784 | 0, // qsub3_then_bsub |
| 14785 | 0, // qsub3_then_dsub |
| 14786 | 0, // qsub3_then_hsub |
| 14787 | 0, // qsub3_then_ssub |
| 14788 | 0, // qsub2_then_bsub |
| 14789 | 0, // qsub2_then_dsub |
| 14790 | 0, // qsub2_then_hsub |
| 14791 | 0, // qsub2_then_ssub |
| 14792 | 0, // x8sub_7_then_sub_32 |
| 14793 | 0, // x8sub_6_then_sub_32 |
| 14794 | 0, // x8sub_5_then_sub_32 |
| 14795 | 0, // x8sub_4_then_sub_32 |
| 14796 | 0, // x8sub_3_then_sub_32 |
| 14797 | 0, // x8sub_2_then_sub_32 |
| 14798 | 0, // x8sub_1_then_sub_32 |
| 14799 | 0, // subo64_then_sub_32 |
| 14800 | 0, // zsub1_then_bsub |
| 14801 | 0, // zsub1_then_dsub |
| 14802 | 0, // zsub1_then_hsub |
| 14803 | 0, // zsub1_then_ssub |
| 14804 | 0, // zsub1_then_zsub |
| 14805 | 0, // zsub1_then_zsub_hi |
| 14806 | 0, // zsub3_then_bsub |
| 14807 | 0, // zsub3_then_dsub |
| 14808 | 0, // zsub3_then_hsub |
| 14809 | 0, // zsub3_then_ssub |
| 14810 | 0, // zsub3_then_zsub |
| 14811 | 0, // zsub3_then_zsub_hi |
| 14812 | 0, // zsub2_then_bsub |
| 14813 | 0, // zsub2_then_dsub |
| 14814 | 0, // zsub2_then_hsub |
| 14815 | 0, // zsub2_then_ssub |
| 14816 | 0, // zsub2_then_zsub |
| 14817 | 0, // zsub2_then_zsub_hi |
| 14818 | 0, // dsub0_dsub1 |
| 14819 | 0, // dsub0_dsub1_dsub2 |
| 14820 | 0, // dsub1_dsub2 |
| 14821 | 0, // dsub1_dsub2_dsub3 |
| 14822 | 0, // dsub2_dsub3 |
| 14823 | 0, // dsub_qsub1_then_dsub |
| 14824 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14825 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14826 | 0, // qsub0_qsub1 |
| 14827 | 0, // qsub0_qsub1_qsub2 |
| 14828 | 0, // qsub1_qsub2 |
| 14829 | 0, // qsub1_qsub2_qsub3 |
| 14830 | 0, // qsub2_qsub3 |
| 14831 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14832 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14833 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14834 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14835 | 0, // x8sub_0_x8sub_1 |
| 14836 | 0, // x8sub_2_x8sub_3 |
| 14837 | 0, // x8sub_4_x8sub_5 |
| 14838 | 0, // x8sub_6_x8sub_7 |
| 14839 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14840 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14841 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14842 | 0, // sub_32_subo64_then_sub_32 |
| 14843 | 0, // dsub_zsub1_then_dsub |
| 14844 | 0, // zsub_zsub1_then_zsub |
| 14845 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14846 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14847 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14848 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14849 | 0, // zsub0_zsub1 |
| 14850 | 0, // zsub0_zsub1_zsub2 |
| 14851 | 0, // zsub1_zsub2 |
| 14852 | 0, // zsub1_zsub2_zsub3 |
| 14853 | 0, // zsub2_zsub3 |
| 14854 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14855 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14856 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14857 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14858 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14859 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14860 | }, |
| 14861 | { // GPR32sponly |
| 14862 | 0, // bsub |
| 14863 | 0, // dsub |
| 14864 | 0, // dsub0 |
| 14865 | 0, // dsub1 |
| 14866 | 0, // dsub2 |
| 14867 | 0, // dsub3 |
| 14868 | 0, // hsub |
| 14869 | 0, // qhisub |
| 14870 | 0, // qsub |
| 14871 | 0, // qsub0 |
| 14872 | 0, // qsub1 |
| 14873 | 0, // qsub2 |
| 14874 | 0, // qsub3 |
| 14875 | 0, // ssub |
| 14876 | 0, // sub_32 |
| 14877 | 0, // sube32 |
| 14878 | 0, // sube64 |
| 14879 | 0, // subo32 |
| 14880 | 0, // subo64 |
| 14881 | 0, // x8sub_0 |
| 14882 | 0, // x8sub_1 |
| 14883 | 0, // x8sub_2 |
| 14884 | 0, // x8sub_3 |
| 14885 | 0, // x8sub_4 |
| 14886 | 0, // x8sub_5 |
| 14887 | 0, // x8sub_6 |
| 14888 | 0, // x8sub_7 |
| 14889 | 0, // zsub |
| 14890 | 0, // zsub0 |
| 14891 | 0, // zsub1 |
| 14892 | 0, // zsub2 |
| 14893 | 0, // zsub3 |
| 14894 | 0, // zsub_hi |
| 14895 | 0, // dsub1_then_bsub |
| 14896 | 0, // dsub1_then_hsub |
| 14897 | 0, // dsub1_then_ssub |
| 14898 | 0, // dsub3_then_bsub |
| 14899 | 0, // dsub3_then_hsub |
| 14900 | 0, // dsub3_then_ssub |
| 14901 | 0, // dsub2_then_bsub |
| 14902 | 0, // dsub2_then_hsub |
| 14903 | 0, // dsub2_then_ssub |
| 14904 | 0, // qsub1_then_bsub |
| 14905 | 0, // qsub1_then_dsub |
| 14906 | 0, // qsub1_then_hsub |
| 14907 | 0, // qsub1_then_ssub |
| 14908 | 0, // qsub3_then_bsub |
| 14909 | 0, // qsub3_then_dsub |
| 14910 | 0, // qsub3_then_hsub |
| 14911 | 0, // qsub3_then_ssub |
| 14912 | 0, // qsub2_then_bsub |
| 14913 | 0, // qsub2_then_dsub |
| 14914 | 0, // qsub2_then_hsub |
| 14915 | 0, // qsub2_then_ssub |
| 14916 | 0, // x8sub_7_then_sub_32 |
| 14917 | 0, // x8sub_6_then_sub_32 |
| 14918 | 0, // x8sub_5_then_sub_32 |
| 14919 | 0, // x8sub_4_then_sub_32 |
| 14920 | 0, // x8sub_3_then_sub_32 |
| 14921 | 0, // x8sub_2_then_sub_32 |
| 14922 | 0, // x8sub_1_then_sub_32 |
| 14923 | 0, // subo64_then_sub_32 |
| 14924 | 0, // zsub1_then_bsub |
| 14925 | 0, // zsub1_then_dsub |
| 14926 | 0, // zsub1_then_hsub |
| 14927 | 0, // zsub1_then_ssub |
| 14928 | 0, // zsub1_then_zsub |
| 14929 | 0, // zsub1_then_zsub_hi |
| 14930 | 0, // zsub3_then_bsub |
| 14931 | 0, // zsub3_then_dsub |
| 14932 | 0, // zsub3_then_hsub |
| 14933 | 0, // zsub3_then_ssub |
| 14934 | 0, // zsub3_then_zsub |
| 14935 | 0, // zsub3_then_zsub_hi |
| 14936 | 0, // zsub2_then_bsub |
| 14937 | 0, // zsub2_then_dsub |
| 14938 | 0, // zsub2_then_hsub |
| 14939 | 0, // zsub2_then_ssub |
| 14940 | 0, // zsub2_then_zsub |
| 14941 | 0, // zsub2_then_zsub_hi |
| 14942 | 0, // dsub0_dsub1 |
| 14943 | 0, // dsub0_dsub1_dsub2 |
| 14944 | 0, // dsub1_dsub2 |
| 14945 | 0, // dsub1_dsub2_dsub3 |
| 14946 | 0, // dsub2_dsub3 |
| 14947 | 0, // dsub_qsub1_then_dsub |
| 14948 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14949 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 14950 | 0, // qsub0_qsub1 |
| 14951 | 0, // qsub0_qsub1_qsub2 |
| 14952 | 0, // qsub1_qsub2 |
| 14953 | 0, // qsub1_qsub2_qsub3 |
| 14954 | 0, // qsub2_qsub3 |
| 14955 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 14956 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 14957 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 14958 | 0, // sub_32_x8sub_1_then_sub_32 |
| 14959 | 0, // x8sub_0_x8sub_1 |
| 14960 | 0, // x8sub_2_x8sub_3 |
| 14961 | 0, // x8sub_4_x8sub_5 |
| 14962 | 0, // x8sub_6_x8sub_7 |
| 14963 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 14964 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 14965 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 14966 | 0, // sub_32_subo64_then_sub_32 |
| 14967 | 0, // dsub_zsub1_then_dsub |
| 14968 | 0, // zsub_zsub1_then_zsub |
| 14969 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14970 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 14971 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14972 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 14973 | 0, // zsub0_zsub1 |
| 14974 | 0, // zsub0_zsub1_zsub2 |
| 14975 | 0, // zsub1_zsub2 |
| 14976 | 0, // zsub1_zsub2_zsub3 |
| 14977 | 0, // zsub2_zsub3 |
| 14978 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 14979 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 14980 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 14981 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 14982 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 14983 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 14984 | }, |
| 14985 | { // WSeqPairsClass |
| 14986 | 0, // bsub |
| 14987 | 0, // dsub |
| 14988 | 0, // dsub0 |
| 14989 | 0, // dsub1 |
| 14990 | 0, // dsub2 |
| 14991 | 0, // dsub3 |
| 14992 | 0, // hsub |
| 14993 | 0, // qhisub |
| 14994 | 0, // qsub |
| 14995 | 0, // qsub0 |
| 14996 | 0, // qsub1 |
| 14997 | 0, // qsub2 |
| 14998 | 0, // qsub3 |
| 14999 | 0, // ssub |
| 15000 | 0, // sub_32 |
| 15001 | 15, // sube32 -> WSeqPairsClass |
| 15002 | 0, // sube64 |
| 15003 | 15, // subo32 -> WSeqPairsClass |
| 15004 | 0, // subo64 |
| 15005 | 0, // x8sub_0 |
| 15006 | 0, // x8sub_1 |
| 15007 | 0, // x8sub_2 |
| 15008 | 0, // x8sub_3 |
| 15009 | 0, // x8sub_4 |
| 15010 | 0, // x8sub_5 |
| 15011 | 0, // x8sub_6 |
| 15012 | 0, // x8sub_7 |
| 15013 | 0, // zsub |
| 15014 | 0, // zsub0 |
| 15015 | 0, // zsub1 |
| 15016 | 0, // zsub2 |
| 15017 | 0, // zsub3 |
| 15018 | 0, // zsub_hi |
| 15019 | 0, // dsub1_then_bsub |
| 15020 | 0, // dsub1_then_hsub |
| 15021 | 0, // dsub1_then_ssub |
| 15022 | 0, // dsub3_then_bsub |
| 15023 | 0, // dsub3_then_hsub |
| 15024 | 0, // dsub3_then_ssub |
| 15025 | 0, // dsub2_then_bsub |
| 15026 | 0, // dsub2_then_hsub |
| 15027 | 0, // dsub2_then_ssub |
| 15028 | 0, // qsub1_then_bsub |
| 15029 | 0, // qsub1_then_dsub |
| 15030 | 0, // qsub1_then_hsub |
| 15031 | 0, // qsub1_then_ssub |
| 15032 | 0, // qsub3_then_bsub |
| 15033 | 0, // qsub3_then_dsub |
| 15034 | 0, // qsub3_then_hsub |
| 15035 | 0, // qsub3_then_ssub |
| 15036 | 0, // qsub2_then_bsub |
| 15037 | 0, // qsub2_then_dsub |
| 15038 | 0, // qsub2_then_hsub |
| 15039 | 0, // qsub2_then_ssub |
| 15040 | 0, // x8sub_7_then_sub_32 |
| 15041 | 0, // x8sub_6_then_sub_32 |
| 15042 | 0, // x8sub_5_then_sub_32 |
| 15043 | 0, // x8sub_4_then_sub_32 |
| 15044 | 0, // x8sub_3_then_sub_32 |
| 15045 | 0, // x8sub_2_then_sub_32 |
| 15046 | 0, // x8sub_1_then_sub_32 |
| 15047 | 0, // subo64_then_sub_32 |
| 15048 | 0, // zsub1_then_bsub |
| 15049 | 0, // zsub1_then_dsub |
| 15050 | 0, // zsub1_then_hsub |
| 15051 | 0, // zsub1_then_ssub |
| 15052 | 0, // zsub1_then_zsub |
| 15053 | 0, // zsub1_then_zsub_hi |
| 15054 | 0, // zsub3_then_bsub |
| 15055 | 0, // zsub3_then_dsub |
| 15056 | 0, // zsub3_then_hsub |
| 15057 | 0, // zsub3_then_ssub |
| 15058 | 0, // zsub3_then_zsub |
| 15059 | 0, // zsub3_then_zsub_hi |
| 15060 | 0, // zsub2_then_bsub |
| 15061 | 0, // zsub2_then_dsub |
| 15062 | 0, // zsub2_then_hsub |
| 15063 | 0, // zsub2_then_ssub |
| 15064 | 0, // zsub2_then_zsub |
| 15065 | 0, // zsub2_then_zsub_hi |
| 15066 | 0, // dsub0_dsub1 |
| 15067 | 0, // dsub0_dsub1_dsub2 |
| 15068 | 0, // dsub1_dsub2 |
| 15069 | 0, // dsub1_dsub2_dsub3 |
| 15070 | 0, // dsub2_dsub3 |
| 15071 | 0, // dsub_qsub1_then_dsub |
| 15072 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15073 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15074 | 0, // qsub0_qsub1 |
| 15075 | 0, // qsub0_qsub1_qsub2 |
| 15076 | 0, // qsub1_qsub2 |
| 15077 | 0, // qsub1_qsub2_qsub3 |
| 15078 | 0, // qsub2_qsub3 |
| 15079 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15080 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15081 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15082 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15083 | 0, // x8sub_0_x8sub_1 |
| 15084 | 0, // x8sub_2_x8sub_3 |
| 15085 | 0, // x8sub_4_x8sub_5 |
| 15086 | 0, // x8sub_6_x8sub_7 |
| 15087 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15088 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15089 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15090 | 0, // sub_32_subo64_then_sub_32 |
| 15091 | 0, // dsub_zsub1_then_dsub |
| 15092 | 0, // zsub_zsub1_then_zsub |
| 15093 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15094 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15095 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15096 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15097 | 0, // zsub0_zsub1 |
| 15098 | 0, // zsub0_zsub1_zsub2 |
| 15099 | 0, // zsub1_zsub2 |
| 15100 | 0, // zsub1_zsub2_zsub3 |
| 15101 | 0, // zsub2_zsub3 |
| 15102 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15103 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15104 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15105 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15106 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15107 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15108 | }, |
| 15109 | { // WSeqPairsClass_with_subo32_in_GPR32common |
| 15110 | 0, // bsub |
| 15111 | 0, // dsub |
| 15112 | 0, // dsub0 |
| 15113 | 0, // dsub1 |
| 15114 | 0, // dsub2 |
| 15115 | 0, // dsub3 |
| 15116 | 0, // hsub |
| 15117 | 0, // qhisub |
| 15118 | 0, // qsub |
| 15119 | 0, // qsub0 |
| 15120 | 0, // qsub1 |
| 15121 | 0, // qsub2 |
| 15122 | 0, // qsub3 |
| 15123 | 0, // ssub |
| 15124 | 0, // sub_32 |
| 15125 | 16, // sube32 -> WSeqPairsClass_with_subo32_in_GPR32common |
| 15126 | 0, // sube64 |
| 15127 | 16, // subo32 -> WSeqPairsClass_with_subo32_in_GPR32common |
| 15128 | 0, // subo64 |
| 15129 | 0, // x8sub_0 |
| 15130 | 0, // x8sub_1 |
| 15131 | 0, // x8sub_2 |
| 15132 | 0, // x8sub_3 |
| 15133 | 0, // x8sub_4 |
| 15134 | 0, // x8sub_5 |
| 15135 | 0, // x8sub_6 |
| 15136 | 0, // x8sub_7 |
| 15137 | 0, // zsub |
| 15138 | 0, // zsub0 |
| 15139 | 0, // zsub1 |
| 15140 | 0, // zsub2 |
| 15141 | 0, // zsub3 |
| 15142 | 0, // zsub_hi |
| 15143 | 0, // dsub1_then_bsub |
| 15144 | 0, // dsub1_then_hsub |
| 15145 | 0, // dsub1_then_ssub |
| 15146 | 0, // dsub3_then_bsub |
| 15147 | 0, // dsub3_then_hsub |
| 15148 | 0, // dsub3_then_ssub |
| 15149 | 0, // dsub2_then_bsub |
| 15150 | 0, // dsub2_then_hsub |
| 15151 | 0, // dsub2_then_ssub |
| 15152 | 0, // qsub1_then_bsub |
| 15153 | 0, // qsub1_then_dsub |
| 15154 | 0, // qsub1_then_hsub |
| 15155 | 0, // qsub1_then_ssub |
| 15156 | 0, // qsub3_then_bsub |
| 15157 | 0, // qsub3_then_dsub |
| 15158 | 0, // qsub3_then_hsub |
| 15159 | 0, // qsub3_then_ssub |
| 15160 | 0, // qsub2_then_bsub |
| 15161 | 0, // qsub2_then_dsub |
| 15162 | 0, // qsub2_then_hsub |
| 15163 | 0, // qsub2_then_ssub |
| 15164 | 0, // x8sub_7_then_sub_32 |
| 15165 | 0, // x8sub_6_then_sub_32 |
| 15166 | 0, // x8sub_5_then_sub_32 |
| 15167 | 0, // x8sub_4_then_sub_32 |
| 15168 | 0, // x8sub_3_then_sub_32 |
| 15169 | 0, // x8sub_2_then_sub_32 |
| 15170 | 0, // x8sub_1_then_sub_32 |
| 15171 | 0, // subo64_then_sub_32 |
| 15172 | 0, // zsub1_then_bsub |
| 15173 | 0, // zsub1_then_dsub |
| 15174 | 0, // zsub1_then_hsub |
| 15175 | 0, // zsub1_then_ssub |
| 15176 | 0, // zsub1_then_zsub |
| 15177 | 0, // zsub1_then_zsub_hi |
| 15178 | 0, // zsub3_then_bsub |
| 15179 | 0, // zsub3_then_dsub |
| 15180 | 0, // zsub3_then_hsub |
| 15181 | 0, // zsub3_then_ssub |
| 15182 | 0, // zsub3_then_zsub |
| 15183 | 0, // zsub3_then_zsub_hi |
| 15184 | 0, // zsub2_then_bsub |
| 15185 | 0, // zsub2_then_dsub |
| 15186 | 0, // zsub2_then_hsub |
| 15187 | 0, // zsub2_then_ssub |
| 15188 | 0, // zsub2_then_zsub |
| 15189 | 0, // zsub2_then_zsub_hi |
| 15190 | 0, // dsub0_dsub1 |
| 15191 | 0, // dsub0_dsub1_dsub2 |
| 15192 | 0, // dsub1_dsub2 |
| 15193 | 0, // dsub1_dsub2_dsub3 |
| 15194 | 0, // dsub2_dsub3 |
| 15195 | 0, // dsub_qsub1_then_dsub |
| 15196 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15197 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15198 | 0, // qsub0_qsub1 |
| 15199 | 0, // qsub0_qsub1_qsub2 |
| 15200 | 0, // qsub1_qsub2 |
| 15201 | 0, // qsub1_qsub2_qsub3 |
| 15202 | 0, // qsub2_qsub3 |
| 15203 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15204 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15205 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15206 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15207 | 0, // x8sub_0_x8sub_1 |
| 15208 | 0, // x8sub_2_x8sub_3 |
| 15209 | 0, // x8sub_4_x8sub_5 |
| 15210 | 0, // x8sub_6_x8sub_7 |
| 15211 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15212 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15213 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15214 | 0, // sub_32_subo64_then_sub_32 |
| 15215 | 0, // dsub_zsub1_then_dsub |
| 15216 | 0, // zsub_zsub1_then_zsub |
| 15217 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15218 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15219 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15220 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15221 | 0, // zsub0_zsub1 |
| 15222 | 0, // zsub0_zsub1_zsub2 |
| 15223 | 0, // zsub1_zsub2 |
| 15224 | 0, // zsub1_zsub2_zsub3 |
| 15225 | 0, // zsub2_zsub3 |
| 15226 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15227 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15228 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15229 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15230 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15231 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15232 | }, |
| 15233 | { // WSeqPairsClass_with_sube32_in_GPR32arg |
| 15234 | 0, // bsub |
| 15235 | 0, // dsub |
| 15236 | 0, // dsub0 |
| 15237 | 0, // dsub1 |
| 15238 | 0, // dsub2 |
| 15239 | 0, // dsub3 |
| 15240 | 0, // hsub |
| 15241 | 0, // qhisub |
| 15242 | 0, // qsub |
| 15243 | 0, // qsub0 |
| 15244 | 0, // qsub1 |
| 15245 | 0, // qsub2 |
| 15246 | 0, // qsub3 |
| 15247 | 0, // ssub |
| 15248 | 0, // sub_32 |
| 15249 | 17, // sube32 -> WSeqPairsClass_with_sube32_in_GPR32arg |
| 15250 | 0, // sube64 |
| 15251 | 17, // subo32 -> WSeqPairsClass_with_sube32_in_GPR32arg |
| 15252 | 0, // subo64 |
| 15253 | 0, // x8sub_0 |
| 15254 | 0, // x8sub_1 |
| 15255 | 0, // x8sub_2 |
| 15256 | 0, // x8sub_3 |
| 15257 | 0, // x8sub_4 |
| 15258 | 0, // x8sub_5 |
| 15259 | 0, // x8sub_6 |
| 15260 | 0, // x8sub_7 |
| 15261 | 0, // zsub |
| 15262 | 0, // zsub0 |
| 15263 | 0, // zsub1 |
| 15264 | 0, // zsub2 |
| 15265 | 0, // zsub3 |
| 15266 | 0, // zsub_hi |
| 15267 | 0, // dsub1_then_bsub |
| 15268 | 0, // dsub1_then_hsub |
| 15269 | 0, // dsub1_then_ssub |
| 15270 | 0, // dsub3_then_bsub |
| 15271 | 0, // dsub3_then_hsub |
| 15272 | 0, // dsub3_then_ssub |
| 15273 | 0, // dsub2_then_bsub |
| 15274 | 0, // dsub2_then_hsub |
| 15275 | 0, // dsub2_then_ssub |
| 15276 | 0, // qsub1_then_bsub |
| 15277 | 0, // qsub1_then_dsub |
| 15278 | 0, // qsub1_then_hsub |
| 15279 | 0, // qsub1_then_ssub |
| 15280 | 0, // qsub3_then_bsub |
| 15281 | 0, // qsub3_then_dsub |
| 15282 | 0, // qsub3_then_hsub |
| 15283 | 0, // qsub3_then_ssub |
| 15284 | 0, // qsub2_then_bsub |
| 15285 | 0, // qsub2_then_dsub |
| 15286 | 0, // qsub2_then_hsub |
| 15287 | 0, // qsub2_then_ssub |
| 15288 | 0, // x8sub_7_then_sub_32 |
| 15289 | 0, // x8sub_6_then_sub_32 |
| 15290 | 0, // x8sub_5_then_sub_32 |
| 15291 | 0, // x8sub_4_then_sub_32 |
| 15292 | 0, // x8sub_3_then_sub_32 |
| 15293 | 0, // x8sub_2_then_sub_32 |
| 15294 | 0, // x8sub_1_then_sub_32 |
| 15295 | 0, // subo64_then_sub_32 |
| 15296 | 0, // zsub1_then_bsub |
| 15297 | 0, // zsub1_then_dsub |
| 15298 | 0, // zsub1_then_hsub |
| 15299 | 0, // zsub1_then_ssub |
| 15300 | 0, // zsub1_then_zsub |
| 15301 | 0, // zsub1_then_zsub_hi |
| 15302 | 0, // zsub3_then_bsub |
| 15303 | 0, // zsub3_then_dsub |
| 15304 | 0, // zsub3_then_hsub |
| 15305 | 0, // zsub3_then_ssub |
| 15306 | 0, // zsub3_then_zsub |
| 15307 | 0, // zsub3_then_zsub_hi |
| 15308 | 0, // zsub2_then_bsub |
| 15309 | 0, // zsub2_then_dsub |
| 15310 | 0, // zsub2_then_hsub |
| 15311 | 0, // zsub2_then_ssub |
| 15312 | 0, // zsub2_then_zsub |
| 15313 | 0, // zsub2_then_zsub_hi |
| 15314 | 0, // dsub0_dsub1 |
| 15315 | 0, // dsub0_dsub1_dsub2 |
| 15316 | 0, // dsub1_dsub2 |
| 15317 | 0, // dsub1_dsub2_dsub3 |
| 15318 | 0, // dsub2_dsub3 |
| 15319 | 0, // dsub_qsub1_then_dsub |
| 15320 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15321 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15322 | 0, // qsub0_qsub1 |
| 15323 | 0, // qsub0_qsub1_qsub2 |
| 15324 | 0, // qsub1_qsub2 |
| 15325 | 0, // qsub1_qsub2_qsub3 |
| 15326 | 0, // qsub2_qsub3 |
| 15327 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15328 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15329 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15330 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15331 | 0, // x8sub_0_x8sub_1 |
| 15332 | 0, // x8sub_2_x8sub_3 |
| 15333 | 0, // x8sub_4_x8sub_5 |
| 15334 | 0, // x8sub_6_x8sub_7 |
| 15335 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15336 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15337 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15338 | 0, // sub_32_subo64_then_sub_32 |
| 15339 | 0, // dsub_zsub1_then_dsub |
| 15340 | 0, // zsub_zsub1_then_zsub |
| 15341 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15342 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15343 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15344 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15345 | 0, // zsub0_zsub1 |
| 15346 | 0, // zsub0_zsub1_zsub2 |
| 15347 | 0, // zsub1_zsub2 |
| 15348 | 0, // zsub1_zsub2_zsub3 |
| 15349 | 0, // zsub2_zsub3 |
| 15350 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15351 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15352 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15353 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15354 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15355 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15356 | }, |
| 15357 | { // GPR64all |
| 15358 | 0, // bsub |
| 15359 | 0, // dsub |
| 15360 | 0, // dsub0 |
| 15361 | 0, // dsub1 |
| 15362 | 0, // dsub2 |
| 15363 | 0, // dsub3 |
| 15364 | 0, // hsub |
| 15365 | 0, // qhisub |
| 15366 | 0, // qsub |
| 15367 | 0, // qsub0 |
| 15368 | 0, // qsub1 |
| 15369 | 0, // qsub2 |
| 15370 | 0, // qsub3 |
| 15371 | 0, // ssub |
| 15372 | 18, // sub_32 -> GPR64all |
| 15373 | 0, // sube32 |
| 15374 | 0, // sube64 |
| 15375 | 0, // subo32 |
| 15376 | 0, // subo64 |
| 15377 | 0, // x8sub_0 |
| 15378 | 0, // x8sub_1 |
| 15379 | 0, // x8sub_2 |
| 15380 | 0, // x8sub_3 |
| 15381 | 0, // x8sub_4 |
| 15382 | 0, // x8sub_5 |
| 15383 | 0, // x8sub_6 |
| 15384 | 0, // x8sub_7 |
| 15385 | 0, // zsub |
| 15386 | 0, // zsub0 |
| 15387 | 0, // zsub1 |
| 15388 | 0, // zsub2 |
| 15389 | 0, // zsub3 |
| 15390 | 0, // zsub_hi |
| 15391 | 0, // dsub1_then_bsub |
| 15392 | 0, // dsub1_then_hsub |
| 15393 | 0, // dsub1_then_ssub |
| 15394 | 0, // dsub3_then_bsub |
| 15395 | 0, // dsub3_then_hsub |
| 15396 | 0, // dsub3_then_ssub |
| 15397 | 0, // dsub2_then_bsub |
| 15398 | 0, // dsub2_then_hsub |
| 15399 | 0, // dsub2_then_ssub |
| 15400 | 0, // qsub1_then_bsub |
| 15401 | 0, // qsub1_then_dsub |
| 15402 | 0, // qsub1_then_hsub |
| 15403 | 0, // qsub1_then_ssub |
| 15404 | 0, // qsub3_then_bsub |
| 15405 | 0, // qsub3_then_dsub |
| 15406 | 0, // qsub3_then_hsub |
| 15407 | 0, // qsub3_then_ssub |
| 15408 | 0, // qsub2_then_bsub |
| 15409 | 0, // qsub2_then_dsub |
| 15410 | 0, // qsub2_then_hsub |
| 15411 | 0, // qsub2_then_ssub |
| 15412 | 0, // x8sub_7_then_sub_32 |
| 15413 | 0, // x8sub_6_then_sub_32 |
| 15414 | 0, // x8sub_5_then_sub_32 |
| 15415 | 0, // x8sub_4_then_sub_32 |
| 15416 | 0, // x8sub_3_then_sub_32 |
| 15417 | 0, // x8sub_2_then_sub_32 |
| 15418 | 0, // x8sub_1_then_sub_32 |
| 15419 | 0, // subo64_then_sub_32 |
| 15420 | 0, // zsub1_then_bsub |
| 15421 | 0, // zsub1_then_dsub |
| 15422 | 0, // zsub1_then_hsub |
| 15423 | 0, // zsub1_then_ssub |
| 15424 | 0, // zsub1_then_zsub |
| 15425 | 0, // zsub1_then_zsub_hi |
| 15426 | 0, // zsub3_then_bsub |
| 15427 | 0, // zsub3_then_dsub |
| 15428 | 0, // zsub3_then_hsub |
| 15429 | 0, // zsub3_then_ssub |
| 15430 | 0, // zsub3_then_zsub |
| 15431 | 0, // zsub3_then_zsub_hi |
| 15432 | 0, // zsub2_then_bsub |
| 15433 | 0, // zsub2_then_dsub |
| 15434 | 0, // zsub2_then_hsub |
| 15435 | 0, // zsub2_then_ssub |
| 15436 | 0, // zsub2_then_zsub |
| 15437 | 0, // zsub2_then_zsub_hi |
| 15438 | 0, // dsub0_dsub1 |
| 15439 | 0, // dsub0_dsub1_dsub2 |
| 15440 | 0, // dsub1_dsub2 |
| 15441 | 0, // dsub1_dsub2_dsub3 |
| 15442 | 0, // dsub2_dsub3 |
| 15443 | 0, // dsub_qsub1_then_dsub |
| 15444 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15445 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15446 | 0, // qsub0_qsub1 |
| 15447 | 0, // qsub0_qsub1_qsub2 |
| 15448 | 0, // qsub1_qsub2 |
| 15449 | 0, // qsub1_qsub2_qsub3 |
| 15450 | 0, // qsub2_qsub3 |
| 15451 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15452 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15453 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15454 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15455 | 0, // x8sub_0_x8sub_1 |
| 15456 | 0, // x8sub_2_x8sub_3 |
| 15457 | 0, // x8sub_4_x8sub_5 |
| 15458 | 0, // x8sub_6_x8sub_7 |
| 15459 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15460 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15461 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15462 | 0, // sub_32_subo64_then_sub_32 |
| 15463 | 0, // dsub_zsub1_then_dsub |
| 15464 | 0, // zsub_zsub1_then_zsub |
| 15465 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15466 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15467 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15468 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15469 | 0, // zsub0_zsub1 |
| 15470 | 0, // zsub0_zsub1_zsub2 |
| 15471 | 0, // zsub1_zsub2 |
| 15472 | 0, // zsub1_zsub2_zsub3 |
| 15473 | 0, // zsub2_zsub3 |
| 15474 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15475 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15476 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15477 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15478 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15479 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15480 | }, |
| 15481 | { // FPR64 |
| 15482 | 19, // bsub -> FPR64 |
| 15483 | 0, // dsub |
| 15484 | 0, // dsub0 |
| 15485 | 0, // dsub1 |
| 15486 | 0, // dsub2 |
| 15487 | 0, // dsub3 |
| 15488 | 19, // hsub -> FPR64 |
| 15489 | 0, // qhisub |
| 15490 | 0, // qsub |
| 15491 | 0, // qsub0 |
| 15492 | 0, // qsub1 |
| 15493 | 0, // qsub2 |
| 15494 | 0, // qsub3 |
| 15495 | 19, // ssub -> FPR64 |
| 15496 | 0, // sub_32 |
| 15497 | 0, // sube32 |
| 15498 | 0, // sube64 |
| 15499 | 0, // subo32 |
| 15500 | 0, // subo64 |
| 15501 | 0, // x8sub_0 |
| 15502 | 0, // x8sub_1 |
| 15503 | 0, // x8sub_2 |
| 15504 | 0, // x8sub_3 |
| 15505 | 0, // x8sub_4 |
| 15506 | 0, // x8sub_5 |
| 15507 | 0, // x8sub_6 |
| 15508 | 0, // x8sub_7 |
| 15509 | 0, // zsub |
| 15510 | 0, // zsub0 |
| 15511 | 0, // zsub1 |
| 15512 | 0, // zsub2 |
| 15513 | 0, // zsub3 |
| 15514 | 0, // zsub_hi |
| 15515 | 0, // dsub1_then_bsub |
| 15516 | 0, // dsub1_then_hsub |
| 15517 | 0, // dsub1_then_ssub |
| 15518 | 0, // dsub3_then_bsub |
| 15519 | 0, // dsub3_then_hsub |
| 15520 | 0, // dsub3_then_ssub |
| 15521 | 0, // dsub2_then_bsub |
| 15522 | 0, // dsub2_then_hsub |
| 15523 | 0, // dsub2_then_ssub |
| 15524 | 0, // qsub1_then_bsub |
| 15525 | 0, // qsub1_then_dsub |
| 15526 | 0, // qsub1_then_hsub |
| 15527 | 0, // qsub1_then_ssub |
| 15528 | 0, // qsub3_then_bsub |
| 15529 | 0, // qsub3_then_dsub |
| 15530 | 0, // qsub3_then_hsub |
| 15531 | 0, // qsub3_then_ssub |
| 15532 | 0, // qsub2_then_bsub |
| 15533 | 0, // qsub2_then_dsub |
| 15534 | 0, // qsub2_then_hsub |
| 15535 | 0, // qsub2_then_ssub |
| 15536 | 0, // x8sub_7_then_sub_32 |
| 15537 | 0, // x8sub_6_then_sub_32 |
| 15538 | 0, // x8sub_5_then_sub_32 |
| 15539 | 0, // x8sub_4_then_sub_32 |
| 15540 | 0, // x8sub_3_then_sub_32 |
| 15541 | 0, // x8sub_2_then_sub_32 |
| 15542 | 0, // x8sub_1_then_sub_32 |
| 15543 | 0, // subo64_then_sub_32 |
| 15544 | 0, // zsub1_then_bsub |
| 15545 | 0, // zsub1_then_dsub |
| 15546 | 0, // zsub1_then_hsub |
| 15547 | 0, // zsub1_then_ssub |
| 15548 | 0, // zsub1_then_zsub |
| 15549 | 0, // zsub1_then_zsub_hi |
| 15550 | 0, // zsub3_then_bsub |
| 15551 | 0, // zsub3_then_dsub |
| 15552 | 0, // zsub3_then_hsub |
| 15553 | 0, // zsub3_then_ssub |
| 15554 | 0, // zsub3_then_zsub |
| 15555 | 0, // zsub3_then_zsub_hi |
| 15556 | 0, // zsub2_then_bsub |
| 15557 | 0, // zsub2_then_dsub |
| 15558 | 0, // zsub2_then_hsub |
| 15559 | 0, // zsub2_then_ssub |
| 15560 | 0, // zsub2_then_zsub |
| 15561 | 0, // zsub2_then_zsub_hi |
| 15562 | 0, // dsub0_dsub1 |
| 15563 | 0, // dsub0_dsub1_dsub2 |
| 15564 | 0, // dsub1_dsub2 |
| 15565 | 0, // dsub1_dsub2_dsub3 |
| 15566 | 0, // dsub2_dsub3 |
| 15567 | 0, // dsub_qsub1_then_dsub |
| 15568 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15569 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15570 | 0, // qsub0_qsub1 |
| 15571 | 0, // qsub0_qsub1_qsub2 |
| 15572 | 0, // qsub1_qsub2 |
| 15573 | 0, // qsub1_qsub2_qsub3 |
| 15574 | 0, // qsub2_qsub3 |
| 15575 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15576 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15577 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15578 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15579 | 0, // x8sub_0_x8sub_1 |
| 15580 | 0, // x8sub_2_x8sub_3 |
| 15581 | 0, // x8sub_4_x8sub_5 |
| 15582 | 0, // x8sub_6_x8sub_7 |
| 15583 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15584 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15585 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15586 | 0, // sub_32_subo64_then_sub_32 |
| 15587 | 0, // dsub_zsub1_then_dsub |
| 15588 | 0, // zsub_zsub1_then_zsub |
| 15589 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15590 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15591 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15592 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15593 | 0, // zsub0_zsub1 |
| 15594 | 0, // zsub0_zsub1_zsub2 |
| 15595 | 0, // zsub1_zsub2 |
| 15596 | 0, // zsub1_zsub2_zsub3 |
| 15597 | 0, // zsub2_zsub3 |
| 15598 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15599 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15600 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15601 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15602 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15603 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15604 | }, |
| 15605 | { // GPR64 |
| 15606 | 0, // bsub |
| 15607 | 0, // dsub |
| 15608 | 0, // dsub0 |
| 15609 | 0, // dsub1 |
| 15610 | 0, // dsub2 |
| 15611 | 0, // dsub3 |
| 15612 | 0, // hsub |
| 15613 | 0, // qhisub |
| 15614 | 0, // qsub |
| 15615 | 0, // qsub0 |
| 15616 | 0, // qsub1 |
| 15617 | 0, // qsub2 |
| 15618 | 0, // qsub3 |
| 15619 | 0, // ssub |
| 15620 | 20, // sub_32 -> GPR64 |
| 15621 | 0, // sube32 |
| 15622 | 0, // sube64 |
| 15623 | 0, // subo32 |
| 15624 | 0, // subo64 |
| 15625 | 0, // x8sub_0 |
| 15626 | 0, // x8sub_1 |
| 15627 | 0, // x8sub_2 |
| 15628 | 0, // x8sub_3 |
| 15629 | 0, // x8sub_4 |
| 15630 | 0, // x8sub_5 |
| 15631 | 0, // x8sub_6 |
| 15632 | 0, // x8sub_7 |
| 15633 | 0, // zsub |
| 15634 | 0, // zsub0 |
| 15635 | 0, // zsub1 |
| 15636 | 0, // zsub2 |
| 15637 | 0, // zsub3 |
| 15638 | 0, // zsub_hi |
| 15639 | 0, // dsub1_then_bsub |
| 15640 | 0, // dsub1_then_hsub |
| 15641 | 0, // dsub1_then_ssub |
| 15642 | 0, // dsub3_then_bsub |
| 15643 | 0, // dsub3_then_hsub |
| 15644 | 0, // dsub3_then_ssub |
| 15645 | 0, // dsub2_then_bsub |
| 15646 | 0, // dsub2_then_hsub |
| 15647 | 0, // dsub2_then_ssub |
| 15648 | 0, // qsub1_then_bsub |
| 15649 | 0, // qsub1_then_dsub |
| 15650 | 0, // qsub1_then_hsub |
| 15651 | 0, // qsub1_then_ssub |
| 15652 | 0, // qsub3_then_bsub |
| 15653 | 0, // qsub3_then_dsub |
| 15654 | 0, // qsub3_then_hsub |
| 15655 | 0, // qsub3_then_ssub |
| 15656 | 0, // qsub2_then_bsub |
| 15657 | 0, // qsub2_then_dsub |
| 15658 | 0, // qsub2_then_hsub |
| 15659 | 0, // qsub2_then_ssub |
| 15660 | 0, // x8sub_7_then_sub_32 |
| 15661 | 0, // x8sub_6_then_sub_32 |
| 15662 | 0, // x8sub_5_then_sub_32 |
| 15663 | 0, // x8sub_4_then_sub_32 |
| 15664 | 0, // x8sub_3_then_sub_32 |
| 15665 | 0, // x8sub_2_then_sub_32 |
| 15666 | 0, // x8sub_1_then_sub_32 |
| 15667 | 0, // subo64_then_sub_32 |
| 15668 | 0, // zsub1_then_bsub |
| 15669 | 0, // zsub1_then_dsub |
| 15670 | 0, // zsub1_then_hsub |
| 15671 | 0, // zsub1_then_ssub |
| 15672 | 0, // zsub1_then_zsub |
| 15673 | 0, // zsub1_then_zsub_hi |
| 15674 | 0, // zsub3_then_bsub |
| 15675 | 0, // zsub3_then_dsub |
| 15676 | 0, // zsub3_then_hsub |
| 15677 | 0, // zsub3_then_ssub |
| 15678 | 0, // zsub3_then_zsub |
| 15679 | 0, // zsub3_then_zsub_hi |
| 15680 | 0, // zsub2_then_bsub |
| 15681 | 0, // zsub2_then_dsub |
| 15682 | 0, // zsub2_then_hsub |
| 15683 | 0, // zsub2_then_ssub |
| 15684 | 0, // zsub2_then_zsub |
| 15685 | 0, // zsub2_then_zsub_hi |
| 15686 | 0, // dsub0_dsub1 |
| 15687 | 0, // dsub0_dsub1_dsub2 |
| 15688 | 0, // dsub1_dsub2 |
| 15689 | 0, // dsub1_dsub2_dsub3 |
| 15690 | 0, // dsub2_dsub3 |
| 15691 | 0, // dsub_qsub1_then_dsub |
| 15692 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15693 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15694 | 0, // qsub0_qsub1 |
| 15695 | 0, // qsub0_qsub1_qsub2 |
| 15696 | 0, // qsub1_qsub2 |
| 15697 | 0, // qsub1_qsub2_qsub3 |
| 15698 | 0, // qsub2_qsub3 |
| 15699 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15700 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15701 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15702 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15703 | 0, // x8sub_0_x8sub_1 |
| 15704 | 0, // x8sub_2_x8sub_3 |
| 15705 | 0, // x8sub_4_x8sub_5 |
| 15706 | 0, // x8sub_6_x8sub_7 |
| 15707 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15708 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15709 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15710 | 0, // sub_32_subo64_then_sub_32 |
| 15711 | 0, // dsub_zsub1_then_dsub |
| 15712 | 0, // zsub_zsub1_then_zsub |
| 15713 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15714 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15715 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15716 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15717 | 0, // zsub0_zsub1 |
| 15718 | 0, // zsub0_zsub1_zsub2 |
| 15719 | 0, // zsub1_zsub2 |
| 15720 | 0, // zsub1_zsub2_zsub3 |
| 15721 | 0, // zsub2_zsub3 |
| 15722 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15723 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15724 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15725 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15726 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15727 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15728 | }, |
| 15729 | { // GPR64sp |
| 15730 | 0, // bsub |
| 15731 | 0, // dsub |
| 15732 | 0, // dsub0 |
| 15733 | 0, // dsub1 |
| 15734 | 0, // dsub2 |
| 15735 | 0, // dsub3 |
| 15736 | 0, // hsub |
| 15737 | 0, // qhisub |
| 15738 | 0, // qsub |
| 15739 | 0, // qsub0 |
| 15740 | 0, // qsub1 |
| 15741 | 0, // qsub2 |
| 15742 | 0, // qsub3 |
| 15743 | 0, // ssub |
| 15744 | 21, // sub_32 -> GPR64sp |
| 15745 | 0, // sube32 |
| 15746 | 0, // sube64 |
| 15747 | 0, // subo32 |
| 15748 | 0, // subo64 |
| 15749 | 0, // x8sub_0 |
| 15750 | 0, // x8sub_1 |
| 15751 | 0, // x8sub_2 |
| 15752 | 0, // x8sub_3 |
| 15753 | 0, // x8sub_4 |
| 15754 | 0, // x8sub_5 |
| 15755 | 0, // x8sub_6 |
| 15756 | 0, // x8sub_7 |
| 15757 | 0, // zsub |
| 15758 | 0, // zsub0 |
| 15759 | 0, // zsub1 |
| 15760 | 0, // zsub2 |
| 15761 | 0, // zsub3 |
| 15762 | 0, // zsub_hi |
| 15763 | 0, // dsub1_then_bsub |
| 15764 | 0, // dsub1_then_hsub |
| 15765 | 0, // dsub1_then_ssub |
| 15766 | 0, // dsub3_then_bsub |
| 15767 | 0, // dsub3_then_hsub |
| 15768 | 0, // dsub3_then_ssub |
| 15769 | 0, // dsub2_then_bsub |
| 15770 | 0, // dsub2_then_hsub |
| 15771 | 0, // dsub2_then_ssub |
| 15772 | 0, // qsub1_then_bsub |
| 15773 | 0, // qsub1_then_dsub |
| 15774 | 0, // qsub1_then_hsub |
| 15775 | 0, // qsub1_then_ssub |
| 15776 | 0, // qsub3_then_bsub |
| 15777 | 0, // qsub3_then_dsub |
| 15778 | 0, // qsub3_then_hsub |
| 15779 | 0, // qsub3_then_ssub |
| 15780 | 0, // qsub2_then_bsub |
| 15781 | 0, // qsub2_then_dsub |
| 15782 | 0, // qsub2_then_hsub |
| 15783 | 0, // qsub2_then_ssub |
| 15784 | 0, // x8sub_7_then_sub_32 |
| 15785 | 0, // x8sub_6_then_sub_32 |
| 15786 | 0, // x8sub_5_then_sub_32 |
| 15787 | 0, // x8sub_4_then_sub_32 |
| 15788 | 0, // x8sub_3_then_sub_32 |
| 15789 | 0, // x8sub_2_then_sub_32 |
| 15790 | 0, // x8sub_1_then_sub_32 |
| 15791 | 0, // subo64_then_sub_32 |
| 15792 | 0, // zsub1_then_bsub |
| 15793 | 0, // zsub1_then_dsub |
| 15794 | 0, // zsub1_then_hsub |
| 15795 | 0, // zsub1_then_ssub |
| 15796 | 0, // zsub1_then_zsub |
| 15797 | 0, // zsub1_then_zsub_hi |
| 15798 | 0, // zsub3_then_bsub |
| 15799 | 0, // zsub3_then_dsub |
| 15800 | 0, // zsub3_then_hsub |
| 15801 | 0, // zsub3_then_ssub |
| 15802 | 0, // zsub3_then_zsub |
| 15803 | 0, // zsub3_then_zsub_hi |
| 15804 | 0, // zsub2_then_bsub |
| 15805 | 0, // zsub2_then_dsub |
| 15806 | 0, // zsub2_then_hsub |
| 15807 | 0, // zsub2_then_ssub |
| 15808 | 0, // zsub2_then_zsub |
| 15809 | 0, // zsub2_then_zsub_hi |
| 15810 | 0, // dsub0_dsub1 |
| 15811 | 0, // dsub0_dsub1_dsub2 |
| 15812 | 0, // dsub1_dsub2 |
| 15813 | 0, // dsub1_dsub2_dsub3 |
| 15814 | 0, // dsub2_dsub3 |
| 15815 | 0, // dsub_qsub1_then_dsub |
| 15816 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15817 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15818 | 0, // qsub0_qsub1 |
| 15819 | 0, // qsub0_qsub1_qsub2 |
| 15820 | 0, // qsub1_qsub2 |
| 15821 | 0, // qsub1_qsub2_qsub3 |
| 15822 | 0, // qsub2_qsub3 |
| 15823 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15824 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15825 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15826 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15827 | 0, // x8sub_0_x8sub_1 |
| 15828 | 0, // x8sub_2_x8sub_3 |
| 15829 | 0, // x8sub_4_x8sub_5 |
| 15830 | 0, // x8sub_6_x8sub_7 |
| 15831 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15832 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15833 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15834 | 0, // sub_32_subo64_then_sub_32 |
| 15835 | 0, // dsub_zsub1_then_dsub |
| 15836 | 0, // zsub_zsub1_then_zsub |
| 15837 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15838 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15839 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15840 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15841 | 0, // zsub0_zsub1 |
| 15842 | 0, // zsub0_zsub1_zsub2 |
| 15843 | 0, // zsub1_zsub2 |
| 15844 | 0, // zsub1_zsub2_zsub3 |
| 15845 | 0, // zsub2_zsub3 |
| 15846 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15847 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15848 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15849 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15850 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15851 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15852 | }, |
| 15853 | { // GPR64common |
| 15854 | 0, // bsub |
| 15855 | 0, // dsub |
| 15856 | 0, // dsub0 |
| 15857 | 0, // dsub1 |
| 15858 | 0, // dsub2 |
| 15859 | 0, // dsub3 |
| 15860 | 0, // hsub |
| 15861 | 0, // qhisub |
| 15862 | 0, // qsub |
| 15863 | 0, // qsub0 |
| 15864 | 0, // qsub1 |
| 15865 | 0, // qsub2 |
| 15866 | 0, // qsub3 |
| 15867 | 0, // ssub |
| 15868 | 22, // sub_32 -> GPR64common |
| 15869 | 0, // sube32 |
| 15870 | 0, // sube64 |
| 15871 | 0, // subo32 |
| 15872 | 0, // subo64 |
| 15873 | 0, // x8sub_0 |
| 15874 | 0, // x8sub_1 |
| 15875 | 0, // x8sub_2 |
| 15876 | 0, // x8sub_3 |
| 15877 | 0, // x8sub_4 |
| 15878 | 0, // x8sub_5 |
| 15879 | 0, // x8sub_6 |
| 15880 | 0, // x8sub_7 |
| 15881 | 0, // zsub |
| 15882 | 0, // zsub0 |
| 15883 | 0, // zsub1 |
| 15884 | 0, // zsub2 |
| 15885 | 0, // zsub3 |
| 15886 | 0, // zsub_hi |
| 15887 | 0, // dsub1_then_bsub |
| 15888 | 0, // dsub1_then_hsub |
| 15889 | 0, // dsub1_then_ssub |
| 15890 | 0, // dsub3_then_bsub |
| 15891 | 0, // dsub3_then_hsub |
| 15892 | 0, // dsub3_then_ssub |
| 15893 | 0, // dsub2_then_bsub |
| 15894 | 0, // dsub2_then_hsub |
| 15895 | 0, // dsub2_then_ssub |
| 15896 | 0, // qsub1_then_bsub |
| 15897 | 0, // qsub1_then_dsub |
| 15898 | 0, // qsub1_then_hsub |
| 15899 | 0, // qsub1_then_ssub |
| 15900 | 0, // qsub3_then_bsub |
| 15901 | 0, // qsub3_then_dsub |
| 15902 | 0, // qsub3_then_hsub |
| 15903 | 0, // qsub3_then_ssub |
| 15904 | 0, // qsub2_then_bsub |
| 15905 | 0, // qsub2_then_dsub |
| 15906 | 0, // qsub2_then_hsub |
| 15907 | 0, // qsub2_then_ssub |
| 15908 | 0, // x8sub_7_then_sub_32 |
| 15909 | 0, // x8sub_6_then_sub_32 |
| 15910 | 0, // x8sub_5_then_sub_32 |
| 15911 | 0, // x8sub_4_then_sub_32 |
| 15912 | 0, // x8sub_3_then_sub_32 |
| 15913 | 0, // x8sub_2_then_sub_32 |
| 15914 | 0, // x8sub_1_then_sub_32 |
| 15915 | 0, // subo64_then_sub_32 |
| 15916 | 0, // zsub1_then_bsub |
| 15917 | 0, // zsub1_then_dsub |
| 15918 | 0, // zsub1_then_hsub |
| 15919 | 0, // zsub1_then_ssub |
| 15920 | 0, // zsub1_then_zsub |
| 15921 | 0, // zsub1_then_zsub_hi |
| 15922 | 0, // zsub3_then_bsub |
| 15923 | 0, // zsub3_then_dsub |
| 15924 | 0, // zsub3_then_hsub |
| 15925 | 0, // zsub3_then_ssub |
| 15926 | 0, // zsub3_then_zsub |
| 15927 | 0, // zsub3_then_zsub_hi |
| 15928 | 0, // zsub2_then_bsub |
| 15929 | 0, // zsub2_then_dsub |
| 15930 | 0, // zsub2_then_hsub |
| 15931 | 0, // zsub2_then_ssub |
| 15932 | 0, // zsub2_then_zsub |
| 15933 | 0, // zsub2_then_zsub_hi |
| 15934 | 0, // dsub0_dsub1 |
| 15935 | 0, // dsub0_dsub1_dsub2 |
| 15936 | 0, // dsub1_dsub2 |
| 15937 | 0, // dsub1_dsub2_dsub3 |
| 15938 | 0, // dsub2_dsub3 |
| 15939 | 0, // dsub_qsub1_then_dsub |
| 15940 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15941 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 15942 | 0, // qsub0_qsub1 |
| 15943 | 0, // qsub0_qsub1_qsub2 |
| 15944 | 0, // qsub1_qsub2 |
| 15945 | 0, // qsub1_qsub2_qsub3 |
| 15946 | 0, // qsub2_qsub3 |
| 15947 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 15948 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 15949 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 15950 | 0, // sub_32_x8sub_1_then_sub_32 |
| 15951 | 0, // x8sub_0_x8sub_1 |
| 15952 | 0, // x8sub_2_x8sub_3 |
| 15953 | 0, // x8sub_4_x8sub_5 |
| 15954 | 0, // x8sub_6_x8sub_7 |
| 15955 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 15956 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 15957 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 15958 | 0, // sub_32_subo64_then_sub_32 |
| 15959 | 0, // dsub_zsub1_then_dsub |
| 15960 | 0, // zsub_zsub1_then_zsub |
| 15961 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15962 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 15963 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15964 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 15965 | 0, // zsub0_zsub1 |
| 15966 | 0, // zsub0_zsub1_zsub2 |
| 15967 | 0, // zsub1_zsub2 |
| 15968 | 0, // zsub1_zsub2_zsub3 |
| 15969 | 0, // zsub2_zsub3 |
| 15970 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 15971 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 15972 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 15973 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 15974 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 15975 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 15976 | }, |
| 15977 | { // GPR64noip |
| 15978 | 0, // bsub |
| 15979 | 0, // dsub |
| 15980 | 0, // dsub0 |
| 15981 | 0, // dsub1 |
| 15982 | 0, // dsub2 |
| 15983 | 0, // dsub3 |
| 15984 | 0, // hsub |
| 15985 | 0, // qhisub |
| 15986 | 0, // qsub |
| 15987 | 0, // qsub0 |
| 15988 | 0, // qsub1 |
| 15989 | 0, // qsub2 |
| 15990 | 0, // qsub3 |
| 15991 | 0, // ssub |
| 15992 | 23, // sub_32 -> GPR64noip |
| 15993 | 0, // sube32 |
| 15994 | 0, // sube64 |
| 15995 | 0, // subo32 |
| 15996 | 0, // subo64 |
| 15997 | 0, // x8sub_0 |
| 15998 | 0, // x8sub_1 |
| 15999 | 0, // x8sub_2 |
| 16000 | 0, // x8sub_3 |
| 16001 | 0, // x8sub_4 |
| 16002 | 0, // x8sub_5 |
| 16003 | 0, // x8sub_6 |
| 16004 | 0, // x8sub_7 |
| 16005 | 0, // zsub |
| 16006 | 0, // zsub0 |
| 16007 | 0, // zsub1 |
| 16008 | 0, // zsub2 |
| 16009 | 0, // zsub3 |
| 16010 | 0, // zsub_hi |
| 16011 | 0, // dsub1_then_bsub |
| 16012 | 0, // dsub1_then_hsub |
| 16013 | 0, // dsub1_then_ssub |
| 16014 | 0, // dsub3_then_bsub |
| 16015 | 0, // dsub3_then_hsub |
| 16016 | 0, // dsub3_then_ssub |
| 16017 | 0, // dsub2_then_bsub |
| 16018 | 0, // dsub2_then_hsub |
| 16019 | 0, // dsub2_then_ssub |
| 16020 | 0, // qsub1_then_bsub |
| 16021 | 0, // qsub1_then_dsub |
| 16022 | 0, // qsub1_then_hsub |
| 16023 | 0, // qsub1_then_ssub |
| 16024 | 0, // qsub3_then_bsub |
| 16025 | 0, // qsub3_then_dsub |
| 16026 | 0, // qsub3_then_hsub |
| 16027 | 0, // qsub3_then_ssub |
| 16028 | 0, // qsub2_then_bsub |
| 16029 | 0, // qsub2_then_dsub |
| 16030 | 0, // qsub2_then_hsub |
| 16031 | 0, // qsub2_then_ssub |
| 16032 | 0, // x8sub_7_then_sub_32 |
| 16033 | 0, // x8sub_6_then_sub_32 |
| 16034 | 0, // x8sub_5_then_sub_32 |
| 16035 | 0, // x8sub_4_then_sub_32 |
| 16036 | 0, // x8sub_3_then_sub_32 |
| 16037 | 0, // x8sub_2_then_sub_32 |
| 16038 | 0, // x8sub_1_then_sub_32 |
| 16039 | 0, // subo64_then_sub_32 |
| 16040 | 0, // zsub1_then_bsub |
| 16041 | 0, // zsub1_then_dsub |
| 16042 | 0, // zsub1_then_hsub |
| 16043 | 0, // zsub1_then_ssub |
| 16044 | 0, // zsub1_then_zsub |
| 16045 | 0, // zsub1_then_zsub_hi |
| 16046 | 0, // zsub3_then_bsub |
| 16047 | 0, // zsub3_then_dsub |
| 16048 | 0, // zsub3_then_hsub |
| 16049 | 0, // zsub3_then_ssub |
| 16050 | 0, // zsub3_then_zsub |
| 16051 | 0, // zsub3_then_zsub_hi |
| 16052 | 0, // zsub2_then_bsub |
| 16053 | 0, // zsub2_then_dsub |
| 16054 | 0, // zsub2_then_hsub |
| 16055 | 0, // zsub2_then_ssub |
| 16056 | 0, // zsub2_then_zsub |
| 16057 | 0, // zsub2_then_zsub_hi |
| 16058 | 0, // dsub0_dsub1 |
| 16059 | 0, // dsub0_dsub1_dsub2 |
| 16060 | 0, // dsub1_dsub2 |
| 16061 | 0, // dsub1_dsub2_dsub3 |
| 16062 | 0, // dsub2_dsub3 |
| 16063 | 0, // dsub_qsub1_then_dsub |
| 16064 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16065 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16066 | 0, // qsub0_qsub1 |
| 16067 | 0, // qsub0_qsub1_qsub2 |
| 16068 | 0, // qsub1_qsub2 |
| 16069 | 0, // qsub1_qsub2_qsub3 |
| 16070 | 0, // qsub2_qsub3 |
| 16071 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16072 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16073 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16074 | 0, // sub_32_x8sub_1_then_sub_32 |
| 16075 | 0, // x8sub_0_x8sub_1 |
| 16076 | 0, // x8sub_2_x8sub_3 |
| 16077 | 0, // x8sub_4_x8sub_5 |
| 16078 | 0, // x8sub_6_x8sub_7 |
| 16079 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 16080 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 16081 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 16082 | 0, // sub_32_subo64_then_sub_32 |
| 16083 | 0, // dsub_zsub1_then_dsub |
| 16084 | 0, // zsub_zsub1_then_zsub |
| 16085 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16086 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16087 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16088 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16089 | 0, // zsub0_zsub1 |
| 16090 | 0, // zsub0_zsub1_zsub2 |
| 16091 | 0, // zsub1_zsub2 |
| 16092 | 0, // zsub1_zsub2_zsub3 |
| 16093 | 0, // zsub2_zsub3 |
| 16094 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16095 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16096 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16097 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16098 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16099 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16100 | }, |
| 16101 | { // GPR64common_and_GPR64noip |
| 16102 | 0, // bsub |
| 16103 | 0, // dsub |
| 16104 | 0, // dsub0 |
| 16105 | 0, // dsub1 |
| 16106 | 0, // dsub2 |
| 16107 | 0, // dsub3 |
| 16108 | 0, // hsub |
| 16109 | 0, // qhisub |
| 16110 | 0, // qsub |
| 16111 | 0, // qsub0 |
| 16112 | 0, // qsub1 |
| 16113 | 0, // qsub2 |
| 16114 | 0, // qsub3 |
| 16115 | 0, // ssub |
| 16116 | 24, // sub_32 -> GPR64common_and_GPR64noip |
| 16117 | 0, // sube32 |
| 16118 | 0, // sube64 |
| 16119 | 0, // subo32 |
| 16120 | 0, // subo64 |
| 16121 | 0, // x8sub_0 |
| 16122 | 0, // x8sub_1 |
| 16123 | 0, // x8sub_2 |
| 16124 | 0, // x8sub_3 |
| 16125 | 0, // x8sub_4 |
| 16126 | 0, // x8sub_5 |
| 16127 | 0, // x8sub_6 |
| 16128 | 0, // x8sub_7 |
| 16129 | 0, // zsub |
| 16130 | 0, // zsub0 |
| 16131 | 0, // zsub1 |
| 16132 | 0, // zsub2 |
| 16133 | 0, // zsub3 |
| 16134 | 0, // zsub_hi |
| 16135 | 0, // dsub1_then_bsub |
| 16136 | 0, // dsub1_then_hsub |
| 16137 | 0, // dsub1_then_ssub |
| 16138 | 0, // dsub3_then_bsub |
| 16139 | 0, // dsub3_then_hsub |
| 16140 | 0, // dsub3_then_ssub |
| 16141 | 0, // dsub2_then_bsub |
| 16142 | 0, // dsub2_then_hsub |
| 16143 | 0, // dsub2_then_ssub |
| 16144 | 0, // qsub1_then_bsub |
| 16145 | 0, // qsub1_then_dsub |
| 16146 | 0, // qsub1_then_hsub |
| 16147 | 0, // qsub1_then_ssub |
| 16148 | 0, // qsub3_then_bsub |
| 16149 | 0, // qsub3_then_dsub |
| 16150 | 0, // qsub3_then_hsub |
| 16151 | 0, // qsub3_then_ssub |
| 16152 | 0, // qsub2_then_bsub |
| 16153 | 0, // qsub2_then_dsub |
| 16154 | 0, // qsub2_then_hsub |
| 16155 | 0, // qsub2_then_ssub |
| 16156 | 0, // x8sub_7_then_sub_32 |
| 16157 | 0, // x8sub_6_then_sub_32 |
| 16158 | 0, // x8sub_5_then_sub_32 |
| 16159 | 0, // x8sub_4_then_sub_32 |
| 16160 | 0, // x8sub_3_then_sub_32 |
| 16161 | 0, // x8sub_2_then_sub_32 |
| 16162 | 0, // x8sub_1_then_sub_32 |
| 16163 | 0, // subo64_then_sub_32 |
| 16164 | 0, // zsub1_then_bsub |
| 16165 | 0, // zsub1_then_dsub |
| 16166 | 0, // zsub1_then_hsub |
| 16167 | 0, // zsub1_then_ssub |
| 16168 | 0, // zsub1_then_zsub |
| 16169 | 0, // zsub1_then_zsub_hi |
| 16170 | 0, // zsub3_then_bsub |
| 16171 | 0, // zsub3_then_dsub |
| 16172 | 0, // zsub3_then_hsub |
| 16173 | 0, // zsub3_then_ssub |
| 16174 | 0, // zsub3_then_zsub |
| 16175 | 0, // zsub3_then_zsub_hi |
| 16176 | 0, // zsub2_then_bsub |
| 16177 | 0, // zsub2_then_dsub |
| 16178 | 0, // zsub2_then_hsub |
| 16179 | 0, // zsub2_then_ssub |
| 16180 | 0, // zsub2_then_zsub |
| 16181 | 0, // zsub2_then_zsub_hi |
| 16182 | 0, // dsub0_dsub1 |
| 16183 | 0, // dsub0_dsub1_dsub2 |
| 16184 | 0, // dsub1_dsub2 |
| 16185 | 0, // dsub1_dsub2_dsub3 |
| 16186 | 0, // dsub2_dsub3 |
| 16187 | 0, // dsub_qsub1_then_dsub |
| 16188 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16189 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16190 | 0, // qsub0_qsub1 |
| 16191 | 0, // qsub0_qsub1_qsub2 |
| 16192 | 0, // qsub1_qsub2 |
| 16193 | 0, // qsub1_qsub2_qsub3 |
| 16194 | 0, // qsub2_qsub3 |
| 16195 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16196 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16197 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16198 | 0, // sub_32_x8sub_1_then_sub_32 |
| 16199 | 0, // x8sub_0_x8sub_1 |
| 16200 | 0, // x8sub_2_x8sub_3 |
| 16201 | 0, // x8sub_4_x8sub_5 |
| 16202 | 0, // x8sub_6_x8sub_7 |
| 16203 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 16204 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 16205 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 16206 | 0, // sub_32_subo64_then_sub_32 |
| 16207 | 0, // dsub_zsub1_then_dsub |
| 16208 | 0, // zsub_zsub1_then_zsub |
| 16209 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16210 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16211 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16212 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16213 | 0, // zsub0_zsub1 |
| 16214 | 0, // zsub0_zsub1_zsub2 |
| 16215 | 0, // zsub1_zsub2 |
| 16216 | 0, // zsub1_zsub2_zsub3 |
| 16217 | 0, // zsub2_zsub3 |
| 16218 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16219 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16220 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16221 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16222 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16223 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16224 | }, |
| 16225 | { // tcGPR64 |
| 16226 | 0, // bsub |
| 16227 | 0, // dsub |
| 16228 | 0, // dsub0 |
| 16229 | 0, // dsub1 |
| 16230 | 0, // dsub2 |
| 16231 | 0, // dsub3 |
| 16232 | 0, // hsub |
| 16233 | 0, // qhisub |
| 16234 | 0, // qsub |
| 16235 | 0, // qsub0 |
| 16236 | 0, // qsub1 |
| 16237 | 0, // qsub2 |
| 16238 | 0, // qsub3 |
| 16239 | 0, // ssub |
| 16240 | 25, // sub_32 -> tcGPR64 |
| 16241 | 0, // sube32 |
| 16242 | 0, // sube64 |
| 16243 | 0, // subo32 |
| 16244 | 0, // subo64 |
| 16245 | 0, // x8sub_0 |
| 16246 | 0, // x8sub_1 |
| 16247 | 0, // x8sub_2 |
| 16248 | 0, // x8sub_3 |
| 16249 | 0, // x8sub_4 |
| 16250 | 0, // x8sub_5 |
| 16251 | 0, // x8sub_6 |
| 16252 | 0, // x8sub_7 |
| 16253 | 0, // zsub |
| 16254 | 0, // zsub0 |
| 16255 | 0, // zsub1 |
| 16256 | 0, // zsub2 |
| 16257 | 0, // zsub3 |
| 16258 | 0, // zsub_hi |
| 16259 | 0, // dsub1_then_bsub |
| 16260 | 0, // dsub1_then_hsub |
| 16261 | 0, // dsub1_then_ssub |
| 16262 | 0, // dsub3_then_bsub |
| 16263 | 0, // dsub3_then_hsub |
| 16264 | 0, // dsub3_then_ssub |
| 16265 | 0, // dsub2_then_bsub |
| 16266 | 0, // dsub2_then_hsub |
| 16267 | 0, // dsub2_then_ssub |
| 16268 | 0, // qsub1_then_bsub |
| 16269 | 0, // qsub1_then_dsub |
| 16270 | 0, // qsub1_then_hsub |
| 16271 | 0, // qsub1_then_ssub |
| 16272 | 0, // qsub3_then_bsub |
| 16273 | 0, // qsub3_then_dsub |
| 16274 | 0, // qsub3_then_hsub |
| 16275 | 0, // qsub3_then_ssub |
| 16276 | 0, // qsub2_then_bsub |
| 16277 | 0, // qsub2_then_dsub |
| 16278 | 0, // qsub2_then_hsub |
| 16279 | 0, // qsub2_then_ssub |
| 16280 | 0, // x8sub_7_then_sub_32 |
| 16281 | 0, // x8sub_6_then_sub_32 |
| 16282 | 0, // x8sub_5_then_sub_32 |
| 16283 | 0, // x8sub_4_then_sub_32 |
| 16284 | 0, // x8sub_3_then_sub_32 |
| 16285 | 0, // x8sub_2_then_sub_32 |
| 16286 | 0, // x8sub_1_then_sub_32 |
| 16287 | 0, // subo64_then_sub_32 |
| 16288 | 0, // zsub1_then_bsub |
| 16289 | 0, // zsub1_then_dsub |
| 16290 | 0, // zsub1_then_hsub |
| 16291 | 0, // zsub1_then_ssub |
| 16292 | 0, // zsub1_then_zsub |
| 16293 | 0, // zsub1_then_zsub_hi |
| 16294 | 0, // zsub3_then_bsub |
| 16295 | 0, // zsub3_then_dsub |
| 16296 | 0, // zsub3_then_hsub |
| 16297 | 0, // zsub3_then_ssub |
| 16298 | 0, // zsub3_then_zsub |
| 16299 | 0, // zsub3_then_zsub_hi |
| 16300 | 0, // zsub2_then_bsub |
| 16301 | 0, // zsub2_then_dsub |
| 16302 | 0, // zsub2_then_hsub |
| 16303 | 0, // zsub2_then_ssub |
| 16304 | 0, // zsub2_then_zsub |
| 16305 | 0, // zsub2_then_zsub_hi |
| 16306 | 0, // dsub0_dsub1 |
| 16307 | 0, // dsub0_dsub1_dsub2 |
| 16308 | 0, // dsub1_dsub2 |
| 16309 | 0, // dsub1_dsub2_dsub3 |
| 16310 | 0, // dsub2_dsub3 |
| 16311 | 0, // dsub_qsub1_then_dsub |
| 16312 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16313 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16314 | 0, // qsub0_qsub1 |
| 16315 | 0, // qsub0_qsub1_qsub2 |
| 16316 | 0, // qsub1_qsub2 |
| 16317 | 0, // qsub1_qsub2_qsub3 |
| 16318 | 0, // qsub2_qsub3 |
| 16319 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16320 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16321 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16322 | 0, // sub_32_x8sub_1_then_sub_32 |
| 16323 | 0, // x8sub_0_x8sub_1 |
| 16324 | 0, // x8sub_2_x8sub_3 |
| 16325 | 0, // x8sub_4_x8sub_5 |
| 16326 | 0, // x8sub_6_x8sub_7 |
| 16327 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 16328 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 16329 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 16330 | 0, // sub_32_subo64_then_sub_32 |
| 16331 | 0, // dsub_zsub1_then_dsub |
| 16332 | 0, // zsub_zsub1_then_zsub |
| 16333 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16334 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16335 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16336 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16337 | 0, // zsub0_zsub1 |
| 16338 | 0, // zsub0_zsub1_zsub2 |
| 16339 | 0, // zsub1_zsub2 |
| 16340 | 0, // zsub1_zsub2_zsub3 |
| 16341 | 0, // zsub2_zsub3 |
| 16342 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16343 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16344 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16345 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16346 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16347 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16348 | }, |
| 16349 | { // GPR64noip_and_tcGPR64 |
| 16350 | 0, // bsub |
| 16351 | 0, // dsub |
| 16352 | 0, // dsub0 |
| 16353 | 0, // dsub1 |
| 16354 | 0, // dsub2 |
| 16355 | 0, // dsub3 |
| 16356 | 0, // hsub |
| 16357 | 0, // qhisub |
| 16358 | 0, // qsub |
| 16359 | 0, // qsub0 |
| 16360 | 0, // qsub1 |
| 16361 | 0, // qsub2 |
| 16362 | 0, // qsub3 |
| 16363 | 0, // ssub |
| 16364 | 26, // sub_32 -> GPR64noip_and_tcGPR64 |
| 16365 | 0, // sube32 |
| 16366 | 0, // sube64 |
| 16367 | 0, // subo32 |
| 16368 | 0, // subo64 |
| 16369 | 0, // x8sub_0 |
| 16370 | 0, // x8sub_1 |
| 16371 | 0, // x8sub_2 |
| 16372 | 0, // x8sub_3 |
| 16373 | 0, // x8sub_4 |
| 16374 | 0, // x8sub_5 |
| 16375 | 0, // x8sub_6 |
| 16376 | 0, // x8sub_7 |
| 16377 | 0, // zsub |
| 16378 | 0, // zsub0 |
| 16379 | 0, // zsub1 |
| 16380 | 0, // zsub2 |
| 16381 | 0, // zsub3 |
| 16382 | 0, // zsub_hi |
| 16383 | 0, // dsub1_then_bsub |
| 16384 | 0, // dsub1_then_hsub |
| 16385 | 0, // dsub1_then_ssub |
| 16386 | 0, // dsub3_then_bsub |
| 16387 | 0, // dsub3_then_hsub |
| 16388 | 0, // dsub3_then_ssub |
| 16389 | 0, // dsub2_then_bsub |
| 16390 | 0, // dsub2_then_hsub |
| 16391 | 0, // dsub2_then_ssub |
| 16392 | 0, // qsub1_then_bsub |
| 16393 | 0, // qsub1_then_dsub |
| 16394 | 0, // qsub1_then_hsub |
| 16395 | 0, // qsub1_then_ssub |
| 16396 | 0, // qsub3_then_bsub |
| 16397 | 0, // qsub3_then_dsub |
| 16398 | 0, // qsub3_then_hsub |
| 16399 | 0, // qsub3_then_ssub |
| 16400 | 0, // qsub2_then_bsub |
| 16401 | 0, // qsub2_then_dsub |
| 16402 | 0, // qsub2_then_hsub |
| 16403 | 0, // qsub2_then_ssub |
| 16404 | 0, // x8sub_7_then_sub_32 |
| 16405 | 0, // x8sub_6_then_sub_32 |
| 16406 | 0, // x8sub_5_then_sub_32 |
| 16407 | 0, // x8sub_4_then_sub_32 |
| 16408 | 0, // x8sub_3_then_sub_32 |
| 16409 | 0, // x8sub_2_then_sub_32 |
| 16410 | 0, // x8sub_1_then_sub_32 |
| 16411 | 0, // subo64_then_sub_32 |
| 16412 | 0, // zsub1_then_bsub |
| 16413 | 0, // zsub1_then_dsub |
| 16414 | 0, // zsub1_then_hsub |
| 16415 | 0, // zsub1_then_ssub |
| 16416 | 0, // zsub1_then_zsub |
| 16417 | 0, // zsub1_then_zsub_hi |
| 16418 | 0, // zsub3_then_bsub |
| 16419 | 0, // zsub3_then_dsub |
| 16420 | 0, // zsub3_then_hsub |
| 16421 | 0, // zsub3_then_ssub |
| 16422 | 0, // zsub3_then_zsub |
| 16423 | 0, // zsub3_then_zsub_hi |
| 16424 | 0, // zsub2_then_bsub |
| 16425 | 0, // zsub2_then_dsub |
| 16426 | 0, // zsub2_then_hsub |
| 16427 | 0, // zsub2_then_ssub |
| 16428 | 0, // zsub2_then_zsub |
| 16429 | 0, // zsub2_then_zsub_hi |
| 16430 | 0, // dsub0_dsub1 |
| 16431 | 0, // dsub0_dsub1_dsub2 |
| 16432 | 0, // dsub1_dsub2 |
| 16433 | 0, // dsub1_dsub2_dsub3 |
| 16434 | 0, // dsub2_dsub3 |
| 16435 | 0, // dsub_qsub1_then_dsub |
| 16436 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16437 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16438 | 0, // qsub0_qsub1 |
| 16439 | 0, // qsub0_qsub1_qsub2 |
| 16440 | 0, // qsub1_qsub2 |
| 16441 | 0, // qsub1_qsub2_qsub3 |
| 16442 | 0, // qsub2_qsub3 |
| 16443 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16444 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16445 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16446 | 0, // sub_32_x8sub_1_then_sub_32 |
| 16447 | 0, // x8sub_0_x8sub_1 |
| 16448 | 0, // x8sub_2_x8sub_3 |
| 16449 | 0, // x8sub_4_x8sub_5 |
| 16450 | 0, // x8sub_6_x8sub_7 |
| 16451 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 16452 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 16453 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 16454 | 0, // sub_32_subo64_then_sub_32 |
| 16455 | 0, // dsub_zsub1_then_dsub |
| 16456 | 0, // zsub_zsub1_then_zsub |
| 16457 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16458 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16459 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16460 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16461 | 0, // zsub0_zsub1 |
| 16462 | 0, // zsub0_zsub1_zsub2 |
| 16463 | 0, // zsub1_zsub2 |
| 16464 | 0, // zsub1_zsub2_zsub3 |
| 16465 | 0, // zsub2_zsub3 |
| 16466 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16467 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16468 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16469 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16470 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16471 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16472 | }, |
| 16473 | { // FPR64_lo |
| 16474 | 27, // bsub -> FPR64_lo |
| 16475 | 0, // dsub |
| 16476 | 0, // dsub0 |
| 16477 | 0, // dsub1 |
| 16478 | 0, // dsub2 |
| 16479 | 0, // dsub3 |
| 16480 | 27, // hsub -> FPR64_lo |
| 16481 | 0, // qhisub |
| 16482 | 0, // qsub |
| 16483 | 0, // qsub0 |
| 16484 | 0, // qsub1 |
| 16485 | 0, // qsub2 |
| 16486 | 0, // qsub3 |
| 16487 | 27, // ssub -> FPR64_lo |
| 16488 | 0, // sub_32 |
| 16489 | 0, // sube32 |
| 16490 | 0, // sube64 |
| 16491 | 0, // subo32 |
| 16492 | 0, // subo64 |
| 16493 | 0, // x8sub_0 |
| 16494 | 0, // x8sub_1 |
| 16495 | 0, // x8sub_2 |
| 16496 | 0, // x8sub_3 |
| 16497 | 0, // x8sub_4 |
| 16498 | 0, // x8sub_5 |
| 16499 | 0, // x8sub_6 |
| 16500 | 0, // x8sub_7 |
| 16501 | 0, // zsub |
| 16502 | 0, // zsub0 |
| 16503 | 0, // zsub1 |
| 16504 | 0, // zsub2 |
| 16505 | 0, // zsub3 |
| 16506 | 0, // zsub_hi |
| 16507 | 0, // dsub1_then_bsub |
| 16508 | 0, // dsub1_then_hsub |
| 16509 | 0, // dsub1_then_ssub |
| 16510 | 0, // dsub3_then_bsub |
| 16511 | 0, // dsub3_then_hsub |
| 16512 | 0, // dsub3_then_ssub |
| 16513 | 0, // dsub2_then_bsub |
| 16514 | 0, // dsub2_then_hsub |
| 16515 | 0, // dsub2_then_ssub |
| 16516 | 0, // qsub1_then_bsub |
| 16517 | 0, // qsub1_then_dsub |
| 16518 | 0, // qsub1_then_hsub |
| 16519 | 0, // qsub1_then_ssub |
| 16520 | 0, // qsub3_then_bsub |
| 16521 | 0, // qsub3_then_dsub |
| 16522 | 0, // qsub3_then_hsub |
| 16523 | 0, // qsub3_then_ssub |
| 16524 | 0, // qsub2_then_bsub |
| 16525 | 0, // qsub2_then_dsub |
| 16526 | 0, // qsub2_then_hsub |
| 16527 | 0, // qsub2_then_ssub |
| 16528 | 0, // x8sub_7_then_sub_32 |
| 16529 | 0, // x8sub_6_then_sub_32 |
| 16530 | 0, // x8sub_5_then_sub_32 |
| 16531 | 0, // x8sub_4_then_sub_32 |
| 16532 | 0, // x8sub_3_then_sub_32 |
| 16533 | 0, // x8sub_2_then_sub_32 |
| 16534 | 0, // x8sub_1_then_sub_32 |
| 16535 | 0, // subo64_then_sub_32 |
| 16536 | 0, // zsub1_then_bsub |
| 16537 | 0, // zsub1_then_dsub |
| 16538 | 0, // zsub1_then_hsub |
| 16539 | 0, // zsub1_then_ssub |
| 16540 | 0, // zsub1_then_zsub |
| 16541 | 0, // zsub1_then_zsub_hi |
| 16542 | 0, // zsub3_then_bsub |
| 16543 | 0, // zsub3_then_dsub |
| 16544 | 0, // zsub3_then_hsub |
| 16545 | 0, // zsub3_then_ssub |
| 16546 | 0, // zsub3_then_zsub |
| 16547 | 0, // zsub3_then_zsub_hi |
| 16548 | 0, // zsub2_then_bsub |
| 16549 | 0, // zsub2_then_dsub |
| 16550 | 0, // zsub2_then_hsub |
| 16551 | 0, // zsub2_then_ssub |
| 16552 | 0, // zsub2_then_zsub |
| 16553 | 0, // zsub2_then_zsub_hi |
| 16554 | 0, // dsub0_dsub1 |
| 16555 | 0, // dsub0_dsub1_dsub2 |
| 16556 | 0, // dsub1_dsub2 |
| 16557 | 0, // dsub1_dsub2_dsub3 |
| 16558 | 0, // dsub2_dsub3 |
| 16559 | 0, // dsub_qsub1_then_dsub |
| 16560 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16561 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16562 | 0, // qsub0_qsub1 |
| 16563 | 0, // qsub0_qsub1_qsub2 |
| 16564 | 0, // qsub1_qsub2 |
| 16565 | 0, // qsub1_qsub2_qsub3 |
| 16566 | 0, // qsub2_qsub3 |
| 16567 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16568 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16569 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16570 | 0, // sub_32_x8sub_1_then_sub_32 |
| 16571 | 0, // x8sub_0_x8sub_1 |
| 16572 | 0, // x8sub_2_x8sub_3 |
| 16573 | 0, // x8sub_4_x8sub_5 |
| 16574 | 0, // x8sub_6_x8sub_7 |
| 16575 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 16576 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 16577 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 16578 | 0, // sub_32_subo64_then_sub_32 |
| 16579 | 0, // dsub_zsub1_then_dsub |
| 16580 | 0, // zsub_zsub1_then_zsub |
| 16581 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16582 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16583 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16584 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16585 | 0, // zsub0_zsub1 |
| 16586 | 0, // zsub0_zsub1_zsub2 |
| 16587 | 0, // zsub1_zsub2 |
| 16588 | 0, // zsub1_zsub2_zsub3 |
| 16589 | 0, // zsub2_zsub3 |
| 16590 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16591 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16592 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16593 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16594 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16595 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16596 | }, |
| 16597 | { // GPR64x8Class |
| 16598 | 0, // bsub |
| 16599 | 0, // dsub |
| 16600 | 0, // dsub0 |
| 16601 | 0, // dsub1 |
| 16602 | 0, // dsub2 |
| 16603 | 0, // dsub3 |
| 16604 | 0, // hsub |
| 16605 | 0, // qhisub |
| 16606 | 0, // qsub |
| 16607 | 0, // qsub0 |
| 16608 | 0, // qsub1 |
| 16609 | 0, // qsub2 |
| 16610 | 0, // qsub3 |
| 16611 | 0, // ssub |
| 16612 | 28, // sub_32 -> GPR64x8Class |
| 16613 | 0, // sube32 |
| 16614 | 0, // sube64 |
| 16615 | 0, // subo32 |
| 16616 | 0, // subo64 |
| 16617 | 28, // x8sub_0 -> GPR64x8Class |
| 16618 | 28, // x8sub_1 -> GPR64x8Class |
| 16619 | 28, // x8sub_2 -> GPR64x8Class |
| 16620 | 28, // x8sub_3 -> GPR64x8Class |
| 16621 | 28, // x8sub_4 -> GPR64x8Class |
| 16622 | 28, // x8sub_5 -> GPR64x8Class |
| 16623 | 28, // x8sub_6 -> GPR64x8Class |
| 16624 | 28, // x8sub_7 -> GPR64x8Class |
| 16625 | 0, // zsub |
| 16626 | 0, // zsub0 |
| 16627 | 0, // zsub1 |
| 16628 | 0, // zsub2 |
| 16629 | 0, // zsub3 |
| 16630 | 0, // zsub_hi |
| 16631 | 0, // dsub1_then_bsub |
| 16632 | 0, // dsub1_then_hsub |
| 16633 | 0, // dsub1_then_ssub |
| 16634 | 0, // dsub3_then_bsub |
| 16635 | 0, // dsub3_then_hsub |
| 16636 | 0, // dsub3_then_ssub |
| 16637 | 0, // dsub2_then_bsub |
| 16638 | 0, // dsub2_then_hsub |
| 16639 | 0, // dsub2_then_ssub |
| 16640 | 0, // qsub1_then_bsub |
| 16641 | 0, // qsub1_then_dsub |
| 16642 | 0, // qsub1_then_hsub |
| 16643 | 0, // qsub1_then_ssub |
| 16644 | 0, // qsub3_then_bsub |
| 16645 | 0, // qsub3_then_dsub |
| 16646 | 0, // qsub3_then_hsub |
| 16647 | 0, // qsub3_then_ssub |
| 16648 | 0, // qsub2_then_bsub |
| 16649 | 0, // qsub2_then_dsub |
| 16650 | 0, // qsub2_then_hsub |
| 16651 | 0, // qsub2_then_ssub |
| 16652 | 28, // x8sub_7_then_sub_32 -> GPR64x8Class |
| 16653 | 28, // x8sub_6_then_sub_32 -> GPR64x8Class |
| 16654 | 28, // x8sub_5_then_sub_32 -> GPR64x8Class |
| 16655 | 28, // x8sub_4_then_sub_32 -> GPR64x8Class |
| 16656 | 28, // x8sub_3_then_sub_32 -> GPR64x8Class |
| 16657 | 28, // x8sub_2_then_sub_32 -> GPR64x8Class |
| 16658 | 28, // x8sub_1_then_sub_32 -> GPR64x8Class |
| 16659 | 0, // subo64_then_sub_32 |
| 16660 | 0, // zsub1_then_bsub |
| 16661 | 0, // zsub1_then_dsub |
| 16662 | 0, // zsub1_then_hsub |
| 16663 | 0, // zsub1_then_ssub |
| 16664 | 0, // zsub1_then_zsub |
| 16665 | 0, // zsub1_then_zsub_hi |
| 16666 | 0, // zsub3_then_bsub |
| 16667 | 0, // zsub3_then_dsub |
| 16668 | 0, // zsub3_then_hsub |
| 16669 | 0, // zsub3_then_ssub |
| 16670 | 0, // zsub3_then_zsub |
| 16671 | 0, // zsub3_then_zsub_hi |
| 16672 | 0, // zsub2_then_bsub |
| 16673 | 0, // zsub2_then_dsub |
| 16674 | 0, // zsub2_then_hsub |
| 16675 | 0, // zsub2_then_ssub |
| 16676 | 0, // zsub2_then_zsub |
| 16677 | 0, // zsub2_then_zsub_hi |
| 16678 | 0, // dsub0_dsub1 |
| 16679 | 0, // dsub0_dsub1_dsub2 |
| 16680 | 0, // dsub1_dsub2 |
| 16681 | 0, // dsub1_dsub2_dsub3 |
| 16682 | 0, // dsub2_dsub3 |
| 16683 | 0, // dsub_qsub1_then_dsub |
| 16684 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16685 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16686 | 0, // qsub0_qsub1 |
| 16687 | 0, // qsub0_qsub1_qsub2 |
| 16688 | 0, // qsub1_qsub2 |
| 16689 | 0, // qsub1_qsub2_qsub3 |
| 16690 | 0, // qsub2_qsub3 |
| 16691 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16692 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16693 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16694 | 28, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class |
| 16695 | 28, // x8sub_0_x8sub_1 -> GPR64x8Class |
| 16696 | 28, // x8sub_2_x8sub_3 -> GPR64x8Class |
| 16697 | 28, // x8sub_4_x8sub_5 -> GPR64x8Class |
| 16698 | 28, // x8sub_6_x8sub_7 -> GPR64x8Class |
| 16699 | 28, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class |
| 16700 | 28, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class |
| 16701 | 28, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class |
| 16702 | 0, // sub_32_subo64_then_sub_32 |
| 16703 | 0, // dsub_zsub1_then_dsub |
| 16704 | 0, // zsub_zsub1_then_zsub |
| 16705 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16706 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16707 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16708 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16709 | 0, // zsub0_zsub1 |
| 16710 | 0, // zsub0_zsub1_zsub2 |
| 16711 | 0, // zsub1_zsub2 |
| 16712 | 0, // zsub1_zsub2_zsub3 |
| 16713 | 0, // zsub2_zsub3 |
| 16714 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16715 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16716 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16717 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16718 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16719 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16720 | }, |
| 16721 | { // GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16722 | 0, // bsub |
| 16723 | 0, // dsub |
| 16724 | 0, // dsub0 |
| 16725 | 0, // dsub1 |
| 16726 | 0, // dsub2 |
| 16727 | 0, // dsub3 |
| 16728 | 0, // hsub |
| 16729 | 0, // qhisub |
| 16730 | 0, // qsub |
| 16731 | 0, // qsub0 |
| 16732 | 0, // qsub1 |
| 16733 | 0, // qsub2 |
| 16734 | 0, // qsub3 |
| 16735 | 0, // ssub |
| 16736 | 29, // sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16737 | 0, // sube32 |
| 16738 | 0, // sube64 |
| 16739 | 0, // subo32 |
| 16740 | 0, // subo64 |
| 16741 | 29, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16742 | 29, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16743 | 29, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16744 | 29, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16745 | 29, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16746 | 29, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16747 | 29, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16748 | 29, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16749 | 0, // zsub |
| 16750 | 0, // zsub0 |
| 16751 | 0, // zsub1 |
| 16752 | 0, // zsub2 |
| 16753 | 0, // zsub3 |
| 16754 | 0, // zsub_hi |
| 16755 | 0, // dsub1_then_bsub |
| 16756 | 0, // dsub1_then_hsub |
| 16757 | 0, // dsub1_then_ssub |
| 16758 | 0, // dsub3_then_bsub |
| 16759 | 0, // dsub3_then_hsub |
| 16760 | 0, // dsub3_then_ssub |
| 16761 | 0, // dsub2_then_bsub |
| 16762 | 0, // dsub2_then_hsub |
| 16763 | 0, // dsub2_then_ssub |
| 16764 | 0, // qsub1_then_bsub |
| 16765 | 0, // qsub1_then_dsub |
| 16766 | 0, // qsub1_then_hsub |
| 16767 | 0, // qsub1_then_ssub |
| 16768 | 0, // qsub3_then_bsub |
| 16769 | 0, // qsub3_then_dsub |
| 16770 | 0, // qsub3_then_hsub |
| 16771 | 0, // qsub3_then_ssub |
| 16772 | 0, // qsub2_then_bsub |
| 16773 | 0, // qsub2_then_dsub |
| 16774 | 0, // qsub2_then_hsub |
| 16775 | 0, // qsub2_then_ssub |
| 16776 | 29, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16777 | 29, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16778 | 29, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16779 | 29, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16780 | 29, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16781 | 29, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16782 | 29, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16783 | 0, // subo64_then_sub_32 |
| 16784 | 0, // zsub1_then_bsub |
| 16785 | 0, // zsub1_then_dsub |
| 16786 | 0, // zsub1_then_hsub |
| 16787 | 0, // zsub1_then_ssub |
| 16788 | 0, // zsub1_then_zsub |
| 16789 | 0, // zsub1_then_zsub_hi |
| 16790 | 0, // zsub3_then_bsub |
| 16791 | 0, // zsub3_then_dsub |
| 16792 | 0, // zsub3_then_hsub |
| 16793 | 0, // zsub3_then_ssub |
| 16794 | 0, // zsub3_then_zsub |
| 16795 | 0, // zsub3_then_zsub_hi |
| 16796 | 0, // zsub2_then_bsub |
| 16797 | 0, // zsub2_then_dsub |
| 16798 | 0, // zsub2_then_hsub |
| 16799 | 0, // zsub2_then_ssub |
| 16800 | 0, // zsub2_then_zsub |
| 16801 | 0, // zsub2_then_zsub_hi |
| 16802 | 0, // dsub0_dsub1 |
| 16803 | 0, // dsub0_dsub1_dsub2 |
| 16804 | 0, // dsub1_dsub2 |
| 16805 | 0, // dsub1_dsub2_dsub3 |
| 16806 | 0, // dsub2_dsub3 |
| 16807 | 0, // dsub_qsub1_then_dsub |
| 16808 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16809 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16810 | 0, // qsub0_qsub1 |
| 16811 | 0, // qsub0_qsub1_qsub2 |
| 16812 | 0, // qsub1_qsub2 |
| 16813 | 0, // qsub1_qsub2_qsub3 |
| 16814 | 0, // qsub2_qsub3 |
| 16815 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16816 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16817 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16818 | 29, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16819 | 29, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16820 | 29, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16821 | 29, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16822 | 29, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16823 | 29, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16824 | 29, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16825 | 29, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 16826 | 0, // sub_32_subo64_then_sub_32 |
| 16827 | 0, // dsub_zsub1_then_dsub |
| 16828 | 0, // zsub_zsub1_then_zsub |
| 16829 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16830 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16831 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16832 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16833 | 0, // zsub0_zsub1 |
| 16834 | 0, // zsub0_zsub1_zsub2 |
| 16835 | 0, // zsub1_zsub2 |
| 16836 | 0, // zsub1_zsub2_zsub3 |
| 16837 | 0, // zsub2_zsub3 |
| 16838 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16839 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16840 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16841 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16842 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16843 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16844 | }, |
| 16845 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16846 | 0, // bsub |
| 16847 | 0, // dsub |
| 16848 | 0, // dsub0 |
| 16849 | 0, // dsub1 |
| 16850 | 0, // dsub2 |
| 16851 | 0, // dsub3 |
| 16852 | 0, // hsub |
| 16853 | 0, // qhisub |
| 16854 | 0, // qsub |
| 16855 | 0, // qsub0 |
| 16856 | 0, // qsub1 |
| 16857 | 0, // qsub2 |
| 16858 | 0, // qsub3 |
| 16859 | 0, // ssub |
| 16860 | 30, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16861 | 0, // sube32 |
| 16862 | 0, // sube64 |
| 16863 | 0, // subo32 |
| 16864 | 0, // subo64 |
| 16865 | 30, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16866 | 30, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16867 | 30, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16868 | 30, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16869 | 30, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16870 | 30, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16871 | 30, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16872 | 30, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16873 | 0, // zsub |
| 16874 | 0, // zsub0 |
| 16875 | 0, // zsub1 |
| 16876 | 0, // zsub2 |
| 16877 | 0, // zsub3 |
| 16878 | 0, // zsub_hi |
| 16879 | 0, // dsub1_then_bsub |
| 16880 | 0, // dsub1_then_hsub |
| 16881 | 0, // dsub1_then_ssub |
| 16882 | 0, // dsub3_then_bsub |
| 16883 | 0, // dsub3_then_hsub |
| 16884 | 0, // dsub3_then_ssub |
| 16885 | 0, // dsub2_then_bsub |
| 16886 | 0, // dsub2_then_hsub |
| 16887 | 0, // dsub2_then_ssub |
| 16888 | 0, // qsub1_then_bsub |
| 16889 | 0, // qsub1_then_dsub |
| 16890 | 0, // qsub1_then_hsub |
| 16891 | 0, // qsub1_then_ssub |
| 16892 | 0, // qsub3_then_bsub |
| 16893 | 0, // qsub3_then_dsub |
| 16894 | 0, // qsub3_then_hsub |
| 16895 | 0, // qsub3_then_ssub |
| 16896 | 0, // qsub2_then_bsub |
| 16897 | 0, // qsub2_then_dsub |
| 16898 | 0, // qsub2_then_hsub |
| 16899 | 0, // qsub2_then_ssub |
| 16900 | 30, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16901 | 30, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16902 | 30, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16903 | 30, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16904 | 30, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16905 | 30, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16906 | 30, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16907 | 0, // subo64_then_sub_32 |
| 16908 | 0, // zsub1_then_bsub |
| 16909 | 0, // zsub1_then_dsub |
| 16910 | 0, // zsub1_then_hsub |
| 16911 | 0, // zsub1_then_ssub |
| 16912 | 0, // zsub1_then_zsub |
| 16913 | 0, // zsub1_then_zsub_hi |
| 16914 | 0, // zsub3_then_bsub |
| 16915 | 0, // zsub3_then_dsub |
| 16916 | 0, // zsub3_then_hsub |
| 16917 | 0, // zsub3_then_ssub |
| 16918 | 0, // zsub3_then_zsub |
| 16919 | 0, // zsub3_then_zsub_hi |
| 16920 | 0, // zsub2_then_bsub |
| 16921 | 0, // zsub2_then_dsub |
| 16922 | 0, // zsub2_then_hsub |
| 16923 | 0, // zsub2_then_ssub |
| 16924 | 0, // zsub2_then_zsub |
| 16925 | 0, // zsub2_then_zsub_hi |
| 16926 | 0, // dsub0_dsub1 |
| 16927 | 0, // dsub0_dsub1_dsub2 |
| 16928 | 0, // dsub1_dsub2 |
| 16929 | 0, // dsub1_dsub2_dsub3 |
| 16930 | 0, // dsub2_dsub3 |
| 16931 | 0, // dsub_qsub1_then_dsub |
| 16932 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16933 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 16934 | 0, // qsub0_qsub1 |
| 16935 | 0, // qsub0_qsub1_qsub2 |
| 16936 | 0, // qsub1_qsub2 |
| 16937 | 0, // qsub1_qsub2_qsub3 |
| 16938 | 0, // qsub2_qsub3 |
| 16939 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 16940 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 16941 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 16942 | 30, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16943 | 30, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16944 | 30, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16945 | 30, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16946 | 30, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16947 | 30, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16948 | 30, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16949 | 30, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 16950 | 0, // sub_32_subo64_then_sub_32 |
| 16951 | 0, // dsub_zsub1_then_dsub |
| 16952 | 0, // zsub_zsub1_then_zsub |
| 16953 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16954 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 16955 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16956 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 16957 | 0, // zsub0_zsub1 |
| 16958 | 0, // zsub0_zsub1_zsub2 |
| 16959 | 0, // zsub1_zsub2 |
| 16960 | 0, // zsub1_zsub2_zsub3 |
| 16961 | 0, // zsub2_zsub3 |
| 16962 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 16963 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 16964 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 16965 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 16966 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 16967 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 16968 | }, |
| 16969 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16970 | 0, // bsub |
| 16971 | 0, // dsub |
| 16972 | 0, // dsub0 |
| 16973 | 0, // dsub1 |
| 16974 | 0, // dsub2 |
| 16975 | 0, // dsub3 |
| 16976 | 0, // hsub |
| 16977 | 0, // qhisub |
| 16978 | 0, // qsub |
| 16979 | 0, // qsub0 |
| 16980 | 0, // qsub1 |
| 16981 | 0, // qsub2 |
| 16982 | 0, // qsub3 |
| 16983 | 0, // ssub |
| 16984 | 31, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16985 | 0, // sube32 |
| 16986 | 0, // sube64 |
| 16987 | 0, // subo32 |
| 16988 | 0, // subo64 |
| 16989 | 31, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16990 | 31, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16991 | 31, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16992 | 31, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16993 | 31, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16994 | 31, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16995 | 31, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16996 | 31, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 16997 | 0, // zsub |
| 16998 | 0, // zsub0 |
| 16999 | 0, // zsub1 |
| 17000 | 0, // zsub2 |
| 17001 | 0, // zsub3 |
| 17002 | 0, // zsub_hi |
| 17003 | 0, // dsub1_then_bsub |
| 17004 | 0, // dsub1_then_hsub |
| 17005 | 0, // dsub1_then_ssub |
| 17006 | 0, // dsub3_then_bsub |
| 17007 | 0, // dsub3_then_hsub |
| 17008 | 0, // dsub3_then_ssub |
| 17009 | 0, // dsub2_then_bsub |
| 17010 | 0, // dsub2_then_hsub |
| 17011 | 0, // dsub2_then_ssub |
| 17012 | 0, // qsub1_then_bsub |
| 17013 | 0, // qsub1_then_dsub |
| 17014 | 0, // qsub1_then_hsub |
| 17015 | 0, // qsub1_then_ssub |
| 17016 | 0, // qsub3_then_bsub |
| 17017 | 0, // qsub3_then_dsub |
| 17018 | 0, // qsub3_then_hsub |
| 17019 | 0, // qsub3_then_ssub |
| 17020 | 0, // qsub2_then_bsub |
| 17021 | 0, // qsub2_then_dsub |
| 17022 | 0, // qsub2_then_hsub |
| 17023 | 0, // qsub2_then_ssub |
| 17024 | 31, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17025 | 31, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17026 | 31, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17027 | 31, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17028 | 31, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17029 | 31, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17030 | 31, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17031 | 0, // subo64_then_sub_32 |
| 17032 | 0, // zsub1_then_bsub |
| 17033 | 0, // zsub1_then_dsub |
| 17034 | 0, // zsub1_then_hsub |
| 17035 | 0, // zsub1_then_ssub |
| 17036 | 0, // zsub1_then_zsub |
| 17037 | 0, // zsub1_then_zsub_hi |
| 17038 | 0, // zsub3_then_bsub |
| 17039 | 0, // zsub3_then_dsub |
| 17040 | 0, // zsub3_then_hsub |
| 17041 | 0, // zsub3_then_ssub |
| 17042 | 0, // zsub3_then_zsub |
| 17043 | 0, // zsub3_then_zsub_hi |
| 17044 | 0, // zsub2_then_bsub |
| 17045 | 0, // zsub2_then_dsub |
| 17046 | 0, // zsub2_then_hsub |
| 17047 | 0, // zsub2_then_ssub |
| 17048 | 0, // zsub2_then_zsub |
| 17049 | 0, // zsub2_then_zsub_hi |
| 17050 | 0, // dsub0_dsub1 |
| 17051 | 0, // dsub0_dsub1_dsub2 |
| 17052 | 0, // dsub1_dsub2 |
| 17053 | 0, // dsub1_dsub2_dsub3 |
| 17054 | 0, // dsub2_dsub3 |
| 17055 | 0, // dsub_qsub1_then_dsub |
| 17056 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17057 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17058 | 0, // qsub0_qsub1 |
| 17059 | 0, // qsub0_qsub1_qsub2 |
| 17060 | 0, // qsub1_qsub2 |
| 17061 | 0, // qsub1_qsub2_qsub3 |
| 17062 | 0, // qsub2_qsub3 |
| 17063 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17064 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17065 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17066 | 31, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17067 | 31, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17068 | 31, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17069 | 31, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17070 | 31, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17071 | 31, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17072 | 31, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17073 | 31, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17074 | 0, // sub_32_subo64_then_sub_32 |
| 17075 | 0, // dsub_zsub1_then_dsub |
| 17076 | 0, // zsub_zsub1_then_zsub |
| 17077 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17078 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17079 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17080 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17081 | 0, // zsub0_zsub1 |
| 17082 | 0, // zsub0_zsub1_zsub2 |
| 17083 | 0, // zsub1_zsub2 |
| 17084 | 0, // zsub1_zsub2_zsub3 |
| 17085 | 0, // zsub2_zsub3 |
| 17086 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17087 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17088 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17089 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17090 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17091 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17092 | }, |
| 17093 | { // GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17094 | 0, // bsub |
| 17095 | 0, // dsub |
| 17096 | 0, // dsub0 |
| 17097 | 0, // dsub1 |
| 17098 | 0, // dsub2 |
| 17099 | 0, // dsub3 |
| 17100 | 0, // hsub |
| 17101 | 0, // qhisub |
| 17102 | 0, // qsub |
| 17103 | 0, // qsub0 |
| 17104 | 0, // qsub1 |
| 17105 | 0, // qsub2 |
| 17106 | 0, // qsub3 |
| 17107 | 0, // ssub |
| 17108 | 32, // sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17109 | 0, // sube32 |
| 17110 | 0, // sube64 |
| 17111 | 0, // subo32 |
| 17112 | 0, // subo64 |
| 17113 | 32, // x8sub_0 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17114 | 32, // x8sub_1 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17115 | 32, // x8sub_2 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17116 | 32, // x8sub_3 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17117 | 32, // x8sub_4 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17118 | 32, // x8sub_5 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17119 | 32, // x8sub_6 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17120 | 32, // x8sub_7 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17121 | 0, // zsub |
| 17122 | 0, // zsub0 |
| 17123 | 0, // zsub1 |
| 17124 | 0, // zsub2 |
| 17125 | 0, // zsub3 |
| 17126 | 0, // zsub_hi |
| 17127 | 0, // dsub1_then_bsub |
| 17128 | 0, // dsub1_then_hsub |
| 17129 | 0, // dsub1_then_ssub |
| 17130 | 0, // dsub3_then_bsub |
| 17131 | 0, // dsub3_then_hsub |
| 17132 | 0, // dsub3_then_ssub |
| 17133 | 0, // dsub2_then_bsub |
| 17134 | 0, // dsub2_then_hsub |
| 17135 | 0, // dsub2_then_ssub |
| 17136 | 0, // qsub1_then_bsub |
| 17137 | 0, // qsub1_then_dsub |
| 17138 | 0, // qsub1_then_hsub |
| 17139 | 0, // qsub1_then_ssub |
| 17140 | 0, // qsub3_then_bsub |
| 17141 | 0, // qsub3_then_dsub |
| 17142 | 0, // qsub3_then_hsub |
| 17143 | 0, // qsub3_then_ssub |
| 17144 | 0, // qsub2_then_bsub |
| 17145 | 0, // qsub2_then_dsub |
| 17146 | 0, // qsub2_then_hsub |
| 17147 | 0, // qsub2_then_ssub |
| 17148 | 32, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17149 | 32, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17150 | 32, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17151 | 32, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17152 | 32, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17153 | 32, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17154 | 32, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17155 | 0, // subo64_then_sub_32 |
| 17156 | 0, // zsub1_then_bsub |
| 17157 | 0, // zsub1_then_dsub |
| 17158 | 0, // zsub1_then_hsub |
| 17159 | 0, // zsub1_then_ssub |
| 17160 | 0, // zsub1_then_zsub |
| 17161 | 0, // zsub1_then_zsub_hi |
| 17162 | 0, // zsub3_then_bsub |
| 17163 | 0, // zsub3_then_dsub |
| 17164 | 0, // zsub3_then_hsub |
| 17165 | 0, // zsub3_then_ssub |
| 17166 | 0, // zsub3_then_zsub |
| 17167 | 0, // zsub3_then_zsub_hi |
| 17168 | 0, // zsub2_then_bsub |
| 17169 | 0, // zsub2_then_dsub |
| 17170 | 0, // zsub2_then_hsub |
| 17171 | 0, // zsub2_then_ssub |
| 17172 | 0, // zsub2_then_zsub |
| 17173 | 0, // zsub2_then_zsub_hi |
| 17174 | 0, // dsub0_dsub1 |
| 17175 | 0, // dsub0_dsub1_dsub2 |
| 17176 | 0, // dsub1_dsub2 |
| 17177 | 0, // dsub1_dsub2_dsub3 |
| 17178 | 0, // dsub2_dsub3 |
| 17179 | 0, // dsub_qsub1_then_dsub |
| 17180 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17181 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17182 | 0, // qsub0_qsub1 |
| 17183 | 0, // qsub0_qsub1_qsub2 |
| 17184 | 0, // qsub1_qsub2 |
| 17185 | 0, // qsub1_qsub2_qsub3 |
| 17186 | 0, // qsub2_qsub3 |
| 17187 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17188 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17189 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17190 | 32, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17191 | 32, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17192 | 32, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17193 | 32, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17194 | 32, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17195 | 32, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17196 | 32, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17197 | 32, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17198 | 0, // sub_32_subo64_then_sub_32 |
| 17199 | 0, // dsub_zsub1_then_dsub |
| 17200 | 0, // zsub_zsub1_then_zsub |
| 17201 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17202 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17203 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17204 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17205 | 0, // zsub0_zsub1 |
| 17206 | 0, // zsub0_zsub1_zsub2 |
| 17207 | 0, // zsub1_zsub2 |
| 17208 | 0, // zsub1_zsub2_zsub3 |
| 17209 | 0, // zsub2_zsub3 |
| 17210 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17211 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17212 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17213 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17214 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17215 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17216 | }, |
| 17217 | { // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17218 | 0, // bsub |
| 17219 | 0, // dsub |
| 17220 | 0, // dsub0 |
| 17221 | 0, // dsub1 |
| 17222 | 0, // dsub2 |
| 17223 | 0, // dsub3 |
| 17224 | 0, // hsub |
| 17225 | 0, // qhisub |
| 17226 | 0, // qsub |
| 17227 | 0, // qsub0 |
| 17228 | 0, // qsub1 |
| 17229 | 0, // qsub2 |
| 17230 | 0, // qsub3 |
| 17231 | 0, // ssub |
| 17232 | 33, // sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17233 | 0, // sube32 |
| 17234 | 0, // sube64 |
| 17235 | 0, // subo32 |
| 17236 | 0, // subo64 |
| 17237 | 33, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17238 | 33, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17239 | 33, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17240 | 33, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17241 | 33, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17242 | 33, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17243 | 33, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17244 | 33, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17245 | 0, // zsub |
| 17246 | 0, // zsub0 |
| 17247 | 0, // zsub1 |
| 17248 | 0, // zsub2 |
| 17249 | 0, // zsub3 |
| 17250 | 0, // zsub_hi |
| 17251 | 0, // dsub1_then_bsub |
| 17252 | 0, // dsub1_then_hsub |
| 17253 | 0, // dsub1_then_ssub |
| 17254 | 0, // dsub3_then_bsub |
| 17255 | 0, // dsub3_then_hsub |
| 17256 | 0, // dsub3_then_ssub |
| 17257 | 0, // dsub2_then_bsub |
| 17258 | 0, // dsub2_then_hsub |
| 17259 | 0, // dsub2_then_ssub |
| 17260 | 0, // qsub1_then_bsub |
| 17261 | 0, // qsub1_then_dsub |
| 17262 | 0, // qsub1_then_hsub |
| 17263 | 0, // qsub1_then_ssub |
| 17264 | 0, // qsub3_then_bsub |
| 17265 | 0, // qsub3_then_dsub |
| 17266 | 0, // qsub3_then_hsub |
| 17267 | 0, // qsub3_then_ssub |
| 17268 | 0, // qsub2_then_bsub |
| 17269 | 0, // qsub2_then_dsub |
| 17270 | 0, // qsub2_then_hsub |
| 17271 | 0, // qsub2_then_ssub |
| 17272 | 33, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17273 | 33, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17274 | 33, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17275 | 33, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17276 | 33, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17277 | 33, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17278 | 33, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17279 | 0, // subo64_then_sub_32 |
| 17280 | 0, // zsub1_then_bsub |
| 17281 | 0, // zsub1_then_dsub |
| 17282 | 0, // zsub1_then_hsub |
| 17283 | 0, // zsub1_then_ssub |
| 17284 | 0, // zsub1_then_zsub |
| 17285 | 0, // zsub1_then_zsub_hi |
| 17286 | 0, // zsub3_then_bsub |
| 17287 | 0, // zsub3_then_dsub |
| 17288 | 0, // zsub3_then_hsub |
| 17289 | 0, // zsub3_then_ssub |
| 17290 | 0, // zsub3_then_zsub |
| 17291 | 0, // zsub3_then_zsub_hi |
| 17292 | 0, // zsub2_then_bsub |
| 17293 | 0, // zsub2_then_dsub |
| 17294 | 0, // zsub2_then_hsub |
| 17295 | 0, // zsub2_then_ssub |
| 17296 | 0, // zsub2_then_zsub |
| 17297 | 0, // zsub2_then_zsub_hi |
| 17298 | 0, // dsub0_dsub1 |
| 17299 | 0, // dsub0_dsub1_dsub2 |
| 17300 | 0, // dsub1_dsub2 |
| 17301 | 0, // dsub1_dsub2_dsub3 |
| 17302 | 0, // dsub2_dsub3 |
| 17303 | 0, // dsub_qsub1_then_dsub |
| 17304 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17305 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17306 | 0, // qsub0_qsub1 |
| 17307 | 0, // qsub0_qsub1_qsub2 |
| 17308 | 0, // qsub1_qsub2 |
| 17309 | 0, // qsub1_qsub2_qsub3 |
| 17310 | 0, // qsub2_qsub3 |
| 17311 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17312 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17313 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17314 | 33, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17315 | 33, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17316 | 33, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17317 | 33, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17318 | 33, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17319 | 33, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17320 | 33, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17321 | 33, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 17322 | 0, // sub_32_subo64_then_sub_32 |
| 17323 | 0, // dsub_zsub1_then_dsub |
| 17324 | 0, // zsub_zsub1_then_zsub |
| 17325 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17326 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17327 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17328 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17329 | 0, // zsub0_zsub1 |
| 17330 | 0, // zsub0_zsub1_zsub2 |
| 17331 | 0, // zsub1_zsub2 |
| 17332 | 0, // zsub1_zsub2_zsub3 |
| 17333 | 0, // zsub2_zsub3 |
| 17334 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17335 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17336 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17337 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17338 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17339 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17340 | }, |
| 17341 | { // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17342 | 0, // bsub |
| 17343 | 0, // dsub |
| 17344 | 0, // dsub0 |
| 17345 | 0, // dsub1 |
| 17346 | 0, // dsub2 |
| 17347 | 0, // dsub3 |
| 17348 | 0, // hsub |
| 17349 | 0, // qhisub |
| 17350 | 0, // qsub |
| 17351 | 0, // qsub0 |
| 17352 | 0, // qsub1 |
| 17353 | 0, // qsub2 |
| 17354 | 0, // qsub3 |
| 17355 | 0, // ssub |
| 17356 | 34, // sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17357 | 0, // sube32 |
| 17358 | 0, // sube64 |
| 17359 | 0, // subo32 |
| 17360 | 0, // subo64 |
| 17361 | 34, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17362 | 34, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17363 | 34, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17364 | 34, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17365 | 34, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17366 | 34, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17367 | 34, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17368 | 34, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17369 | 0, // zsub |
| 17370 | 0, // zsub0 |
| 17371 | 0, // zsub1 |
| 17372 | 0, // zsub2 |
| 17373 | 0, // zsub3 |
| 17374 | 0, // zsub_hi |
| 17375 | 0, // dsub1_then_bsub |
| 17376 | 0, // dsub1_then_hsub |
| 17377 | 0, // dsub1_then_ssub |
| 17378 | 0, // dsub3_then_bsub |
| 17379 | 0, // dsub3_then_hsub |
| 17380 | 0, // dsub3_then_ssub |
| 17381 | 0, // dsub2_then_bsub |
| 17382 | 0, // dsub2_then_hsub |
| 17383 | 0, // dsub2_then_ssub |
| 17384 | 0, // qsub1_then_bsub |
| 17385 | 0, // qsub1_then_dsub |
| 17386 | 0, // qsub1_then_hsub |
| 17387 | 0, // qsub1_then_ssub |
| 17388 | 0, // qsub3_then_bsub |
| 17389 | 0, // qsub3_then_dsub |
| 17390 | 0, // qsub3_then_hsub |
| 17391 | 0, // qsub3_then_ssub |
| 17392 | 0, // qsub2_then_bsub |
| 17393 | 0, // qsub2_then_dsub |
| 17394 | 0, // qsub2_then_hsub |
| 17395 | 0, // qsub2_then_ssub |
| 17396 | 34, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17397 | 34, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17398 | 34, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17399 | 34, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17400 | 34, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17401 | 34, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17402 | 34, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17403 | 0, // subo64_then_sub_32 |
| 17404 | 0, // zsub1_then_bsub |
| 17405 | 0, // zsub1_then_dsub |
| 17406 | 0, // zsub1_then_hsub |
| 17407 | 0, // zsub1_then_ssub |
| 17408 | 0, // zsub1_then_zsub |
| 17409 | 0, // zsub1_then_zsub_hi |
| 17410 | 0, // zsub3_then_bsub |
| 17411 | 0, // zsub3_then_dsub |
| 17412 | 0, // zsub3_then_hsub |
| 17413 | 0, // zsub3_then_ssub |
| 17414 | 0, // zsub3_then_zsub |
| 17415 | 0, // zsub3_then_zsub_hi |
| 17416 | 0, // zsub2_then_bsub |
| 17417 | 0, // zsub2_then_dsub |
| 17418 | 0, // zsub2_then_hsub |
| 17419 | 0, // zsub2_then_ssub |
| 17420 | 0, // zsub2_then_zsub |
| 17421 | 0, // zsub2_then_zsub_hi |
| 17422 | 0, // dsub0_dsub1 |
| 17423 | 0, // dsub0_dsub1_dsub2 |
| 17424 | 0, // dsub1_dsub2 |
| 17425 | 0, // dsub1_dsub2_dsub3 |
| 17426 | 0, // dsub2_dsub3 |
| 17427 | 0, // dsub_qsub1_then_dsub |
| 17428 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17429 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17430 | 0, // qsub0_qsub1 |
| 17431 | 0, // qsub0_qsub1_qsub2 |
| 17432 | 0, // qsub1_qsub2 |
| 17433 | 0, // qsub1_qsub2_qsub3 |
| 17434 | 0, // qsub2_qsub3 |
| 17435 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17436 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17437 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17438 | 34, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17439 | 34, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17440 | 34, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17441 | 34, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17442 | 34, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17443 | 34, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17444 | 34, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17445 | 34, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17446 | 0, // sub_32_subo64_then_sub_32 |
| 17447 | 0, // dsub_zsub1_then_dsub |
| 17448 | 0, // zsub_zsub1_then_zsub |
| 17449 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17450 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17451 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17452 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17453 | 0, // zsub0_zsub1 |
| 17454 | 0, // zsub0_zsub1_zsub2 |
| 17455 | 0, // zsub1_zsub2 |
| 17456 | 0, // zsub1_zsub2_zsub3 |
| 17457 | 0, // zsub2_zsub3 |
| 17458 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17459 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17460 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17461 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17462 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17463 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17464 | }, |
| 17465 | { // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17466 | 0, // bsub |
| 17467 | 0, // dsub |
| 17468 | 0, // dsub0 |
| 17469 | 0, // dsub1 |
| 17470 | 0, // dsub2 |
| 17471 | 0, // dsub3 |
| 17472 | 0, // hsub |
| 17473 | 0, // qhisub |
| 17474 | 0, // qsub |
| 17475 | 0, // qsub0 |
| 17476 | 0, // qsub1 |
| 17477 | 0, // qsub2 |
| 17478 | 0, // qsub3 |
| 17479 | 0, // ssub |
| 17480 | 35, // sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17481 | 0, // sube32 |
| 17482 | 0, // sube64 |
| 17483 | 0, // subo32 |
| 17484 | 0, // subo64 |
| 17485 | 35, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17486 | 35, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17487 | 35, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17488 | 35, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17489 | 35, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17490 | 35, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17491 | 35, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17492 | 35, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17493 | 0, // zsub |
| 17494 | 0, // zsub0 |
| 17495 | 0, // zsub1 |
| 17496 | 0, // zsub2 |
| 17497 | 0, // zsub3 |
| 17498 | 0, // zsub_hi |
| 17499 | 0, // dsub1_then_bsub |
| 17500 | 0, // dsub1_then_hsub |
| 17501 | 0, // dsub1_then_ssub |
| 17502 | 0, // dsub3_then_bsub |
| 17503 | 0, // dsub3_then_hsub |
| 17504 | 0, // dsub3_then_ssub |
| 17505 | 0, // dsub2_then_bsub |
| 17506 | 0, // dsub2_then_hsub |
| 17507 | 0, // dsub2_then_ssub |
| 17508 | 0, // qsub1_then_bsub |
| 17509 | 0, // qsub1_then_dsub |
| 17510 | 0, // qsub1_then_hsub |
| 17511 | 0, // qsub1_then_ssub |
| 17512 | 0, // qsub3_then_bsub |
| 17513 | 0, // qsub3_then_dsub |
| 17514 | 0, // qsub3_then_hsub |
| 17515 | 0, // qsub3_then_ssub |
| 17516 | 0, // qsub2_then_bsub |
| 17517 | 0, // qsub2_then_dsub |
| 17518 | 0, // qsub2_then_hsub |
| 17519 | 0, // qsub2_then_ssub |
| 17520 | 35, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17521 | 35, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17522 | 35, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17523 | 35, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17524 | 35, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17525 | 35, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17526 | 35, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17527 | 0, // subo64_then_sub_32 |
| 17528 | 0, // zsub1_then_bsub |
| 17529 | 0, // zsub1_then_dsub |
| 17530 | 0, // zsub1_then_hsub |
| 17531 | 0, // zsub1_then_ssub |
| 17532 | 0, // zsub1_then_zsub |
| 17533 | 0, // zsub1_then_zsub_hi |
| 17534 | 0, // zsub3_then_bsub |
| 17535 | 0, // zsub3_then_dsub |
| 17536 | 0, // zsub3_then_hsub |
| 17537 | 0, // zsub3_then_ssub |
| 17538 | 0, // zsub3_then_zsub |
| 17539 | 0, // zsub3_then_zsub_hi |
| 17540 | 0, // zsub2_then_bsub |
| 17541 | 0, // zsub2_then_dsub |
| 17542 | 0, // zsub2_then_hsub |
| 17543 | 0, // zsub2_then_ssub |
| 17544 | 0, // zsub2_then_zsub |
| 17545 | 0, // zsub2_then_zsub_hi |
| 17546 | 0, // dsub0_dsub1 |
| 17547 | 0, // dsub0_dsub1_dsub2 |
| 17548 | 0, // dsub1_dsub2 |
| 17549 | 0, // dsub1_dsub2_dsub3 |
| 17550 | 0, // dsub2_dsub3 |
| 17551 | 0, // dsub_qsub1_then_dsub |
| 17552 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17553 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17554 | 0, // qsub0_qsub1 |
| 17555 | 0, // qsub0_qsub1_qsub2 |
| 17556 | 0, // qsub1_qsub2 |
| 17557 | 0, // qsub1_qsub2_qsub3 |
| 17558 | 0, // qsub2_qsub3 |
| 17559 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17560 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17561 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17562 | 35, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17563 | 35, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17564 | 35, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17565 | 35, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17566 | 35, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17567 | 35, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17568 | 35, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17569 | 35, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17570 | 0, // sub_32_subo64_then_sub_32 |
| 17571 | 0, // dsub_zsub1_then_dsub |
| 17572 | 0, // zsub_zsub1_then_zsub |
| 17573 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17574 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17575 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17576 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17577 | 0, // zsub0_zsub1 |
| 17578 | 0, // zsub0_zsub1_zsub2 |
| 17579 | 0, // zsub1_zsub2 |
| 17580 | 0, // zsub1_zsub2_zsub3 |
| 17581 | 0, // zsub2_zsub3 |
| 17582 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17583 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17584 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17585 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17586 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17587 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17588 | }, |
| 17589 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17590 | 0, // bsub |
| 17591 | 0, // dsub |
| 17592 | 0, // dsub0 |
| 17593 | 0, // dsub1 |
| 17594 | 0, // dsub2 |
| 17595 | 0, // dsub3 |
| 17596 | 0, // hsub |
| 17597 | 0, // qhisub |
| 17598 | 0, // qsub |
| 17599 | 0, // qsub0 |
| 17600 | 0, // qsub1 |
| 17601 | 0, // qsub2 |
| 17602 | 0, // qsub3 |
| 17603 | 0, // ssub |
| 17604 | 36, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17605 | 0, // sube32 |
| 17606 | 0, // sube64 |
| 17607 | 0, // subo32 |
| 17608 | 0, // subo64 |
| 17609 | 36, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17610 | 36, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17611 | 36, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17612 | 36, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17613 | 36, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17614 | 36, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17615 | 36, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17616 | 36, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17617 | 0, // zsub |
| 17618 | 0, // zsub0 |
| 17619 | 0, // zsub1 |
| 17620 | 0, // zsub2 |
| 17621 | 0, // zsub3 |
| 17622 | 0, // zsub_hi |
| 17623 | 0, // dsub1_then_bsub |
| 17624 | 0, // dsub1_then_hsub |
| 17625 | 0, // dsub1_then_ssub |
| 17626 | 0, // dsub3_then_bsub |
| 17627 | 0, // dsub3_then_hsub |
| 17628 | 0, // dsub3_then_ssub |
| 17629 | 0, // dsub2_then_bsub |
| 17630 | 0, // dsub2_then_hsub |
| 17631 | 0, // dsub2_then_ssub |
| 17632 | 0, // qsub1_then_bsub |
| 17633 | 0, // qsub1_then_dsub |
| 17634 | 0, // qsub1_then_hsub |
| 17635 | 0, // qsub1_then_ssub |
| 17636 | 0, // qsub3_then_bsub |
| 17637 | 0, // qsub3_then_dsub |
| 17638 | 0, // qsub3_then_hsub |
| 17639 | 0, // qsub3_then_ssub |
| 17640 | 0, // qsub2_then_bsub |
| 17641 | 0, // qsub2_then_dsub |
| 17642 | 0, // qsub2_then_hsub |
| 17643 | 0, // qsub2_then_ssub |
| 17644 | 36, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17645 | 36, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17646 | 36, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17647 | 36, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17648 | 36, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17649 | 36, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17650 | 36, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17651 | 0, // subo64_then_sub_32 |
| 17652 | 0, // zsub1_then_bsub |
| 17653 | 0, // zsub1_then_dsub |
| 17654 | 0, // zsub1_then_hsub |
| 17655 | 0, // zsub1_then_ssub |
| 17656 | 0, // zsub1_then_zsub |
| 17657 | 0, // zsub1_then_zsub_hi |
| 17658 | 0, // zsub3_then_bsub |
| 17659 | 0, // zsub3_then_dsub |
| 17660 | 0, // zsub3_then_hsub |
| 17661 | 0, // zsub3_then_ssub |
| 17662 | 0, // zsub3_then_zsub |
| 17663 | 0, // zsub3_then_zsub_hi |
| 17664 | 0, // zsub2_then_bsub |
| 17665 | 0, // zsub2_then_dsub |
| 17666 | 0, // zsub2_then_hsub |
| 17667 | 0, // zsub2_then_ssub |
| 17668 | 0, // zsub2_then_zsub |
| 17669 | 0, // zsub2_then_zsub_hi |
| 17670 | 0, // dsub0_dsub1 |
| 17671 | 0, // dsub0_dsub1_dsub2 |
| 17672 | 0, // dsub1_dsub2 |
| 17673 | 0, // dsub1_dsub2_dsub3 |
| 17674 | 0, // dsub2_dsub3 |
| 17675 | 0, // dsub_qsub1_then_dsub |
| 17676 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17677 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17678 | 0, // qsub0_qsub1 |
| 17679 | 0, // qsub0_qsub1_qsub2 |
| 17680 | 0, // qsub1_qsub2 |
| 17681 | 0, // qsub1_qsub2_qsub3 |
| 17682 | 0, // qsub2_qsub3 |
| 17683 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17684 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17685 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17686 | 36, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17687 | 36, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17688 | 36, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17689 | 36, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17690 | 36, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17691 | 36, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17692 | 36, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17693 | 36, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 17694 | 0, // sub_32_subo64_then_sub_32 |
| 17695 | 0, // dsub_zsub1_then_dsub |
| 17696 | 0, // zsub_zsub1_then_zsub |
| 17697 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17698 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17699 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17700 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17701 | 0, // zsub0_zsub1 |
| 17702 | 0, // zsub0_zsub1_zsub2 |
| 17703 | 0, // zsub1_zsub2 |
| 17704 | 0, // zsub1_zsub2_zsub3 |
| 17705 | 0, // zsub2_zsub3 |
| 17706 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17707 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17708 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17709 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17710 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17711 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17712 | }, |
| 17713 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17714 | 0, // bsub |
| 17715 | 0, // dsub |
| 17716 | 0, // dsub0 |
| 17717 | 0, // dsub1 |
| 17718 | 0, // dsub2 |
| 17719 | 0, // dsub3 |
| 17720 | 0, // hsub |
| 17721 | 0, // qhisub |
| 17722 | 0, // qsub |
| 17723 | 0, // qsub0 |
| 17724 | 0, // qsub1 |
| 17725 | 0, // qsub2 |
| 17726 | 0, // qsub3 |
| 17727 | 0, // ssub |
| 17728 | 37, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17729 | 0, // sube32 |
| 17730 | 0, // sube64 |
| 17731 | 0, // subo32 |
| 17732 | 0, // subo64 |
| 17733 | 37, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17734 | 37, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17735 | 37, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17736 | 37, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17737 | 37, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17738 | 37, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17739 | 37, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17740 | 37, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17741 | 0, // zsub |
| 17742 | 0, // zsub0 |
| 17743 | 0, // zsub1 |
| 17744 | 0, // zsub2 |
| 17745 | 0, // zsub3 |
| 17746 | 0, // zsub_hi |
| 17747 | 0, // dsub1_then_bsub |
| 17748 | 0, // dsub1_then_hsub |
| 17749 | 0, // dsub1_then_ssub |
| 17750 | 0, // dsub3_then_bsub |
| 17751 | 0, // dsub3_then_hsub |
| 17752 | 0, // dsub3_then_ssub |
| 17753 | 0, // dsub2_then_bsub |
| 17754 | 0, // dsub2_then_hsub |
| 17755 | 0, // dsub2_then_ssub |
| 17756 | 0, // qsub1_then_bsub |
| 17757 | 0, // qsub1_then_dsub |
| 17758 | 0, // qsub1_then_hsub |
| 17759 | 0, // qsub1_then_ssub |
| 17760 | 0, // qsub3_then_bsub |
| 17761 | 0, // qsub3_then_dsub |
| 17762 | 0, // qsub3_then_hsub |
| 17763 | 0, // qsub3_then_ssub |
| 17764 | 0, // qsub2_then_bsub |
| 17765 | 0, // qsub2_then_dsub |
| 17766 | 0, // qsub2_then_hsub |
| 17767 | 0, // qsub2_then_ssub |
| 17768 | 37, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17769 | 37, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17770 | 37, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17771 | 37, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17772 | 37, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17773 | 37, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17774 | 37, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17775 | 0, // subo64_then_sub_32 |
| 17776 | 0, // zsub1_then_bsub |
| 17777 | 0, // zsub1_then_dsub |
| 17778 | 0, // zsub1_then_hsub |
| 17779 | 0, // zsub1_then_ssub |
| 17780 | 0, // zsub1_then_zsub |
| 17781 | 0, // zsub1_then_zsub_hi |
| 17782 | 0, // zsub3_then_bsub |
| 17783 | 0, // zsub3_then_dsub |
| 17784 | 0, // zsub3_then_hsub |
| 17785 | 0, // zsub3_then_ssub |
| 17786 | 0, // zsub3_then_zsub |
| 17787 | 0, // zsub3_then_zsub_hi |
| 17788 | 0, // zsub2_then_bsub |
| 17789 | 0, // zsub2_then_dsub |
| 17790 | 0, // zsub2_then_hsub |
| 17791 | 0, // zsub2_then_ssub |
| 17792 | 0, // zsub2_then_zsub |
| 17793 | 0, // zsub2_then_zsub_hi |
| 17794 | 0, // dsub0_dsub1 |
| 17795 | 0, // dsub0_dsub1_dsub2 |
| 17796 | 0, // dsub1_dsub2 |
| 17797 | 0, // dsub1_dsub2_dsub3 |
| 17798 | 0, // dsub2_dsub3 |
| 17799 | 0, // dsub_qsub1_then_dsub |
| 17800 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17801 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17802 | 0, // qsub0_qsub1 |
| 17803 | 0, // qsub0_qsub1_qsub2 |
| 17804 | 0, // qsub1_qsub2 |
| 17805 | 0, // qsub1_qsub2_qsub3 |
| 17806 | 0, // qsub2_qsub3 |
| 17807 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17808 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17809 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17810 | 37, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17811 | 37, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17812 | 37, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17813 | 37, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17814 | 37, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17815 | 37, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17816 | 37, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17817 | 37, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 17818 | 0, // sub_32_subo64_then_sub_32 |
| 17819 | 0, // dsub_zsub1_then_dsub |
| 17820 | 0, // zsub_zsub1_then_zsub |
| 17821 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17822 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17823 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17824 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17825 | 0, // zsub0_zsub1 |
| 17826 | 0, // zsub0_zsub1_zsub2 |
| 17827 | 0, // zsub1_zsub2 |
| 17828 | 0, // zsub1_zsub2_zsub3 |
| 17829 | 0, // zsub2_zsub3 |
| 17830 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17831 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17832 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17833 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17834 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17835 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17836 | }, |
| 17837 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17838 | 0, // bsub |
| 17839 | 0, // dsub |
| 17840 | 0, // dsub0 |
| 17841 | 0, // dsub1 |
| 17842 | 0, // dsub2 |
| 17843 | 0, // dsub3 |
| 17844 | 0, // hsub |
| 17845 | 0, // qhisub |
| 17846 | 0, // qsub |
| 17847 | 0, // qsub0 |
| 17848 | 0, // qsub1 |
| 17849 | 0, // qsub2 |
| 17850 | 0, // qsub3 |
| 17851 | 0, // ssub |
| 17852 | 38, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17853 | 0, // sube32 |
| 17854 | 0, // sube64 |
| 17855 | 0, // subo32 |
| 17856 | 0, // subo64 |
| 17857 | 38, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17858 | 38, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17859 | 38, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17860 | 38, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17861 | 38, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17862 | 38, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17863 | 38, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17864 | 38, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17865 | 0, // zsub |
| 17866 | 0, // zsub0 |
| 17867 | 0, // zsub1 |
| 17868 | 0, // zsub2 |
| 17869 | 0, // zsub3 |
| 17870 | 0, // zsub_hi |
| 17871 | 0, // dsub1_then_bsub |
| 17872 | 0, // dsub1_then_hsub |
| 17873 | 0, // dsub1_then_ssub |
| 17874 | 0, // dsub3_then_bsub |
| 17875 | 0, // dsub3_then_hsub |
| 17876 | 0, // dsub3_then_ssub |
| 17877 | 0, // dsub2_then_bsub |
| 17878 | 0, // dsub2_then_hsub |
| 17879 | 0, // dsub2_then_ssub |
| 17880 | 0, // qsub1_then_bsub |
| 17881 | 0, // qsub1_then_dsub |
| 17882 | 0, // qsub1_then_hsub |
| 17883 | 0, // qsub1_then_ssub |
| 17884 | 0, // qsub3_then_bsub |
| 17885 | 0, // qsub3_then_dsub |
| 17886 | 0, // qsub3_then_hsub |
| 17887 | 0, // qsub3_then_ssub |
| 17888 | 0, // qsub2_then_bsub |
| 17889 | 0, // qsub2_then_dsub |
| 17890 | 0, // qsub2_then_hsub |
| 17891 | 0, // qsub2_then_ssub |
| 17892 | 38, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17893 | 38, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17894 | 38, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17895 | 38, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17896 | 38, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17897 | 38, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17898 | 38, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17899 | 0, // subo64_then_sub_32 |
| 17900 | 0, // zsub1_then_bsub |
| 17901 | 0, // zsub1_then_dsub |
| 17902 | 0, // zsub1_then_hsub |
| 17903 | 0, // zsub1_then_ssub |
| 17904 | 0, // zsub1_then_zsub |
| 17905 | 0, // zsub1_then_zsub_hi |
| 17906 | 0, // zsub3_then_bsub |
| 17907 | 0, // zsub3_then_dsub |
| 17908 | 0, // zsub3_then_hsub |
| 17909 | 0, // zsub3_then_ssub |
| 17910 | 0, // zsub3_then_zsub |
| 17911 | 0, // zsub3_then_zsub_hi |
| 17912 | 0, // zsub2_then_bsub |
| 17913 | 0, // zsub2_then_dsub |
| 17914 | 0, // zsub2_then_hsub |
| 17915 | 0, // zsub2_then_ssub |
| 17916 | 0, // zsub2_then_zsub |
| 17917 | 0, // zsub2_then_zsub_hi |
| 17918 | 0, // dsub0_dsub1 |
| 17919 | 0, // dsub0_dsub1_dsub2 |
| 17920 | 0, // dsub1_dsub2 |
| 17921 | 0, // dsub1_dsub2_dsub3 |
| 17922 | 0, // dsub2_dsub3 |
| 17923 | 0, // dsub_qsub1_then_dsub |
| 17924 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17925 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 17926 | 0, // qsub0_qsub1 |
| 17927 | 0, // qsub0_qsub1_qsub2 |
| 17928 | 0, // qsub1_qsub2 |
| 17929 | 0, // qsub1_qsub2_qsub3 |
| 17930 | 0, // qsub2_qsub3 |
| 17931 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 17932 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 17933 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 17934 | 38, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17935 | 38, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17936 | 38, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17937 | 38, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17938 | 38, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17939 | 38, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17940 | 38, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17941 | 38, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17942 | 0, // sub_32_subo64_then_sub_32 |
| 17943 | 0, // dsub_zsub1_then_dsub |
| 17944 | 0, // zsub_zsub1_then_zsub |
| 17945 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17946 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 17947 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17948 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 17949 | 0, // zsub0_zsub1 |
| 17950 | 0, // zsub0_zsub1_zsub2 |
| 17951 | 0, // zsub1_zsub2 |
| 17952 | 0, // zsub1_zsub2_zsub3 |
| 17953 | 0, // zsub2_zsub3 |
| 17954 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 17955 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 17956 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 17957 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 17958 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 17959 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 17960 | }, |
| 17961 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17962 | 0, // bsub |
| 17963 | 0, // dsub |
| 17964 | 0, // dsub0 |
| 17965 | 0, // dsub1 |
| 17966 | 0, // dsub2 |
| 17967 | 0, // dsub3 |
| 17968 | 0, // hsub |
| 17969 | 0, // qhisub |
| 17970 | 0, // qsub |
| 17971 | 0, // qsub0 |
| 17972 | 0, // qsub1 |
| 17973 | 0, // qsub2 |
| 17974 | 0, // qsub3 |
| 17975 | 0, // ssub |
| 17976 | 39, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17977 | 0, // sube32 |
| 17978 | 0, // sube64 |
| 17979 | 0, // subo32 |
| 17980 | 0, // subo64 |
| 17981 | 39, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17982 | 39, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17983 | 39, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17984 | 39, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17985 | 39, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17986 | 39, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17987 | 39, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17988 | 39, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 17989 | 0, // zsub |
| 17990 | 0, // zsub0 |
| 17991 | 0, // zsub1 |
| 17992 | 0, // zsub2 |
| 17993 | 0, // zsub3 |
| 17994 | 0, // zsub_hi |
| 17995 | 0, // dsub1_then_bsub |
| 17996 | 0, // dsub1_then_hsub |
| 17997 | 0, // dsub1_then_ssub |
| 17998 | 0, // dsub3_then_bsub |
| 17999 | 0, // dsub3_then_hsub |
| 18000 | 0, // dsub3_then_ssub |
| 18001 | 0, // dsub2_then_bsub |
| 18002 | 0, // dsub2_then_hsub |
| 18003 | 0, // dsub2_then_ssub |
| 18004 | 0, // qsub1_then_bsub |
| 18005 | 0, // qsub1_then_dsub |
| 18006 | 0, // qsub1_then_hsub |
| 18007 | 0, // qsub1_then_ssub |
| 18008 | 0, // qsub3_then_bsub |
| 18009 | 0, // qsub3_then_dsub |
| 18010 | 0, // qsub3_then_hsub |
| 18011 | 0, // qsub3_then_ssub |
| 18012 | 0, // qsub2_then_bsub |
| 18013 | 0, // qsub2_then_dsub |
| 18014 | 0, // qsub2_then_hsub |
| 18015 | 0, // qsub2_then_ssub |
| 18016 | 39, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18017 | 39, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18018 | 39, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18019 | 39, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18020 | 39, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18021 | 39, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18022 | 39, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18023 | 0, // subo64_then_sub_32 |
| 18024 | 0, // zsub1_then_bsub |
| 18025 | 0, // zsub1_then_dsub |
| 18026 | 0, // zsub1_then_hsub |
| 18027 | 0, // zsub1_then_ssub |
| 18028 | 0, // zsub1_then_zsub |
| 18029 | 0, // zsub1_then_zsub_hi |
| 18030 | 0, // zsub3_then_bsub |
| 18031 | 0, // zsub3_then_dsub |
| 18032 | 0, // zsub3_then_hsub |
| 18033 | 0, // zsub3_then_ssub |
| 18034 | 0, // zsub3_then_zsub |
| 18035 | 0, // zsub3_then_zsub_hi |
| 18036 | 0, // zsub2_then_bsub |
| 18037 | 0, // zsub2_then_dsub |
| 18038 | 0, // zsub2_then_hsub |
| 18039 | 0, // zsub2_then_ssub |
| 18040 | 0, // zsub2_then_zsub |
| 18041 | 0, // zsub2_then_zsub_hi |
| 18042 | 0, // dsub0_dsub1 |
| 18043 | 0, // dsub0_dsub1_dsub2 |
| 18044 | 0, // dsub1_dsub2 |
| 18045 | 0, // dsub1_dsub2_dsub3 |
| 18046 | 0, // dsub2_dsub3 |
| 18047 | 0, // dsub_qsub1_then_dsub |
| 18048 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18049 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18050 | 0, // qsub0_qsub1 |
| 18051 | 0, // qsub0_qsub1_qsub2 |
| 18052 | 0, // qsub1_qsub2 |
| 18053 | 0, // qsub1_qsub2_qsub3 |
| 18054 | 0, // qsub2_qsub3 |
| 18055 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18056 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18057 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18058 | 39, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18059 | 39, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18060 | 39, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18061 | 39, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18062 | 39, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18063 | 39, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18064 | 39, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18065 | 39, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18066 | 0, // sub_32_subo64_then_sub_32 |
| 18067 | 0, // dsub_zsub1_then_dsub |
| 18068 | 0, // zsub_zsub1_then_zsub |
| 18069 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18070 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18071 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18072 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18073 | 0, // zsub0_zsub1 |
| 18074 | 0, // zsub0_zsub1_zsub2 |
| 18075 | 0, // zsub1_zsub2 |
| 18076 | 0, // zsub1_zsub2_zsub3 |
| 18077 | 0, // zsub2_zsub3 |
| 18078 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18079 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18080 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18081 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18082 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18083 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18084 | }, |
| 18085 | { // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18086 | 0, // bsub |
| 18087 | 0, // dsub |
| 18088 | 0, // dsub0 |
| 18089 | 0, // dsub1 |
| 18090 | 0, // dsub2 |
| 18091 | 0, // dsub3 |
| 18092 | 0, // hsub |
| 18093 | 0, // qhisub |
| 18094 | 0, // qsub |
| 18095 | 0, // qsub0 |
| 18096 | 0, // qsub1 |
| 18097 | 0, // qsub2 |
| 18098 | 0, // qsub3 |
| 18099 | 0, // ssub |
| 18100 | 40, // sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18101 | 0, // sube32 |
| 18102 | 0, // sube64 |
| 18103 | 0, // subo32 |
| 18104 | 0, // subo64 |
| 18105 | 40, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18106 | 40, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18107 | 40, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18108 | 40, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18109 | 40, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18110 | 40, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18111 | 40, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18112 | 40, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18113 | 0, // zsub |
| 18114 | 0, // zsub0 |
| 18115 | 0, // zsub1 |
| 18116 | 0, // zsub2 |
| 18117 | 0, // zsub3 |
| 18118 | 0, // zsub_hi |
| 18119 | 0, // dsub1_then_bsub |
| 18120 | 0, // dsub1_then_hsub |
| 18121 | 0, // dsub1_then_ssub |
| 18122 | 0, // dsub3_then_bsub |
| 18123 | 0, // dsub3_then_hsub |
| 18124 | 0, // dsub3_then_ssub |
| 18125 | 0, // dsub2_then_bsub |
| 18126 | 0, // dsub2_then_hsub |
| 18127 | 0, // dsub2_then_ssub |
| 18128 | 0, // qsub1_then_bsub |
| 18129 | 0, // qsub1_then_dsub |
| 18130 | 0, // qsub1_then_hsub |
| 18131 | 0, // qsub1_then_ssub |
| 18132 | 0, // qsub3_then_bsub |
| 18133 | 0, // qsub3_then_dsub |
| 18134 | 0, // qsub3_then_hsub |
| 18135 | 0, // qsub3_then_ssub |
| 18136 | 0, // qsub2_then_bsub |
| 18137 | 0, // qsub2_then_dsub |
| 18138 | 0, // qsub2_then_hsub |
| 18139 | 0, // qsub2_then_ssub |
| 18140 | 40, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18141 | 40, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18142 | 40, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18143 | 40, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18144 | 40, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18145 | 40, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18146 | 40, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18147 | 0, // subo64_then_sub_32 |
| 18148 | 0, // zsub1_then_bsub |
| 18149 | 0, // zsub1_then_dsub |
| 18150 | 0, // zsub1_then_hsub |
| 18151 | 0, // zsub1_then_ssub |
| 18152 | 0, // zsub1_then_zsub |
| 18153 | 0, // zsub1_then_zsub_hi |
| 18154 | 0, // zsub3_then_bsub |
| 18155 | 0, // zsub3_then_dsub |
| 18156 | 0, // zsub3_then_hsub |
| 18157 | 0, // zsub3_then_ssub |
| 18158 | 0, // zsub3_then_zsub |
| 18159 | 0, // zsub3_then_zsub_hi |
| 18160 | 0, // zsub2_then_bsub |
| 18161 | 0, // zsub2_then_dsub |
| 18162 | 0, // zsub2_then_hsub |
| 18163 | 0, // zsub2_then_ssub |
| 18164 | 0, // zsub2_then_zsub |
| 18165 | 0, // zsub2_then_zsub_hi |
| 18166 | 0, // dsub0_dsub1 |
| 18167 | 0, // dsub0_dsub1_dsub2 |
| 18168 | 0, // dsub1_dsub2 |
| 18169 | 0, // dsub1_dsub2_dsub3 |
| 18170 | 0, // dsub2_dsub3 |
| 18171 | 0, // dsub_qsub1_then_dsub |
| 18172 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18173 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18174 | 0, // qsub0_qsub1 |
| 18175 | 0, // qsub0_qsub1_qsub2 |
| 18176 | 0, // qsub1_qsub2 |
| 18177 | 0, // qsub1_qsub2_qsub3 |
| 18178 | 0, // qsub2_qsub3 |
| 18179 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18180 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18181 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18182 | 40, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18183 | 40, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18184 | 40, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18185 | 40, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18186 | 40, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18187 | 40, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18188 | 40, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18189 | 40, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 18190 | 0, // sub_32_subo64_then_sub_32 |
| 18191 | 0, // dsub_zsub1_then_dsub |
| 18192 | 0, // zsub_zsub1_then_zsub |
| 18193 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18194 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18195 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18196 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18197 | 0, // zsub0_zsub1 |
| 18198 | 0, // zsub0_zsub1_zsub2 |
| 18199 | 0, // zsub1_zsub2 |
| 18200 | 0, // zsub1_zsub2_zsub3 |
| 18201 | 0, // zsub2_zsub3 |
| 18202 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18203 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18204 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18205 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18206 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18207 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18208 | }, |
| 18209 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18210 | 0, // bsub |
| 18211 | 0, // dsub |
| 18212 | 0, // dsub0 |
| 18213 | 0, // dsub1 |
| 18214 | 0, // dsub2 |
| 18215 | 0, // dsub3 |
| 18216 | 0, // hsub |
| 18217 | 0, // qhisub |
| 18218 | 0, // qsub |
| 18219 | 0, // qsub0 |
| 18220 | 0, // qsub1 |
| 18221 | 0, // qsub2 |
| 18222 | 0, // qsub3 |
| 18223 | 0, // ssub |
| 18224 | 41, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18225 | 0, // sube32 |
| 18226 | 0, // sube64 |
| 18227 | 0, // subo32 |
| 18228 | 0, // subo64 |
| 18229 | 41, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18230 | 41, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18231 | 41, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18232 | 41, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18233 | 41, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18234 | 41, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18235 | 41, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18236 | 41, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18237 | 0, // zsub |
| 18238 | 0, // zsub0 |
| 18239 | 0, // zsub1 |
| 18240 | 0, // zsub2 |
| 18241 | 0, // zsub3 |
| 18242 | 0, // zsub_hi |
| 18243 | 0, // dsub1_then_bsub |
| 18244 | 0, // dsub1_then_hsub |
| 18245 | 0, // dsub1_then_ssub |
| 18246 | 0, // dsub3_then_bsub |
| 18247 | 0, // dsub3_then_hsub |
| 18248 | 0, // dsub3_then_ssub |
| 18249 | 0, // dsub2_then_bsub |
| 18250 | 0, // dsub2_then_hsub |
| 18251 | 0, // dsub2_then_ssub |
| 18252 | 0, // qsub1_then_bsub |
| 18253 | 0, // qsub1_then_dsub |
| 18254 | 0, // qsub1_then_hsub |
| 18255 | 0, // qsub1_then_ssub |
| 18256 | 0, // qsub3_then_bsub |
| 18257 | 0, // qsub3_then_dsub |
| 18258 | 0, // qsub3_then_hsub |
| 18259 | 0, // qsub3_then_ssub |
| 18260 | 0, // qsub2_then_bsub |
| 18261 | 0, // qsub2_then_dsub |
| 18262 | 0, // qsub2_then_hsub |
| 18263 | 0, // qsub2_then_ssub |
| 18264 | 41, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18265 | 41, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18266 | 41, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18267 | 41, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18268 | 41, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18269 | 41, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18270 | 41, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18271 | 0, // subo64_then_sub_32 |
| 18272 | 0, // zsub1_then_bsub |
| 18273 | 0, // zsub1_then_dsub |
| 18274 | 0, // zsub1_then_hsub |
| 18275 | 0, // zsub1_then_ssub |
| 18276 | 0, // zsub1_then_zsub |
| 18277 | 0, // zsub1_then_zsub_hi |
| 18278 | 0, // zsub3_then_bsub |
| 18279 | 0, // zsub3_then_dsub |
| 18280 | 0, // zsub3_then_hsub |
| 18281 | 0, // zsub3_then_ssub |
| 18282 | 0, // zsub3_then_zsub |
| 18283 | 0, // zsub3_then_zsub_hi |
| 18284 | 0, // zsub2_then_bsub |
| 18285 | 0, // zsub2_then_dsub |
| 18286 | 0, // zsub2_then_hsub |
| 18287 | 0, // zsub2_then_ssub |
| 18288 | 0, // zsub2_then_zsub |
| 18289 | 0, // zsub2_then_zsub_hi |
| 18290 | 0, // dsub0_dsub1 |
| 18291 | 0, // dsub0_dsub1_dsub2 |
| 18292 | 0, // dsub1_dsub2 |
| 18293 | 0, // dsub1_dsub2_dsub3 |
| 18294 | 0, // dsub2_dsub3 |
| 18295 | 0, // dsub_qsub1_then_dsub |
| 18296 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18297 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18298 | 0, // qsub0_qsub1 |
| 18299 | 0, // qsub0_qsub1_qsub2 |
| 18300 | 0, // qsub1_qsub2 |
| 18301 | 0, // qsub1_qsub2_qsub3 |
| 18302 | 0, // qsub2_qsub3 |
| 18303 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18304 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18305 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18306 | 41, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18307 | 41, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18308 | 41, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18309 | 41, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18310 | 41, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18311 | 41, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18312 | 41, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18313 | 41, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 18314 | 0, // sub_32_subo64_then_sub_32 |
| 18315 | 0, // dsub_zsub1_then_dsub |
| 18316 | 0, // zsub_zsub1_then_zsub |
| 18317 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18318 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18319 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18320 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18321 | 0, // zsub0_zsub1 |
| 18322 | 0, // zsub0_zsub1_zsub2 |
| 18323 | 0, // zsub1_zsub2 |
| 18324 | 0, // zsub1_zsub2_zsub3 |
| 18325 | 0, // zsub2_zsub3 |
| 18326 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18327 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18328 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18329 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18330 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18331 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18332 | }, |
| 18333 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18334 | 0, // bsub |
| 18335 | 0, // dsub |
| 18336 | 0, // dsub0 |
| 18337 | 0, // dsub1 |
| 18338 | 0, // dsub2 |
| 18339 | 0, // dsub3 |
| 18340 | 0, // hsub |
| 18341 | 0, // qhisub |
| 18342 | 0, // qsub |
| 18343 | 0, // qsub0 |
| 18344 | 0, // qsub1 |
| 18345 | 0, // qsub2 |
| 18346 | 0, // qsub3 |
| 18347 | 0, // ssub |
| 18348 | 42, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18349 | 0, // sube32 |
| 18350 | 0, // sube64 |
| 18351 | 0, // subo32 |
| 18352 | 0, // subo64 |
| 18353 | 42, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18354 | 42, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18355 | 42, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18356 | 42, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18357 | 42, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18358 | 42, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18359 | 42, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18360 | 42, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18361 | 0, // zsub |
| 18362 | 0, // zsub0 |
| 18363 | 0, // zsub1 |
| 18364 | 0, // zsub2 |
| 18365 | 0, // zsub3 |
| 18366 | 0, // zsub_hi |
| 18367 | 0, // dsub1_then_bsub |
| 18368 | 0, // dsub1_then_hsub |
| 18369 | 0, // dsub1_then_ssub |
| 18370 | 0, // dsub3_then_bsub |
| 18371 | 0, // dsub3_then_hsub |
| 18372 | 0, // dsub3_then_ssub |
| 18373 | 0, // dsub2_then_bsub |
| 18374 | 0, // dsub2_then_hsub |
| 18375 | 0, // dsub2_then_ssub |
| 18376 | 0, // qsub1_then_bsub |
| 18377 | 0, // qsub1_then_dsub |
| 18378 | 0, // qsub1_then_hsub |
| 18379 | 0, // qsub1_then_ssub |
| 18380 | 0, // qsub3_then_bsub |
| 18381 | 0, // qsub3_then_dsub |
| 18382 | 0, // qsub3_then_hsub |
| 18383 | 0, // qsub3_then_ssub |
| 18384 | 0, // qsub2_then_bsub |
| 18385 | 0, // qsub2_then_dsub |
| 18386 | 0, // qsub2_then_hsub |
| 18387 | 0, // qsub2_then_ssub |
| 18388 | 42, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18389 | 42, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18390 | 42, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18391 | 42, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18392 | 42, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18393 | 42, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18394 | 42, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18395 | 0, // subo64_then_sub_32 |
| 18396 | 0, // zsub1_then_bsub |
| 18397 | 0, // zsub1_then_dsub |
| 18398 | 0, // zsub1_then_hsub |
| 18399 | 0, // zsub1_then_ssub |
| 18400 | 0, // zsub1_then_zsub |
| 18401 | 0, // zsub1_then_zsub_hi |
| 18402 | 0, // zsub3_then_bsub |
| 18403 | 0, // zsub3_then_dsub |
| 18404 | 0, // zsub3_then_hsub |
| 18405 | 0, // zsub3_then_ssub |
| 18406 | 0, // zsub3_then_zsub |
| 18407 | 0, // zsub3_then_zsub_hi |
| 18408 | 0, // zsub2_then_bsub |
| 18409 | 0, // zsub2_then_dsub |
| 18410 | 0, // zsub2_then_hsub |
| 18411 | 0, // zsub2_then_ssub |
| 18412 | 0, // zsub2_then_zsub |
| 18413 | 0, // zsub2_then_zsub_hi |
| 18414 | 0, // dsub0_dsub1 |
| 18415 | 0, // dsub0_dsub1_dsub2 |
| 18416 | 0, // dsub1_dsub2 |
| 18417 | 0, // dsub1_dsub2_dsub3 |
| 18418 | 0, // dsub2_dsub3 |
| 18419 | 0, // dsub_qsub1_then_dsub |
| 18420 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18421 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18422 | 0, // qsub0_qsub1 |
| 18423 | 0, // qsub0_qsub1_qsub2 |
| 18424 | 0, // qsub1_qsub2 |
| 18425 | 0, // qsub1_qsub2_qsub3 |
| 18426 | 0, // qsub2_qsub3 |
| 18427 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18428 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18429 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18430 | 42, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18431 | 42, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18432 | 42, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18433 | 42, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18434 | 42, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18435 | 42, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18436 | 42, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18437 | 42, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18438 | 0, // sub_32_subo64_then_sub_32 |
| 18439 | 0, // dsub_zsub1_then_dsub |
| 18440 | 0, // zsub_zsub1_then_zsub |
| 18441 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18442 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18443 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18444 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18445 | 0, // zsub0_zsub1 |
| 18446 | 0, // zsub0_zsub1_zsub2 |
| 18447 | 0, // zsub1_zsub2 |
| 18448 | 0, // zsub1_zsub2_zsub3 |
| 18449 | 0, // zsub2_zsub3 |
| 18450 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18451 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18452 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18453 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18454 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18455 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18456 | }, |
| 18457 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18458 | 0, // bsub |
| 18459 | 0, // dsub |
| 18460 | 0, // dsub0 |
| 18461 | 0, // dsub1 |
| 18462 | 0, // dsub2 |
| 18463 | 0, // dsub3 |
| 18464 | 0, // hsub |
| 18465 | 0, // qhisub |
| 18466 | 0, // qsub |
| 18467 | 0, // qsub0 |
| 18468 | 0, // qsub1 |
| 18469 | 0, // qsub2 |
| 18470 | 0, // qsub3 |
| 18471 | 0, // ssub |
| 18472 | 43, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18473 | 0, // sube32 |
| 18474 | 0, // sube64 |
| 18475 | 0, // subo32 |
| 18476 | 0, // subo64 |
| 18477 | 43, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18478 | 43, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18479 | 43, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18480 | 43, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18481 | 43, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18482 | 43, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18483 | 43, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18484 | 43, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18485 | 0, // zsub |
| 18486 | 0, // zsub0 |
| 18487 | 0, // zsub1 |
| 18488 | 0, // zsub2 |
| 18489 | 0, // zsub3 |
| 18490 | 0, // zsub_hi |
| 18491 | 0, // dsub1_then_bsub |
| 18492 | 0, // dsub1_then_hsub |
| 18493 | 0, // dsub1_then_ssub |
| 18494 | 0, // dsub3_then_bsub |
| 18495 | 0, // dsub3_then_hsub |
| 18496 | 0, // dsub3_then_ssub |
| 18497 | 0, // dsub2_then_bsub |
| 18498 | 0, // dsub2_then_hsub |
| 18499 | 0, // dsub2_then_ssub |
| 18500 | 0, // qsub1_then_bsub |
| 18501 | 0, // qsub1_then_dsub |
| 18502 | 0, // qsub1_then_hsub |
| 18503 | 0, // qsub1_then_ssub |
| 18504 | 0, // qsub3_then_bsub |
| 18505 | 0, // qsub3_then_dsub |
| 18506 | 0, // qsub3_then_hsub |
| 18507 | 0, // qsub3_then_ssub |
| 18508 | 0, // qsub2_then_bsub |
| 18509 | 0, // qsub2_then_dsub |
| 18510 | 0, // qsub2_then_hsub |
| 18511 | 0, // qsub2_then_ssub |
| 18512 | 43, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18513 | 43, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18514 | 43, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18515 | 43, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18516 | 43, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18517 | 43, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18518 | 43, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18519 | 0, // subo64_then_sub_32 |
| 18520 | 0, // zsub1_then_bsub |
| 18521 | 0, // zsub1_then_dsub |
| 18522 | 0, // zsub1_then_hsub |
| 18523 | 0, // zsub1_then_ssub |
| 18524 | 0, // zsub1_then_zsub |
| 18525 | 0, // zsub1_then_zsub_hi |
| 18526 | 0, // zsub3_then_bsub |
| 18527 | 0, // zsub3_then_dsub |
| 18528 | 0, // zsub3_then_hsub |
| 18529 | 0, // zsub3_then_ssub |
| 18530 | 0, // zsub3_then_zsub |
| 18531 | 0, // zsub3_then_zsub_hi |
| 18532 | 0, // zsub2_then_bsub |
| 18533 | 0, // zsub2_then_dsub |
| 18534 | 0, // zsub2_then_hsub |
| 18535 | 0, // zsub2_then_ssub |
| 18536 | 0, // zsub2_then_zsub |
| 18537 | 0, // zsub2_then_zsub_hi |
| 18538 | 0, // dsub0_dsub1 |
| 18539 | 0, // dsub0_dsub1_dsub2 |
| 18540 | 0, // dsub1_dsub2 |
| 18541 | 0, // dsub1_dsub2_dsub3 |
| 18542 | 0, // dsub2_dsub3 |
| 18543 | 0, // dsub_qsub1_then_dsub |
| 18544 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18545 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18546 | 0, // qsub0_qsub1 |
| 18547 | 0, // qsub0_qsub1_qsub2 |
| 18548 | 0, // qsub1_qsub2 |
| 18549 | 0, // qsub1_qsub2_qsub3 |
| 18550 | 0, // qsub2_qsub3 |
| 18551 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18552 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18553 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18554 | 43, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18555 | 43, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18556 | 43, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18557 | 43, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18558 | 43, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18559 | 43, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18560 | 43, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18561 | 43, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18562 | 0, // sub_32_subo64_then_sub_32 |
| 18563 | 0, // dsub_zsub1_then_dsub |
| 18564 | 0, // zsub_zsub1_then_zsub |
| 18565 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18566 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18567 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18568 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18569 | 0, // zsub0_zsub1 |
| 18570 | 0, // zsub0_zsub1_zsub2 |
| 18571 | 0, // zsub1_zsub2 |
| 18572 | 0, // zsub1_zsub2_zsub3 |
| 18573 | 0, // zsub2_zsub3 |
| 18574 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18575 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18576 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18577 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18578 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18579 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18580 | }, |
| 18581 | { // GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18582 | 0, // bsub |
| 18583 | 0, // dsub |
| 18584 | 0, // dsub0 |
| 18585 | 0, // dsub1 |
| 18586 | 0, // dsub2 |
| 18587 | 0, // dsub3 |
| 18588 | 0, // hsub |
| 18589 | 0, // qhisub |
| 18590 | 0, // qsub |
| 18591 | 0, // qsub0 |
| 18592 | 0, // qsub1 |
| 18593 | 0, // qsub2 |
| 18594 | 0, // qsub3 |
| 18595 | 0, // ssub |
| 18596 | 44, // sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18597 | 0, // sube32 |
| 18598 | 0, // sube64 |
| 18599 | 0, // subo32 |
| 18600 | 0, // subo64 |
| 18601 | 44, // x8sub_0 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18602 | 44, // x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18603 | 44, // x8sub_2 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18604 | 44, // x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18605 | 44, // x8sub_4 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18606 | 44, // x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18607 | 44, // x8sub_6 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18608 | 44, // x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18609 | 0, // zsub |
| 18610 | 0, // zsub0 |
| 18611 | 0, // zsub1 |
| 18612 | 0, // zsub2 |
| 18613 | 0, // zsub3 |
| 18614 | 0, // zsub_hi |
| 18615 | 0, // dsub1_then_bsub |
| 18616 | 0, // dsub1_then_hsub |
| 18617 | 0, // dsub1_then_ssub |
| 18618 | 0, // dsub3_then_bsub |
| 18619 | 0, // dsub3_then_hsub |
| 18620 | 0, // dsub3_then_ssub |
| 18621 | 0, // dsub2_then_bsub |
| 18622 | 0, // dsub2_then_hsub |
| 18623 | 0, // dsub2_then_ssub |
| 18624 | 0, // qsub1_then_bsub |
| 18625 | 0, // qsub1_then_dsub |
| 18626 | 0, // qsub1_then_hsub |
| 18627 | 0, // qsub1_then_ssub |
| 18628 | 0, // qsub3_then_bsub |
| 18629 | 0, // qsub3_then_dsub |
| 18630 | 0, // qsub3_then_hsub |
| 18631 | 0, // qsub3_then_ssub |
| 18632 | 0, // qsub2_then_bsub |
| 18633 | 0, // qsub2_then_dsub |
| 18634 | 0, // qsub2_then_hsub |
| 18635 | 0, // qsub2_then_ssub |
| 18636 | 44, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18637 | 44, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18638 | 44, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18639 | 44, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18640 | 44, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18641 | 44, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18642 | 44, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18643 | 0, // subo64_then_sub_32 |
| 18644 | 0, // zsub1_then_bsub |
| 18645 | 0, // zsub1_then_dsub |
| 18646 | 0, // zsub1_then_hsub |
| 18647 | 0, // zsub1_then_ssub |
| 18648 | 0, // zsub1_then_zsub |
| 18649 | 0, // zsub1_then_zsub_hi |
| 18650 | 0, // zsub3_then_bsub |
| 18651 | 0, // zsub3_then_dsub |
| 18652 | 0, // zsub3_then_hsub |
| 18653 | 0, // zsub3_then_ssub |
| 18654 | 0, // zsub3_then_zsub |
| 18655 | 0, // zsub3_then_zsub_hi |
| 18656 | 0, // zsub2_then_bsub |
| 18657 | 0, // zsub2_then_dsub |
| 18658 | 0, // zsub2_then_hsub |
| 18659 | 0, // zsub2_then_ssub |
| 18660 | 0, // zsub2_then_zsub |
| 18661 | 0, // zsub2_then_zsub_hi |
| 18662 | 0, // dsub0_dsub1 |
| 18663 | 0, // dsub0_dsub1_dsub2 |
| 18664 | 0, // dsub1_dsub2 |
| 18665 | 0, // dsub1_dsub2_dsub3 |
| 18666 | 0, // dsub2_dsub3 |
| 18667 | 0, // dsub_qsub1_then_dsub |
| 18668 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18669 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18670 | 0, // qsub0_qsub1 |
| 18671 | 0, // qsub0_qsub1_qsub2 |
| 18672 | 0, // qsub1_qsub2 |
| 18673 | 0, // qsub1_qsub2_qsub3 |
| 18674 | 0, // qsub2_qsub3 |
| 18675 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18676 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18677 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18678 | 44, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18679 | 44, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18680 | 44, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18681 | 44, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18682 | 44, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18683 | 44, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18684 | 44, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18685 | 44, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 18686 | 0, // sub_32_subo64_then_sub_32 |
| 18687 | 0, // dsub_zsub1_then_dsub |
| 18688 | 0, // zsub_zsub1_then_zsub |
| 18689 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18690 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18691 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18692 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18693 | 0, // zsub0_zsub1 |
| 18694 | 0, // zsub0_zsub1_zsub2 |
| 18695 | 0, // zsub1_zsub2 |
| 18696 | 0, // zsub1_zsub2_zsub3 |
| 18697 | 0, // zsub2_zsub3 |
| 18698 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18699 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18700 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18701 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18702 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18703 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18704 | }, |
| 18705 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18706 | 0, // bsub |
| 18707 | 0, // dsub |
| 18708 | 0, // dsub0 |
| 18709 | 0, // dsub1 |
| 18710 | 0, // dsub2 |
| 18711 | 0, // dsub3 |
| 18712 | 0, // hsub |
| 18713 | 0, // qhisub |
| 18714 | 0, // qsub |
| 18715 | 0, // qsub0 |
| 18716 | 0, // qsub1 |
| 18717 | 0, // qsub2 |
| 18718 | 0, // qsub3 |
| 18719 | 0, // ssub |
| 18720 | 45, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18721 | 0, // sube32 |
| 18722 | 0, // sube64 |
| 18723 | 0, // subo32 |
| 18724 | 0, // subo64 |
| 18725 | 45, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18726 | 45, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18727 | 45, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18728 | 45, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18729 | 45, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18730 | 45, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18731 | 45, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18732 | 45, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18733 | 0, // zsub |
| 18734 | 0, // zsub0 |
| 18735 | 0, // zsub1 |
| 18736 | 0, // zsub2 |
| 18737 | 0, // zsub3 |
| 18738 | 0, // zsub_hi |
| 18739 | 0, // dsub1_then_bsub |
| 18740 | 0, // dsub1_then_hsub |
| 18741 | 0, // dsub1_then_ssub |
| 18742 | 0, // dsub3_then_bsub |
| 18743 | 0, // dsub3_then_hsub |
| 18744 | 0, // dsub3_then_ssub |
| 18745 | 0, // dsub2_then_bsub |
| 18746 | 0, // dsub2_then_hsub |
| 18747 | 0, // dsub2_then_ssub |
| 18748 | 0, // qsub1_then_bsub |
| 18749 | 0, // qsub1_then_dsub |
| 18750 | 0, // qsub1_then_hsub |
| 18751 | 0, // qsub1_then_ssub |
| 18752 | 0, // qsub3_then_bsub |
| 18753 | 0, // qsub3_then_dsub |
| 18754 | 0, // qsub3_then_hsub |
| 18755 | 0, // qsub3_then_ssub |
| 18756 | 0, // qsub2_then_bsub |
| 18757 | 0, // qsub2_then_dsub |
| 18758 | 0, // qsub2_then_hsub |
| 18759 | 0, // qsub2_then_ssub |
| 18760 | 45, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18761 | 45, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18762 | 45, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18763 | 45, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18764 | 45, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18765 | 45, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18766 | 45, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18767 | 0, // subo64_then_sub_32 |
| 18768 | 0, // zsub1_then_bsub |
| 18769 | 0, // zsub1_then_dsub |
| 18770 | 0, // zsub1_then_hsub |
| 18771 | 0, // zsub1_then_ssub |
| 18772 | 0, // zsub1_then_zsub |
| 18773 | 0, // zsub1_then_zsub_hi |
| 18774 | 0, // zsub3_then_bsub |
| 18775 | 0, // zsub3_then_dsub |
| 18776 | 0, // zsub3_then_hsub |
| 18777 | 0, // zsub3_then_ssub |
| 18778 | 0, // zsub3_then_zsub |
| 18779 | 0, // zsub3_then_zsub_hi |
| 18780 | 0, // zsub2_then_bsub |
| 18781 | 0, // zsub2_then_dsub |
| 18782 | 0, // zsub2_then_hsub |
| 18783 | 0, // zsub2_then_ssub |
| 18784 | 0, // zsub2_then_zsub |
| 18785 | 0, // zsub2_then_zsub_hi |
| 18786 | 0, // dsub0_dsub1 |
| 18787 | 0, // dsub0_dsub1_dsub2 |
| 18788 | 0, // dsub1_dsub2 |
| 18789 | 0, // dsub1_dsub2_dsub3 |
| 18790 | 0, // dsub2_dsub3 |
| 18791 | 0, // dsub_qsub1_then_dsub |
| 18792 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18793 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18794 | 0, // qsub0_qsub1 |
| 18795 | 0, // qsub0_qsub1_qsub2 |
| 18796 | 0, // qsub1_qsub2 |
| 18797 | 0, // qsub1_qsub2_qsub3 |
| 18798 | 0, // qsub2_qsub3 |
| 18799 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18800 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18801 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18802 | 45, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18803 | 45, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18804 | 45, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18805 | 45, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18806 | 45, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18807 | 45, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18808 | 45, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18809 | 45, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 18810 | 0, // sub_32_subo64_then_sub_32 |
| 18811 | 0, // dsub_zsub1_then_dsub |
| 18812 | 0, // zsub_zsub1_then_zsub |
| 18813 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18814 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18815 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18816 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18817 | 0, // zsub0_zsub1 |
| 18818 | 0, // zsub0_zsub1_zsub2 |
| 18819 | 0, // zsub1_zsub2 |
| 18820 | 0, // zsub1_zsub2_zsub3 |
| 18821 | 0, // zsub2_zsub3 |
| 18822 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18823 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18824 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18825 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18826 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18827 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18828 | }, |
| 18829 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18830 | 0, // bsub |
| 18831 | 0, // dsub |
| 18832 | 0, // dsub0 |
| 18833 | 0, // dsub1 |
| 18834 | 0, // dsub2 |
| 18835 | 0, // dsub3 |
| 18836 | 0, // hsub |
| 18837 | 0, // qhisub |
| 18838 | 0, // qsub |
| 18839 | 0, // qsub0 |
| 18840 | 0, // qsub1 |
| 18841 | 0, // qsub2 |
| 18842 | 0, // qsub3 |
| 18843 | 0, // ssub |
| 18844 | 46, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18845 | 0, // sube32 |
| 18846 | 0, // sube64 |
| 18847 | 0, // subo32 |
| 18848 | 0, // subo64 |
| 18849 | 46, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18850 | 46, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18851 | 46, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18852 | 46, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18853 | 46, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18854 | 46, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18855 | 46, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18856 | 46, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18857 | 0, // zsub |
| 18858 | 0, // zsub0 |
| 18859 | 0, // zsub1 |
| 18860 | 0, // zsub2 |
| 18861 | 0, // zsub3 |
| 18862 | 0, // zsub_hi |
| 18863 | 0, // dsub1_then_bsub |
| 18864 | 0, // dsub1_then_hsub |
| 18865 | 0, // dsub1_then_ssub |
| 18866 | 0, // dsub3_then_bsub |
| 18867 | 0, // dsub3_then_hsub |
| 18868 | 0, // dsub3_then_ssub |
| 18869 | 0, // dsub2_then_bsub |
| 18870 | 0, // dsub2_then_hsub |
| 18871 | 0, // dsub2_then_ssub |
| 18872 | 0, // qsub1_then_bsub |
| 18873 | 0, // qsub1_then_dsub |
| 18874 | 0, // qsub1_then_hsub |
| 18875 | 0, // qsub1_then_ssub |
| 18876 | 0, // qsub3_then_bsub |
| 18877 | 0, // qsub3_then_dsub |
| 18878 | 0, // qsub3_then_hsub |
| 18879 | 0, // qsub3_then_ssub |
| 18880 | 0, // qsub2_then_bsub |
| 18881 | 0, // qsub2_then_dsub |
| 18882 | 0, // qsub2_then_hsub |
| 18883 | 0, // qsub2_then_ssub |
| 18884 | 46, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18885 | 46, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18886 | 46, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18887 | 46, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18888 | 46, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18889 | 46, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18890 | 46, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18891 | 0, // subo64_then_sub_32 |
| 18892 | 0, // zsub1_then_bsub |
| 18893 | 0, // zsub1_then_dsub |
| 18894 | 0, // zsub1_then_hsub |
| 18895 | 0, // zsub1_then_ssub |
| 18896 | 0, // zsub1_then_zsub |
| 18897 | 0, // zsub1_then_zsub_hi |
| 18898 | 0, // zsub3_then_bsub |
| 18899 | 0, // zsub3_then_dsub |
| 18900 | 0, // zsub3_then_hsub |
| 18901 | 0, // zsub3_then_ssub |
| 18902 | 0, // zsub3_then_zsub |
| 18903 | 0, // zsub3_then_zsub_hi |
| 18904 | 0, // zsub2_then_bsub |
| 18905 | 0, // zsub2_then_dsub |
| 18906 | 0, // zsub2_then_hsub |
| 18907 | 0, // zsub2_then_ssub |
| 18908 | 0, // zsub2_then_zsub |
| 18909 | 0, // zsub2_then_zsub_hi |
| 18910 | 0, // dsub0_dsub1 |
| 18911 | 0, // dsub0_dsub1_dsub2 |
| 18912 | 0, // dsub1_dsub2 |
| 18913 | 0, // dsub1_dsub2_dsub3 |
| 18914 | 0, // dsub2_dsub3 |
| 18915 | 0, // dsub_qsub1_then_dsub |
| 18916 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18917 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 18918 | 0, // qsub0_qsub1 |
| 18919 | 0, // qsub0_qsub1_qsub2 |
| 18920 | 0, // qsub1_qsub2 |
| 18921 | 0, // qsub1_qsub2_qsub3 |
| 18922 | 0, // qsub2_qsub3 |
| 18923 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 18924 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 18925 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 18926 | 46, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18927 | 46, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18928 | 46, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18929 | 46, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18930 | 46, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18931 | 46, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18932 | 46, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18933 | 46, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18934 | 0, // sub_32_subo64_then_sub_32 |
| 18935 | 0, // dsub_zsub1_then_dsub |
| 18936 | 0, // zsub_zsub1_then_zsub |
| 18937 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18938 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 18939 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18940 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 18941 | 0, // zsub0_zsub1 |
| 18942 | 0, // zsub0_zsub1_zsub2 |
| 18943 | 0, // zsub1_zsub2 |
| 18944 | 0, // zsub1_zsub2_zsub3 |
| 18945 | 0, // zsub2_zsub3 |
| 18946 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 18947 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 18948 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 18949 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 18950 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 18951 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 18952 | }, |
| 18953 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18954 | 0, // bsub |
| 18955 | 0, // dsub |
| 18956 | 0, // dsub0 |
| 18957 | 0, // dsub1 |
| 18958 | 0, // dsub2 |
| 18959 | 0, // dsub3 |
| 18960 | 0, // hsub |
| 18961 | 0, // qhisub |
| 18962 | 0, // qsub |
| 18963 | 0, // qsub0 |
| 18964 | 0, // qsub1 |
| 18965 | 0, // qsub2 |
| 18966 | 0, // qsub3 |
| 18967 | 0, // ssub |
| 18968 | 47, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18969 | 0, // sube32 |
| 18970 | 0, // sube64 |
| 18971 | 0, // subo32 |
| 18972 | 0, // subo64 |
| 18973 | 47, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18974 | 47, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18975 | 47, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18976 | 47, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18977 | 47, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18978 | 47, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18979 | 47, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18980 | 47, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 18981 | 0, // zsub |
| 18982 | 0, // zsub0 |
| 18983 | 0, // zsub1 |
| 18984 | 0, // zsub2 |
| 18985 | 0, // zsub3 |
| 18986 | 0, // zsub_hi |
| 18987 | 0, // dsub1_then_bsub |
| 18988 | 0, // dsub1_then_hsub |
| 18989 | 0, // dsub1_then_ssub |
| 18990 | 0, // dsub3_then_bsub |
| 18991 | 0, // dsub3_then_hsub |
| 18992 | 0, // dsub3_then_ssub |
| 18993 | 0, // dsub2_then_bsub |
| 18994 | 0, // dsub2_then_hsub |
| 18995 | 0, // dsub2_then_ssub |
| 18996 | 0, // qsub1_then_bsub |
| 18997 | 0, // qsub1_then_dsub |
| 18998 | 0, // qsub1_then_hsub |
| 18999 | 0, // qsub1_then_ssub |
| 19000 | 0, // qsub3_then_bsub |
| 19001 | 0, // qsub3_then_dsub |
| 19002 | 0, // qsub3_then_hsub |
| 19003 | 0, // qsub3_then_ssub |
| 19004 | 0, // qsub2_then_bsub |
| 19005 | 0, // qsub2_then_dsub |
| 19006 | 0, // qsub2_then_hsub |
| 19007 | 0, // qsub2_then_ssub |
| 19008 | 47, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19009 | 47, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19010 | 47, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19011 | 47, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19012 | 47, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19013 | 47, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19014 | 47, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19015 | 0, // subo64_then_sub_32 |
| 19016 | 0, // zsub1_then_bsub |
| 19017 | 0, // zsub1_then_dsub |
| 19018 | 0, // zsub1_then_hsub |
| 19019 | 0, // zsub1_then_ssub |
| 19020 | 0, // zsub1_then_zsub |
| 19021 | 0, // zsub1_then_zsub_hi |
| 19022 | 0, // zsub3_then_bsub |
| 19023 | 0, // zsub3_then_dsub |
| 19024 | 0, // zsub3_then_hsub |
| 19025 | 0, // zsub3_then_ssub |
| 19026 | 0, // zsub3_then_zsub |
| 19027 | 0, // zsub3_then_zsub_hi |
| 19028 | 0, // zsub2_then_bsub |
| 19029 | 0, // zsub2_then_dsub |
| 19030 | 0, // zsub2_then_hsub |
| 19031 | 0, // zsub2_then_ssub |
| 19032 | 0, // zsub2_then_zsub |
| 19033 | 0, // zsub2_then_zsub_hi |
| 19034 | 0, // dsub0_dsub1 |
| 19035 | 0, // dsub0_dsub1_dsub2 |
| 19036 | 0, // dsub1_dsub2 |
| 19037 | 0, // dsub1_dsub2_dsub3 |
| 19038 | 0, // dsub2_dsub3 |
| 19039 | 0, // dsub_qsub1_then_dsub |
| 19040 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19041 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19042 | 0, // qsub0_qsub1 |
| 19043 | 0, // qsub0_qsub1_qsub2 |
| 19044 | 0, // qsub1_qsub2 |
| 19045 | 0, // qsub1_qsub2_qsub3 |
| 19046 | 0, // qsub2_qsub3 |
| 19047 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19048 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19049 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19050 | 47, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19051 | 47, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19052 | 47, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19053 | 47, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19054 | 47, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19055 | 47, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19056 | 47, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19057 | 47, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19058 | 0, // sub_32_subo64_then_sub_32 |
| 19059 | 0, // dsub_zsub1_then_dsub |
| 19060 | 0, // zsub_zsub1_then_zsub |
| 19061 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19062 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19063 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19064 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19065 | 0, // zsub0_zsub1 |
| 19066 | 0, // zsub0_zsub1_zsub2 |
| 19067 | 0, // zsub1_zsub2 |
| 19068 | 0, // zsub1_zsub2_zsub3 |
| 19069 | 0, // zsub2_zsub3 |
| 19070 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19071 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19072 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19073 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19074 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19075 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19076 | }, |
| 19077 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19078 | 0, // bsub |
| 19079 | 0, // dsub |
| 19080 | 0, // dsub0 |
| 19081 | 0, // dsub1 |
| 19082 | 0, // dsub2 |
| 19083 | 0, // dsub3 |
| 19084 | 0, // hsub |
| 19085 | 0, // qhisub |
| 19086 | 0, // qsub |
| 19087 | 0, // qsub0 |
| 19088 | 0, // qsub1 |
| 19089 | 0, // qsub2 |
| 19090 | 0, // qsub3 |
| 19091 | 0, // ssub |
| 19092 | 48, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19093 | 0, // sube32 |
| 19094 | 0, // sube64 |
| 19095 | 0, // subo32 |
| 19096 | 0, // subo64 |
| 19097 | 48, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19098 | 48, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19099 | 48, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19100 | 48, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19101 | 48, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19102 | 48, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19103 | 48, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19104 | 48, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19105 | 0, // zsub |
| 19106 | 0, // zsub0 |
| 19107 | 0, // zsub1 |
| 19108 | 0, // zsub2 |
| 19109 | 0, // zsub3 |
| 19110 | 0, // zsub_hi |
| 19111 | 0, // dsub1_then_bsub |
| 19112 | 0, // dsub1_then_hsub |
| 19113 | 0, // dsub1_then_ssub |
| 19114 | 0, // dsub3_then_bsub |
| 19115 | 0, // dsub3_then_hsub |
| 19116 | 0, // dsub3_then_ssub |
| 19117 | 0, // dsub2_then_bsub |
| 19118 | 0, // dsub2_then_hsub |
| 19119 | 0, // dsub2_then_ssub |
| 19120 | 0, // qsub1_then_bsub |
| 19121 | 0, // qsub1_then_dsub |
| 19122 | 0, // qsub1_then_hsub |
| 19123 | 0, // qsub1_then_ssub |
| 19124 | 0, // qsub3_then_bsub |
| 19125 | 0, // qsub3_then_dsub |
| 19126 | 0, // qsub3_then_hsub |
| 19127 | 0, // qsub3_then_ssub |
| 19128 | 0, // qsub2_then_bsub |
| 19129 | 0, // qsub2_then_dsub |
| 19130 | 0, // qsub2_then_hsub |
| 19131 | 0, // qsub2_then_ssub |
| 19132 | 48, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19133 | 48, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19134 | 48, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19135 | 48, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19136 | 48, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19137 | 48, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19138 | 48, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19139 | 0, // subo64_then_sub_32 |
| 19140 | 0, // zsub1_then_bsub |
| 19141 | 0, // zsub1_then_dsub |
| 19142 | 0, // zsub1_then_hsub |
| 19143 | 0, // zsub1_then_ssub |
| 19144 | 0, // zsub1_then_zsub |
| 19145 | 0, // zsub1_then_zsub_hi |
| 19146 | 0, // zsub3_then_bsub |
| 19147 | 0, // zsub3_then_dsub |
| 19148 | 0, // zsub3_then_hsub |
| 19149 | 0, // zsub3_then_ssub |
| 19150 | 0, // zsub3_then_zsub |
| 19151 | 0, // zsub3_then_zsub_hi |
| 19152 | 0, // zsub2_then_bsub |
| 19153 | 0, // zsub2_then_dsub |
| 19154 | 0, // zsub2_then_hsub |
| 19155 | 0, // zsub2_then_ssub |
| 19156 | 0, // zsub2_then_zsub |
| 19157 | 0, // zsub2_then_zsub_hi |
| 19158 | 0, // dsub0_dsub1 |
| 19159 | 0, // dsub0_dsub1_dsub2 |
| 19160 | 0, // dsub1_dsub2 |
| 19161 | 0, // dsub1_dsub2_dsub3 |
| 19162 | 0, // dsub2_dsub3 |
| 19163 | 0, // dsub_qsub1_then_dsub |
| 19164 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19165 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19166 | 0, // qsub0_qsub1 |
| 19167 | 0, // qsub0_qsub1_qsub2 |
| 19168 | 0, // qsub1_qsub2 |
| 19169 | 0, // qsub1_qsub2_qsub3 |
| 19170 | 0, // qsub2_qsub3 |
| 19171 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19172 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19173 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19174 | 48, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19175 | 48, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19176 | 48, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19177 | 48, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19178 | 48, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19179 | 48, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19180 | 48, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19181 | 48, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19182 | 0, // sub_32_subo64_then_sub_32 |
| 19183 | 0, // dsub_zsub1_then_dsub |
| 19184 | 0, // zsub_zsub1_then_zsub |
| 19185 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19186 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19187 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19188 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19189 | 0, // zsub0_zsub1 |
| 19190 | 0, // zsub0_zsub1_zsub2 |
| 19191 | 0, // zsub1_zsub2 |
| 19192 | 0, // zsub1_zsub2_zsub3 |
| 19193 | 0, // zsub2_zsub3 |
| 19194 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19195 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19196 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19197 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19198 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19199 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19200 | }, |
| 19201 | { // GPR64arg |
| 19202 | 0, // bsub |
| 19203 | 0, // dsub |
| 19204 | 0, // dsub0 |
| 19205 | 0, // dsub1 |
| 19206 | 0, // dsub2 |
| 19207 | 0, // dsub3 |
| 19208 | 0, // hsub |
| 19209 | 0, // qhisub |
| 19210 | 0, // qsub |
| 19211 | 0, // qsub0 |
| 19212 | 0, // qsub1 |
| 19213 | 0, // qsub2 |
| 19214 | 0, // qsub3 |
| 19215 | 0, // ssub |
| 19216 | 49, // sub_32 -> GPR64arg |
| 19217 | 0, // sube32 |
| 19218 | 0, // sube64 |
| 19219 | 0, // subo32 |
| 19220 | 0, // subo64 |
| 19221 | 0, // x8sub_0 |
| 19222 | 0, // x8sub_1 |
| 19223 | 0, // x8sub_2 |
| 19224 | 0, // x8sub_3 |
| 19225 | 0, // x8sub_4 |
| 19226 | 0, // x8sub_5 |
| 19227 | 0, // x8sub_6 |
| 19228 | 0, // x8sub_7 |
| 19229 | 0, // zsub |
| 19230 | 0, // zsub0 |
| 19231 | 0, // zsub1 |
| 19232 | 0, // zsub2 |
| 19233 | 0, // zsub3 |
| 19234 | 0, // zsub_hi |
| 19235 | 0, // dsub1_then_bsub |
| 19236 | 0, // dsub1_then_hsub |
| 19237 | 0, // dsub1_then_ssub |
| 19238 | 0, // dsub3_then_bsub |
| 19239 | 0, // dsub3_then_hsub |
| 19240 | 0, // dsub3_then_ssub |
| 19241 | 0, // dsub2_then_bsub |
| 19242 | 0, // dsub2_then_hsub |
| 19243 | 0, // dsub2_then_ssub |
| 19244 | 0, // qsub1_then_bsub |
| 19245 | 0, // qsub1_then_dsub |
| 19246 | 0, // qsub1_then_hsub |
| 19247 | 0, // qsub1_then_ssub |
| 19248 | 0, // qsub3_then_bsub |
| 19249 | 0, // qsub3_then_dsub |
| 19250 | 0, // qsub3_then_hsub |
| 19251 | 0, // qsub3_then_ssub |
| 19252 | 0, // qsub2_then_bsub |
| 19253 | 0, // qsub2_then_dsub |
| 19254 | 0, // qsub2_then_hsub |
| 19255 | 0, // qsub2_then_ssub |
| 19256 | 0, // x8sub_7_then_sub_32 |
| 19257 | 0, // x8sub_6_then_sub_32 |
| 19258 | 0, // x8sub_5_then_sub_32 |
| 19259 | 0, // x8sub_4_then_sub_32 |
| 19260 | 0, // x8sub_3_then_sub_32 |
| 19261 | 0, // x8sub_2_then_sub_32 |
| 19262 | 0, // x8sub_1_then_sub_32 |
| 19263 | 0, // subo64_then_sub_32 |
| 19264 | 0, // zsub1_then_bsub |
| 19265 | 0, // zsub1_then_dsub |
| 19266 | 0, // zsub1_then_hsub |
| 19267 | 0, // zsub1_then_ssub |
| 19268 | 0, // zsub1_then_zsub |
| 19269 | 0, // zsub1_then_zsub_hi |
| 19270 | 0, // zsub3_then_bsub |
| 19271 | 0, // zsub3_then_dsub |
| 19272 | 0, // zsub3_then_hsub |
| 19273 | 0, // zsub3_then_ssub |
| 19274 | 0, // zsub3_then_zsub |
| 19275 | 0, // zsub3_then_zsub_hi |
| 19276 | 0, // zsub2_then_bsub |
| 19277 | 0, // zsub2_then_dsub |
| 19278 | 0, // zsub2_then_hsub |
| 19279 | 0, // zsub2_then_ssub |
| 19280 | 0, // zsub2_then_zsub |
| 19281 | 0, // zsub2_then_zsub_hi |
| 19282 | 0, // dsub0_dsub1 |
| 19283 | 0, // dsub0_dsub1_dsub2 |
| 19284 | 0, // dsub1_dsub2 |
| 19285 | 0, // dsub1_dsub2_dsub3 |
| 19286 | 0, // dsub2_dsub3 |
| 19287 | 0, // dsub_qsub1_then_dsub |
| 19288 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19289 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19290 | 0, // qsub0_qsub1 |
| 19291 | 0, // qsub0_qsub1_qsub2 |
| 19292 | 0, // qsub1_qsub2 |
| 19293 | 0, // qsub1_qsub2_qsub3 |
| 19294 | 0, // qsub2_qsub3 |
| 19295 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19296 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19297 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19298 | 0, // sub_32_x8sub_1_then_sub_32 |
| 19299 | 0, // x8sub_0_x8sub_1 |
| 19300 | 0, // x8sub_2_x8sub_3 |
| 19301 | 0, // x8sub_4_x8sub_5 |
| 19302 | 0, // x8sub_6_x8sub_7 |
| 19303 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 19304 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 19305 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 19306 | 0, // sub_32_subo64_then_sub_32 |
| 19307 | 0, // dsub_zsub1_then_dsub |
| 19308 | 0, // zsub_zsub1_then_zsub |
| 19309 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19310 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19311 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19312 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19313 | 0, // zsub0_zsub1 |
| 19314 | 0, // zsub0_zsub1_zsub2 |
| 19315 | 0, // zsub1_zsub2 |
| 19316 | 0, // zsub1_zsub2_zsub3 |
| 19317 | 0, // zsub2_zsub3 |
| 19318 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19319 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19320 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19321 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19322 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19323 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19324 | }, |
| 19325 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19326 | 0, // bsub |
| 19327 | 0, // dsub |
| 19328 | 0, // dsub0 |
| 19329 | 0, // dsub1 |
| 19330 | 0, // dsub2 |
| 19331 | 0, // dsub3 |
| 19332 | 0, // hsub |
| 19333 | 0, // qhisub |
| 19334 | 0, // qsub |
| 19335 | 0, // qsub0 |
| 19336 | 0, // qsub1 |
| 19337 | 0, // qsub2 |
| 19338 | 0, // qsub3 |
| 19339 | 0, // ssub |
| 19340 | 50, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19341 | 0, // sube32 |
| 19342 | 0, // sube64 |
| 19343 | 0, // subo32 |
| 19344 | 0, // subo64 |
| 19345 | 50, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19346 | 50, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19347 | 50, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19348 | 50, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19349 | 50, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19350 | 50, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19351 | 50, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19352 | 50, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19353 | 0, // zsub |
| 19354 | 0, // zsub0 |
| 19355 | 0, // zsub1 |
| 19356 | 0, // zsub2 |
| 19357 | 0, // zsub3 |
| 19358 | 0, // zsub_hi |
| 19359 | 0, // dsub1_then_bsub |
| 19360 | 0, // dsub1_then_hsub |
| 19361 | 0, // dsub1_then_ssub |
| 19362 | 0, // dsub3_then_bsub |
| 19363 | 0, // dsub3_then_hsub |
| 19364 | 0, // dsub3_then_ssub |
| 19365 | 0, // dsub2_then_bsub |
| 19366 | 0, // dsub2_then_hsub |
| 19367 | 0, // dsub2_then_ssub |
| 19368 | 0, // qsub1_then_bsub |
| 19369 | 0, // qsub1_then_dsub |
| 19370 | 0, // qsub1_then_hsub |
| 19371 | 0, // qsub1_then_ssub |
| 19372 | 0, // qsub3_then_bsub |
| 19373 | 0, // qsub3_then_dsub |
| 19374 | 0, // qsub3_then_hsub |
| 19375 | 0, // qsub3_then_ssub |
| 19376 | 0, // qsub2_then_bsub |
| 19377 | 0, // qsub2_then_dsub |
| 19378 | 0, // qsub2_then_hsub |
| 19379 | 0, // qsub2_then_ssub |
| 19380 | 50, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19381 | 50, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19382 | 50, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19383 | 50, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19384 | 50, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19385 | 50, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19386 | 50, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19387 | 0, // subo64_then_sub_32 |
| 19388 | 0, // zsub1_then_bsub |
| 19389 | 0, // zsub1_then_dsub |
| 19390 | 0, // zsub1_then_hsub |
| 19391 | 0, // zsub1_then_ssub |
| 19392 | 0, // zsub1_then_zsub |
| 19393 | 0, // zsub1_then_zsub_hi |
| 19394 | 0, // zsub3_then_bsub |
| 19395 | 0, // zsub3_then_dsub |
| 19396 | 0, // zsub3_then_hsub |
| 19397 | 0, // zsub3_then_ssub |
| 19398 | 0, // zsub3_then_zsub |
| 19399 | 0, // zsub3_then_zsub_hi |
| 19400 | 0, // zsub2_then_bsub |
| 19401 | 0, // zsub2_then_dsub |
| 19402 | 0, // zsub2_then_hsub |
| 19403 | 0, // zsub2_then_ssub |
| 19404 | 0, // zsub2_then_zsub |
| 19405 | 0, // zsub2_then_zsub_hi |
| 19406 | 0, // dsub0_dsub1 |
| 19407 | 0, // dsub0_dsub1_dsub2 |
| 19408 | 0, // dsub1_dsub2 |
| 19409 | 0, // dsub1_dsub2_dsub3 |
| 19410 | 0, // dsub2_dsub3 |
| 19411 | 0, // dsub_qsub1_then_dsub |
| 19412 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19413 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19414 | 0, // qsub0_qsub1 |
| 19415 | 0, // qsub0_qsub1_qsub2 |
| 19416 | 0, // qsub1_qsub2 |
| 19417 | 0, // qsub1_qsub2_qsub3 |
| 19418 | 0, // qsub2_qsub3 |
| 19419 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19420 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19421 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19422 | 50, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19423 | 50, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19424 | 50, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19425 | 50, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19426 | 50, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19427 | 50, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19428 | 50, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19429 | 50, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 19430 | 0, // sub_32_subo64_then_sub_32 |
| 19431 | 0, // dsub_zsub1_then_dsub |
| 19432 | 0, // zsub_zsub1_then_zsub |
| 19433 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19434 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19435 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19436 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19437 | 0, // zsub0_zsub1 |
| 19438 | 0, // zsub0_zsub1_zsub2 |
| 19439 | 0, // zsub1_zsub2 |
| 19440 | 0, // zsub1_zsub2_zsub3 |
| 19441 | 0, // zsub2_zsub3 |
| 19442 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19443 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19444 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19445 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19446 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19447 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19448 | }, |
| 19449 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19450 | 0, // bsub |
| 19451 | 0, // dsub |
| 19452 | 0, // dsub0 |
| 19453 | 0, // dsub1 |
| 19454 | 0, // dsub2 |
| 19455 | 0, // dsub3 |
| 19456 | 0, // hsub |
| 19457 | 0, // qhisub |
| 19458 | 0, // qsub |
| 19459 | 0, // qsub0 |
| 19460 | 0, // qsub1 |
| 19461 | 0, // qsub2 |
| 19462 | 0, // qsub3 |
| 19463 | 0, // ssub |
| 19464 | 51, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19465 | 0, // sube32 |
| 19466 | 0, // sube64 |
| 19467 | 0, // subo32 |
| 19468 | 0, // subo64 |
| 19469 | 51, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19470 | 51, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19471 | 51, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19472 | 51, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19473 | 51, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19474 | 51, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19475 | 51, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19476 | 51, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19477 | 0, // zsub |
| 19478 | 0, // zsub0 |
| 19479 | 0, // zsub1 |
| 19480 | 0, // zsub2 |
| 19481 | 0, // zsub3 |
| 19482 | 0, // zsub_hi |
| 19483 | 0, // dsub1_then_bsub |
| 19484 | 0, // dsub1_then_hsub |
| 19485 | 0, // dsub1_then_ssub |
| 19486 | 0, // dsub3_then_bsub |
| 19487 | 0, // dsub3_then_hsub |
| 19488 | 0, // dsub3_then_ssub |
| 19489 | 0, // dsub2_then_bsub |
| 19490 | 0, // dsub2_then_hsub |
| 19491 | 0, // dsub2_then_ssub |
| 19492 | 0, // qsub1_then_bsub |
| 19493 | 0, // qsub1_then_dsub |
| 19494 | 0, // qsub1_then_hsub |
| 19495 | 0, // qsub1_then_ssub |
| 19496 | 0, // qsub3_then_bsub |
| 19497 | 0, // qsub3_then_dsub |
| 19498 | 0, // qsub3_then_hsub |
| 19499 | 0, // qsub3_then_ssub |
| 19500 | 0, // qsub2_then_bsub |
| 19501 | 0, // qsub2_then_dsub |
| 19502 | 0, // qsub2_then_hsub |
| 19503 | 0, // qsub2_then_ssub |
| 19504 | 51, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19505 | 51, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19506 | 51, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19507 | 51, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19508 | 51, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19509 | 51, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19510 | 51, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19511 | 0, // subo64_then_sub_32 |
| 19512 | 0, // zsub1_then_bsub |
| 19513 | 0, // zsub1_then_dsub |
| 19514 | 0, // zsub1_then_hsub |
| 19515 | 0, // zsub1_then_ssub |
| 19516 | 0, // zsub1_then_zsub |
| 19517 | 0, // zsub1_then_zsub_hi |
| 19518 | 0, // zsub3_then_bsub |
| 19519 | 0, // zsub3_then_dsub |
| 19520 | 0, // zsub3_then_hsub |
| 19521 | 0, // zsub3_then_ssub |
| 19522 | 0, // zsub3_then_zsub |
| 19523 | 0, // zsub3_then_zsub_hi |
| 19524 | 0, // zsub2_then_bsub |
| 19525 | 0, // zsub2_then_dsub |
| 19526 | 0, // zsub2_then_hsub |
| 19527 | 0, // zsub2_then_ssub |
| 19528 | 0, // zsub2_then_zsub |
| 19529 | 0, // zsub2_then_zsub_hi |
| 19530 | 0, // dsub0_dsub1 |
| 19531 | 0, // dsub0_dsub1_dsub2 |
| 19532 | 0, // dsub1_dsub2 |
| 19533 | 0, // dsub1_dsub2_dsub3 |
| 19534 | 0, // dsub2_dsub3 |
| 19535 | 0, // dsub_qsub1_then_dsub |
| 19536 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19537 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19538 | 0, // qsub0_qsub1 |
| 19539 | 0, // qsub0_qsub1_qsub2 |
| 19540 | 0, // qsub1_qsub2 |
| 19541 | 0, // qsub1_qsub2_qsub3 |
| 19542 | 0, // qsub2_qsub3 |
| 19543 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19544 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19545 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19546 | 51, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19547 | 51, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19548 | 51, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19549 | 51, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19550 | 51, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19551 | 51, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19552 | 51, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19553 | 51, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19554 | 0, // sub_32_subo64_then_sub_32 |
| 19555 | 0, // dsub_zsub1_then_dsub |
| 19556 | 0, // zsub_zsub1_then_zsub |
| 19557 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19558 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19559 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19560 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19561 | 0, // zsub0_zsub1 |
| 19562 | 0, // zsub0_zsub1_zsub2 |
| 19563 | 0, // zsub1_zsub2 |
| 19564 | 0, // zsub1_zsub2_zsub3 |
| 19565 | 0, // zsub2_zsub3 |
| 19566 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19567 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19568 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19569 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19570 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19571 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19572 | }, |
| 19573 | { // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19574 | 0, // bsub |
| 19575 | 0, // dsub |
| 19576 | 0, // dsub0 |
| 19577 | 0, // dsub1 |
| 19578 | 0, // dsub2 |
| 19579 | 0, // dsub3 |
| 19580 | 0, // hsub |
| 19581 | 0, // qhisub |
| 19582 | 0, // qsub |
| 19583 | 0, // qsub0 |
| 19584 | 0, // qsub1 |
| 19585 | 0, // qsub2 |
| 19586 | 0, // qsub3 |
| 19587 | 0, // ssub |
| 19588 | 52, // sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19589 | 0, // sube32 |
| 19590 | 0, // sube64 |
| 19591 | 0, // subo32 |
| 19592 | 0, // subo64 |
| 19593 | 52, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19594 | 52, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19595 | 52, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19596 | 52, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19597 | 52, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19598 | 52, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19599 | 52, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19600 | 52, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19601 | 0, // zsub |
| 19602 | 0, // zsub0 |
| 19603 | 0, // zsub1 |
| 19604 | 0, // zsub2 |
| 19605 | 0, // zsub3 |
| 19606 | 0, // zsub_hi |
| 19607 | 0, // dsub1_then_bsub |
| 19608 | 0, // dsub1_then_hsub |
| 19609 | 0, // dsub1_then_ssub |
| 19610 | 0, // dsub3_then_bsub |
| 19611 | 0, // dsub3_then_hsub |
| 19612 | 0, // dsub3_then_ssub |
| 19613 | 0, // dsub2_then_bsub |
| 19614 | 0, // dsub2_then_hsub |
| 19615 | 0, // dsub2_then_ssub |
| 19616 | 0, // qsub1_then_bsub |
| 19617 | 0, // qsub1_then_dsub |
| 19618 | 0, // qsub1_then_hsub |
| 19619 | 0, // qsub1_then_ssub |
| 19620 | 0, // qsub3_then_bsub |
| 19621 | 0, // qsub3_then_dsub |
| 19622 | 0, // qsub3_then_hsub |
| 19623 | 0, // qsub3_then_ssub |
| 19624 | 0, // qsub2_then_bsub |
| 19625 | 0, // qsub2_then_dsub |
| 19626 | 0, // qsub2_then_hsub |
| 19627 | 0, // qsub2_then_ssub |
| 19628 | 52, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19629 | 52, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19630 | 52, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19631 | 52, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19632 | 52, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19633 | 52, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19634 | 52, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19635 | 0, // subo64_then_sub_32 |
| 19636 | 0, // zsub1_then_bsub |
| 19637 | 0, // zsub1_then_dsub |
| 19638 | 0, // zsub1_then_hsub |
| 19639 | 0, // zsub1_then_ssub |
| 19640 | 0, // zsub1_then_zsub |
| 19641 | 0, // zsub1_then_zsub_hi |
| 19642 | 0, // zsub3_then_bsub |
| 19643 | 0, // zsub3_then_dsub |
| 19644 | 0, // zsub3_then_hsub |
| 19645 | 0, // zsub3_then_ssub |
| 19646 | 0, // zsub3_then_zsub |
| 19647 | 0, // zsub3_then_zsub_hi |
| 19648 | 0, // zsub2_then_bsub |
| 19649 | 0, // zsub2_then_dsub |
| 19650 | 0, // zsub2_then_hsub |
| 19651 | 0, // zsub2_then_ssub |
| 19652 | 0, // zsub2_then_zsub |
| 19653 | 0, // zsub2_then_zsub_hi |
| 19654 | 0, // dsub0_dsub1 |
| 19655 | 0, // dsub0_dsub1_dsub2 |
| 19656 | 0, // dsub1_dsub2 |
| 19657 | 0, // dsub1_dsub2_dsub3 |
| 19658 | 0, // dsub2_dsub3 |
| 19659 | 0, // dsub_qsub1_then_dsub |
| 19660 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19661 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19662 | 0, // qsub0_qsub1 |
| 19663 | 0, // qsub0_qsub1_qsub2 |
| 19664 | 0, // qsub1_qsub2 |
| 19665 | 0, // qsub1_qsub2_qsub3 |
| 19666 | 0, // qsub2_qsub3 |
| 19667 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19668 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19669 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19670 | 52, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19671 | 52, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19672 | 52, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19673 | 52, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19674 | 52, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19675 | 52, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19676 | 52, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19677 | 52, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19678 | 0, // sub_32_subo64_then_sub_32 |
| 19679 | 0, // dsub_zsub1_then_dsub |
| 19680 | 0, // zsub_zsub1_then_zsub |
| 19681 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19682 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19683 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19684 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19685 | 0, // zsub0_zsub1 |
| 19686 | 0, // zsub0_zsub1_zsub2 |
| 19687 | 0, // zsub1_zsub2 |
| 19688 | 0, // zsub1_zsub2_zsub3 |
| 19689 | 0, // zsub2_zsub3 |
| 19690 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19691 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19692 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19693 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19694 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19695 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19696 | }, |
| 19697 | { // GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19698 | 0, // bsub |
| 19699 | 0, // dsub |
| 19700 | 0, // dsub0 |
| 19701 | 0, // dsub1 |
| 19702 | 0, // dsub2 |
| 19703 | 0, // dsub3 |
| 19704 | 0, // hsub |
| 19705 | 0, // qhisub |
| 19706 | 0, // qsub |
| 19707 | 0, // qsub0 |
| 19708 | 0, // qsub1 |
| 19709 | 0, // qsub2 |
| 19710 | 0, // qsub3 |
| 19711 | 0, // ssub |
| 19712 | 53, // sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19713 | 0, // sube32 |
| 19714 | 0, // sube64 |
| 19715 | 0, // subo32 |
| 19716 | 0, // subo64 |
| 19717 | 53, // x8sub_0 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19718 | 53, // x8sub_1 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19719 | 53, // x8sub_2 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19720 | 53, // x8sub_3 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19721 | 53, // x8sub_4 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19722 | 53, // x8sub_5 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19723 | 53, // x8sub_6 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19724 | 53, // x8sub_7 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19725 | 0, // zsub |
| 19726 | 0, // zsub0 |
| 19727 | 0, // zsub1 |
| 19728 | 0, // zsub2 |
| 19729 | 0, // zsub3 |
| 19730 | 0, // zsub_hi |
| 19731 | 0, // dsub1_then_bsub |
| 19732 | 0, // dsub1_then_hsub |
| 19733 | 0, // dsub1_then_ssub |
| 19734 | 0, // dsub3_then_bsub |
| 19735 | 0, // dsub3_then_hsub |
| 19736 | 0, // dsub3_then_ssub |
| 19737 | 0, // dsub2_then_bsub |
| 19738 | 0, // dsub2_then_hsub |
| 19739 | 0, // dsub2_then_ssub |
| 19740 | 0, // qsub1_then_bsub |
| 19741 | 0, // qsub1_then_dsub |
| 19742 | 0, // qsub1_then_hsub |
| 19743 | 0, // qsub1_then_ssub |
| 19744 | 0, // qsub3_then_bsub |
| 19745 | 0, // qsub3_then_dsub |
| 19746 | 0, // qsub3_then_hsub |
| 19747 | 0, // qsub3_then_ssub |
| 19748 | 0, // qsub2_then_bsub |
| 19749 | 0, // qsub2_then_dsub |
| 19750 | 0, // qsub2_then_hsub |
| 19751 | 0, // qsub2_then_ssub |
| 19752 | 53, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19753 | 53, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19754 | 53, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19755 | 53, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19756 | 53, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19757 | 53, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19758 | 53, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19759 | 0, // subo64_then_sub_32 |
| 19760 | 0, // zsub1_then_bsub |
| 19761 | 0, // zsub1_then_dsub |
| 19762 | 0, // zsub1_then_hsub |
| 19763 | 0, // zsub1_then_ssub |
| 19764 | 0, // zsub1_then_zsub |
| 19765 | 0, // zsub1_then_zsub_hi |
| 19766 | 0, // zsub3_then_bsub |
| 19767 | 0, // zsub3_then_dsub |
| 19768 | 0, // zsub3_then_hsub |
| 19769 | 0, // zsub3_then_ssub |
| 19770 | 0, // zsub3_then_zsub |
| 19771 | 0, // zsub3_then_zsub_hi |
| 19772 | 0, // zsub2_then_bsub |
| 19773 | 0, // zsub2_then_dsub |
| 19774 | 0, // zsub2_then_hsub |
| 19775 | 0, // zsub2_then_ssub |
| 19776 | 0, // zsub2_then_zsub |
| 19777 | 0, // zsub2_then_zsub_hi |
| 19778 | 0, // dsub0_dsub1 |
| 19779 | 0, // dsub0_dsub1_dsub2 |
| 19780 | 0, // dsub1_dsub2 |
| 19781 | 0, // dsub1_dsub2_dsub3 |
| 19782 | 0, // dsub2_dsub3 |
| 19783 | 0, // dsub_qsub1_then_dsub |
| 19784 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19785 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19786 | 0, // qsub0_qsub1 |
| 19787 | 0, // qsub0_qsub1_qsub2 |
| 19788 | 0, // qsub1_qsub2 |
| 19789 | 0, // qsub1_qsub2_qsub3 |
| 19790 | 0, // qsub2_qsub3 |
| 19791 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19792 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19793 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19794 | 53, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19795 | 53, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19796 | 53, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19797 | 53, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19798 | 53, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19799 | 53, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19800 | 53, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19801 | 53, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 19802 | 0, // sub_32_subo64_then_sub_32 |
| 19803 | 0, // dsub_zsub1_then_dsub |
| 19804 | 0, // zsub_zsub1_then_zsub |
| 19805 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19806 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19807 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19808 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19809 | 0, // zsub0_zsub1 |
| 19810 | 0, // zsub0_zsub1_zsub2 |
| 19811 | 0, // zsub1_zsub2 |
| 19812 | 0, // zsub1_zsub2_zsub3 |
| 19813 | 0, // zsub2_zsub3 |
| 19814 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19815 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19816 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19817 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19818 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19819 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19820 | }, |
| 19821 | { // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19822 | 0, // bsub |
| 19823 | 0, // dsub |
| 19824 | 0, // dsub0 |
| 19825 | 0, // dsub1 |
| 19826 | 0, // dsub2 |
| 19827 | 0, // dsub3 |
| 19828 | 0, // hsub |
| 19829 | 0, // qhisub |
| 19830 | 0, // qsub |
| 19831 | 0, // qsub0 |
| 19832 | 0, // qsub1 |
| 19833 | 0, // qsub2 |
| 19834 | 0, // qsub3 |
| 19835 | 0, // ssub |
| 19836 | 54, // sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19837 | 0, // sube32 |
| 19838 | 0, // sube64 |
| 19839 | 0, // subo32 |
| 19840 | 0, // subo64 |
| 19841 | 54, // x8sub_0 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19842 | 54, // x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19843 | 54, // x8sub_2 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19844 | 54, // x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19845 | 54, // x8sub_4 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19846 | 54, // x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19847 | 54, // x8sub_6 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19848 | 54, // x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19849 | 0, // zsub |
| 19850 | 0, // zsub0 |
| 19851 | 0, // zsub1 |
| 19852 | 0, // zsub2 |
| 19853 | 0, // zsub3 |
| 19854 | 0, // zsub_hi |
| 19855 | 0, // dsub1_then_bsub |
| 19856 | 0, // dsub1_then_hsub |
| 19857 | 0, // dsub1_then_ssub |
| 19858 | 0, // dsub3_then_bsub |
| 19859 | 0, // dsub3_then_hsub |
| 19860 | 0, // dsub3_then_ssub |
| 19861 | 0, // dsub2_then_bsub |
| 19862 | 0, // dsub2_then_hsub |
| 19863 | 0, // dsub2_then_ssub |
| 19864 | 0, // qsub1_then_bsub |
| 19865 | 0, // qsub1_then_dsub |
| 19866 | 0, // qsub1_then_hsub |
| 19867 | 0, // qsub1_then_ssub |
| 19868 | 0, // qsub3_then_bsub |
| 19869 | 0, // qsub3_then_dsub |
| 19870 | 0, // qsub3_then_hsub |
| 19871 | 0, // qsub3_then_ssub |
| 19872 | 0, // qsub2_then_bsub |
| 19873 | 0, // qsub2_then_dsub |
| 19874 | 0, // qsub2_then_hsub |
| 19875 | 0, // qsub2_then_ssub |
| 19876 | 54, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19877 | 54, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19878 | 54, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19879 | 54, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19880 | 54, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19881 | 54, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19882 | 54, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19883 | 0, // subo64_then_sub_32 |
| 19884 | 0, // zsub1_then_bsub |
| 19885 | 0, // zsub1_then_dsub |
| 19886 | 0, // zsub1_then_hsub |
| 19887 | 0, // zsub1_then_ssub |
| 19888 | 0, // zsub1_then_zsub |
| 19889 | 0, // zsub1_then_zsub_hi |
| 19890 | 0, // zsub3_then_bsub |
| 19891 | 0, // zsub3_then_dsub |
| 19892 | 0, // zsub3_then_hsub |
| 19893 | 0, // zsub3_then_ssub |
| 19894 | 0, // zsub3_then_zsub |
| 19895 | 0, // zsub3_then_zsub_hi |
| 19896 | 0, // zsub2_then_bsub |
| 19897 | 0, // zsub2_then_dsub |
| 19898 | 0, // zsub2_then_hsub |
| 19899 | 0, // zsub2_then_ssub |
| 19900 | 0, // zsub2_then_zsub |
| 19901 | 0, // zsub2_then_zsub_hi |
| 19902 | 0, // dsub0_dsub1 |
| 19903 | 0, // dsub0_dsub1_dsub2 |
| 19904 | 0, // dsub1_dsub2 |
| 19905 | 0, // dsub1_dsub2_dsub3 |
| 19906 | 0, // dsub2_dsub3 |
| 19907 | 0, // dsub_qsub1_then_dsub |
| 19908 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19909 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 19910 | 0, // qsub0_qsub1 |
| 19911 | 0, // qsub0_qsub1_qsub2 |
| 19912 | 0, // qsub1_qsub2 |
| 19913 | 0, // qsub1_qsub2_qsub3 |
| 19914 | 0, // qsub2_qsub3 |
| 19915 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 19916 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 19917 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 19918 | 54, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19919 | 54, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19920 | 54, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19921 | 54, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19922 | 54, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19923 | 54, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19924 | 54, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19925 | 54, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 19926 | 0, // sub_32_subo64_then_sub_32 |
| 19927 | 0, // dsub_zsub1_then_dsub |
| 19928 | 0, // zsub_zsub1_then_zsub |
| 19929 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19930 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 19931 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19932 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 19933 | 0, // zsub0_zsub1 |
| 19934 | 0, // zsub0_zsub1_zsub2 |
| 19935 | 0, // zsub1_zsub2 |
| 19936 | 0, // zsub1_zsub2_zsub3 |
| 19937 | 0, // zsub2_zsub3 |
| 19938 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 19939 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 19940 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 19941 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 19942 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 19943 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 19944 | }, |
| 19945 | { // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19946 | 0, // bsub |
| 19947 | 0, // dsub |
| 19948 | 0, // dsub0 |
| 19949 | 0, // dsub1 |
| 19950 | 0, // dsub2 |
| 19951 | 0, // dsub3 |
| 19952 | 0, // hsub |
| 19953 | 0, // qhisub |
| 19954 | 0, // qsub |
| 19955 | 0, // qsub0 |
| 19956 | 0, // qsub1 |
| 19957 | 0, // qsub2 |
| 19958 | 0, // qsub3 |
| 19959 | 0, // ssub |
| 19960 | 55, // sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19961 | 0, // sube32 |
| 19962 | 0, // sube64 |
| 19963 | 0, // subo32 |
| 19964 | 0, // subo64 |
| 19965 | 55, // x8sub_0 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19966 | 55, // x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19967 | 55, // x8sub_2 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19968 | 55, // x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19969 | 55, // x8sub_4 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19970 | 55, // x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19971 | 55, // x8sub_6 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19972 | 55, // x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 19973 | 0, // zsub |
| 19974 | 0, // zsub0 |
| 19975 | 0, // zsub1 |
| 19976 | 0, // zsub2 |
| 19977 | 0, // zsub3 |
| 19978 | 0, // zsub_hi |
| 19979 | 0, // dsub1_then_bsub |
| 19980 | 0, // dsub1_then_hsub |
| 19981 | 0, // dsub1_then_ssub |
| 19982 | 0, // dsub3_then_bsub |
| 19983 | 0, // dsub3_then_hsub |
| 19984 | 0, // dsub3_then_ssub |
| 19985 | 0, // dsub2_then_bsub |
| 19986 | 0, // dsub2_then_hsub |
| 19987 | 0, // dsub2_then_ssub |
| 19988 | 0, // qsub1_then_bsub |
| 19989 | 0, // qsub1_then_dsub |
| 19990 | 0, // qsub1_then_hsub |
| 19991 | 0, // qsub1_then_ssub |
| 19992 | 0, // qsub3_then_bsub |
| 19993 | 0, // qsub3_then_dsub |
| 19994 | 0, // qsub3_then_hsub |
| 19995 | 0, // qsub3_then_ssub |
| 19996 | 0, // qsub2_then_bsub |
| 19997 | 0, // qsub2_then_dsub |
| 19998 | 0, // qsub2_then_hsub |
| 19999 | 0, // qsub2_then_ssub |
| 20000 | 55, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20001 | 55, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20002 | 55, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20003 | 55, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20004 | 55, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20005 | 55, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20006 | 55, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20007 | 0, // subo64_then_sub_32 |
| 20008 | 0, // zsub1_then_bsub |
| 20009 | 0, // zsub1_then_dsub |
| 20010 | 0, // zsub1_then_hsub |
| 20011 | 0, // zsub1_then_ssub |
| 20012 | 0, // zsub1_then_zsub |
| 20013 | 0, // zsub1_then_zsub_hi |
| 20014 | 0, // zsub3_then_bsub |
| 20015 | 0, // zsub3_then_dsub |
| 20016 | 0, // zsub3_then_hsub |
| 20017 | 0, // zsub3_then_ssub |
| 20018 | 0, // zsub3_then_zsub |
| 20019 | 0, // zsub3_then_zsub_hi |
| 20020 | 0, // zsub2_then_bsub |
| 20021 | 0, // zsub2_then_dsub |
| 20022 | 0, // zsub2_then_hsub |
| 20023 | 0, // zsub2_then_ssub |
| 20024 | 0, // zsub2_then_zsub |
| 20025 | 0, // zsub2_then_zsub_hi |
| 20026 | 0, // dsub0_dsub1 |
| 20027 | 0, // dsub0_dsub1_dsub2 |
| 20028 | 0, // dsub1_dsub2 |
| 20029 | 0, // dsub1_dsub2_dsub3 |
| 20030 | 0, // dsub2_dsub3 |
| 20031 | 0, // dsub_qsub1_then_dsub |
| 20032 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20033 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20034 | 0, // qsub0_qsub1 |
| 20035 | 0, // qsub0_qsub1_qsub2 |
| 20036 | 0, // qsub1_qsub2 |
| 20037 | 0, // qsub1_qsub2_qsub3 |
| 20038 | 0, // qsub2_qsub3 |
| 20039 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20040 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20041 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20042 | 55, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20043 | 55, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20044 | 55, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20045 | 55, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20046 | 55, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20047 | 55, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20048 | 55, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20049 | 55, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20050 | 0, // sub_32_subo64_then_sub_32 |
| 20051 | 0, // dsub_zsub1_then_dsub |
| 20052 | 0, // zsub_zsub1_then_zsub |
| 20053 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20054 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20055 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20056 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20057 | 0, // zsub0_zsub1 |
| 20058 | 0, // zsub0_zsub1_zsub2 |
| 20059 | 0, // zsub1_zsub2 |
| 20060 | 0, // zsub1_zsub2_zsub3 |
| 20061 | 0, // zsub2_zsub3 |
| 20062 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20063 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20064 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20065 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20066 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20067 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20068 | }, |
| 20069 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20070 | 0, // bsub |
| 20071 | 0, // dsub |
| 20072 | 0, // dsub0 |
| 20073 | 0, // dsub1 |
| 20074 | 0, // dsub2 |
| 20075 | 0, // dsub3 |
| 20076 | 0, // hsub |
| 20077 | 0, // qhisub |
| 20078 | 0, // qsub |
| 20079 | 0, // qsub0 |
| 20080 | 0, // qsub1 |
| 20081 | 0, // qsub2 |
| 20082 | 0, // qsub3 |
| 20083 | 0, // ssub |
| 20084 | 56, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20085 | 0, // sube32 |
| 20086 | 0, // sube64 |
| 20087 | 0, // subo32 |
| 20088 | 0, // subo64 |
| 20089 | 56, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20090 | 56, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20091 | 56, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20092 | 56, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20093 | 56, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20094 | 56, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20095 | 56, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20096 | 56, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20097 | 0, // zsub |
| 20098 | 0, // zsub0 |
| 20099 | 0, // zsub1 |
| 20100 | 0, // zsub2 |
| 20101 | 0, // zsub3 |
| 20102 | 0, // zsub_hi |
| 20103 | 0, // dsub1_then_bsub |
| 20104 | 0, // dsub1_then_hsub |
| 20105 | 0, // dsub1_then_ssub |
| 20106 | 0, // dsub3_then_bsub |
| 20107 | 0, // dsub3_then_hsub |
| 20108 | 0, // dsub3_then_ssub |
| 20109 | 0, // dsub2_then_bsub |
| 20110 | 0, // dsub2_then_hsub |
| 20111 | 0, // dsub2_then_ssub |
| 20112 | 0, // qsub1_then_bsub |
| 20113 | 0, // qsub1_then_dsub |
| 20114 | 0, // qsub1_then_hsub |
| 20115 | 0, // qsub1_then_ssub |
| 20116 | 0, // qsub3_then_bsub |
| 20117 | 0, // qsub3_then_dsub |
| 20118 | 0, // qsub3_then_hsub |
| 20119 | 0, // qsub3_then_ssub |
| 20120 | 0, // qsub2_then_bsub |
| 20121 | 0, // qsub2_then_dsub |
| 20122 | 0, // qsub2_then_hsub |
| 20123 | 0, // qsub2_then_ssub |
| 20124 | 56, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20125 | 56, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20126 | 56, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20127 | 56, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20128 | 56, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20129 | 56, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20130 | 56, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20131 | 0, // subo64_then_sub_32 |
| 20132 | 0, // zsub1_then_bsub |
| 20133 | 0, // zsub1_then_dsub |
| 20134 | 0, // zsub1_then_hsub |
| 20135 | 0, // zsub1_then_ssub |
| 20136 | 0, // zsub1_then_zsub |
| 20137 | 0, // zsub1_then_zsub_hi |
| 20138 | 0, // zsub3_then_bsub |
| 20139 | 0, // zsub3_then_dsub |
| 20140 | 0, // zsub3_then_hsub |
| 20141 | 0, // zsub3_then_ssub |
| 20142 | 0, // zsub3_then_zsub |
| 20143 | 0, // zsub3_then_zsub_hi |
| 20144 | 0, // zsub2_then_bsub |
| 20145 | 0, // zsub2_then_dsub |
| 20146 | 0, // zsub2_then_hsub |
| 20147 | 0, // zsub2_then_ssub |
| 20148 | 0, // zsub2_then_zsub |
| 20149 | 0, // zsub2_then_zsub_hi |
| 20150 | 0, // dsub0_dsub1 |
| 20151 | 0, // dsub0_dsub1_dsub2 |
| 20152 | 0, // dsub1_dsub2 |
| 20153 | 0, // dsub1_dsub2_dsub3 |
| 20154 | 0, // dsub2_dsub3 |
| 20155 | 0, // dsub_qsub1_then_dsub |
| 20156 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20157 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20158 | 0, // qsub0_qsub1 |
| 20159 | 0, // qsub0_qsub1_qsub2 |
| 20160 | 0, // qsub1_qsub2 |
| 20161 | 0, // qsub1_qsub2_qsub3 |
| 20162 | 0, // qsub2_qsub3 |
| 20163 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20164 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20165 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20166 | 56, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20167 | 56, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20168 | 56, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20169 | 56, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20170 | 56, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20171 | 56, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20172 | 56, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20173 | 56, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20174 | 0, // sub_32_subo64_then_sub_32 |
| 20175 | 0, // dsub_zsub1_then_dsub |
| 20176 | 0, // zsub_zsub1_then_zsub |
| 20177 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20178 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20179 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20180 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20181 | 0, // zsub0_zsub1 |
| 20182 | 0, // zsub0_zsub1_zsub2 |
| 20183 | 0, // zsub1_zsub2 |
| 20184 | 0, // zsub1_zsub2_zsub3 |
| 20185 | 0, // zsub2_zsub3 |
| 20186 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20187 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20188 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20189 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20190 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20191 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20192 | }, |
| 20193 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20194 | 0, // bsub |
| 20195 | 0, // dsub |
| 20196 | 0, // dsub0 |
| 20197 | 0, // dsub1 |
| 20198 | 0, // dsub2 |
| 20199 | 0, // dsub3 |
| 20200 | 0, // hsub |
| 20201 | 0, // qhisub |
| 20202 | 0, // qsub |
| 20203 | 0, // qsub0 |
| 20204 | 0, // qsub1 |
| 20205 | 0, // qsub2 |
| 20206 | 0, // qsub3 |
| 20207 | 0, // ssub |
| 20208 | 57, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20209 | 0, // sube32 |
| 20210 | 0, // sube64 |
| 20211 | 0, // subo32 |
| 20212 | 0, // subo64 |
| 20213 | 57, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20214 | 57, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20215 | 57, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20216 | 57, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20217 | 57, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20218 | 57, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20219 | 57, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20220 | 57, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20221 | 0, // zsub |
| 20222 | 0, // zsub0 |
| 20223 | 0, // zsub1 |
| 20224 | 0, // zsub2 |
| 20225 | 0, // zsub3 |
| 20226 | 0, // zsub_hi |
| 20227 | 0, // dsub1_then_bsub |
| 20228 | 0, // dsub1_then_hsub |
| 20229 | 0, // dsub1_then_ssub |
| 20230 | 0, // dsub3_then_bsub |
| 20231 | 0, // dsub3_then_hsub |
| 20232 | 0, // dsub3_then_ssub |
| 20233 | 0, // dsub2_then_bsub |
| 20234 | 0, // dsub2_then_hsub |
| 20235 | 0, // dsub2_then_ssub |
| 20236 | 0, // qsub1_then_bsub |
| 20237 | 0, // qsub1_then_dsub |
| 20238 | 0, // qsub1_then_hsub |
| 20239 | 0, // qsub1_then_ssub |
| 20240 | 0, // qsub3_then_bsub |
| 20241 | 0, // qsub3_then_dsub |
| 20242 | 0, // qsub3_then_hsub |
| 20243 | 0, // qsub3_then_ssub |
| 20244 | 0, // qsub2_then_bsub |
| 20245 | 0, // qsub2_then_dsub |
| 20246 | 0, // qsub2_then_hsub |
| 20247 | 0, // qsub2_then_ssub |
| 20248 | 57, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20249 | 57, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20250 | 57, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20251 | 57, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20252 | 57, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20253 | 57, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20254 | 57, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20255 | 0, // subo64_then_sub_32 |
| 20256 | 0, // zsub1_then_bsub |
| 20257 | 0, // zsub1_then_dsub |
| 20258 | 0, // zsub1_then_hsub |
| 20259 | 0, // zsub1_then_ssub |
| 20260 | 0, // zsub1_then_zsub |
| 20261 | 0, // zsub1_then_zsub_hi |
| 20262 | 0, // zsub3_then_bsub |
| 20263 | 0, // zsub3_then_dsub |
| 20264 | 0, // zsub3_then_hsub |
| 20265 | 0, // zsub3_then_ssub |
| 20266 | 0, // zsub3_then_zsub |
| 20267 | 0, // zsub3_then_zsub_hi |
| 20268 | 0, // zsub2_then_bsub |
| 20269 | 0, // zsub2_then_dsub |
| 20270 | 0, // zsub2_then_hsub |
| 20271 | 0, // zsub2_then_ssub |
| 20272 | 0, // zsub2_then_zsub |
| 20273 | 0, // zsub2_then_zsub_hi |
| 20274 | 0, // dsub0_dsub1 |
| 20275 | 0, // dsub0_dsub1_dsub2 |
| 20276 | 0, // dsub1_dsub2 |
| 20277 | 0, // dsub1_dsub2_dsub3 |
| 20278 | 0, // dsub2_dsub3 |
| 20279 | 0, // dsub_qsub1_then_dsub |
| 20280 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20281 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20282 | 0, // qsub0_qsub1 |
| 20283 | 0, // qsub0_qsub1_qsub2 |
| 20284 | 0, // qsub1_qsub2 |
| 20285 | 0, // qsub1_qsub2_qsub3 |
| 20286 | 0, // qsub2_qsub3 |
| 20287 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20288 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20289 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20290 | 57, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20291 | 57, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20292 | 57, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20293 | 57, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20294 | 57, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20295 | 57, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20296 | 57, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20297 | 57, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20298 | 0, // sub_32_subo64_then_sub_32 |
| 20299 | 0, // dsub_zsub1_then_dsub |
| 20300 | 0, // zsub_zsub1_then_zsub |
| 20301 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20302 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20303 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20304 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20305 | 0, // zsub0_zsub1 |
| 20306 | 0, // zsub0_zsub1_zsub2 |
| 20307 | 0, // zsub1_zsub2 |
| 20308 | 0, // zsub1_zsub2_zsub3 |
| 20309 | 0, // zsub2_zsub3 |
| 20310 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20311 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20312 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20313 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20314 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20315 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20316 | }, |
| 20317 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20318 | 0, // bsub |
| 20319 | 0, // dsub |
| 20320 | 0, // dsub0 |
| 20321 | 0, // dsub1 |
| 20322 | 0, // dsub2 |
| 20323 | 0, // dsub3 |
| 20324 | 0, // hsub |
| 20325 | 0, // qhisub |
| 20326 | 0, // qsub |
| 20327 | 0, // qsub0 |
| 20328 | 0, // qsub1 |
| 20329 | 0, // qsub2 |
| 20330 | 0, // qsub3 |
| 20331 | 0, // ssub |
| 20332 | 58, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20333 | 0, // sube32 |
| 20334 | 0, // sube64 |
| 20335 | 0, // subo32 |
| 20336 | 0, // subo64 |
| 20337 | 58, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20338 | 58, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20339 | 58, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20340 | 58, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20341 | 58, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20342 | 58, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20343 | 58, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20344 | 58, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20345 | 0, // zsub |
| 20346 | 0, // zsub0 |
| 20347 | 0, // zsub1 |
| 20348 | 0, // zsub2 |
| 20349 | 0, // zsub3 |
| 20350 | 0, // zsub_hi |
| 20351 | 0, // dsub1_then_bsub |
| 20352 | 0, // dsub1_then_hsub |
| 20353 | 0, // dsub1_then_ssub |
| 20354 | 0, // dsub3_then_bsub |
| 20355 | 0, // dsub3_then_hsub |
| 20356 | 0, // dsub3_then_ssub |
| 20357 | 0, // dsub2_then_bsub |
| 20358 | 0, // dsub2_then_hsub |
| 20359 | 0, // dsub2_then_ssub |
| 20360 | 0, // qsub1_then_bsub |
| 20361 | 0, // qsub1_then_dsub |
| 20362 | 0, // qsub1_then_hsub |
| 20363 | 0, // qsub1_then_ssub |
| 20364 | 0, // qsub3_then_bsub |
| 20365 | 0, // qsub3_then_dsub |
| 20366 | 0, // qsub3_then_hsub |
| 20367 | 0, // qsub3_then_ssub |
| 20368 | 0, // qsub2_then_bsub |
| 20369 | 0, // qsub2_then_dsub |
| 20370 | 0, // qsub2_then_hsub |
| 20371 | 0, // qsub2_then_ssub |
| 20372 | 58, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20373 | 58, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20374 | 58, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20375 | 58, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20376 | 58, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20377 | 58, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20378 | 58, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20379 | 0, // subo64_then_sub_32 |
| 20380 | 0, // zsub1_then_bsub |
| 20381 | 0, // zsub1_then_dsub |
| 20382 | 0, // zsub1_then_hsub |
| 20383 | 0, // zsub1_then_ssub |
| 20384 | 0, // zsub1_then_zsub |
| 20385 | 0, // zsub1_then_zsub_hi |
| 20386 | 0, // zsub3_then_bsub |
| 20387 | 0, // zsub3_then_dsub |
| 20388 | 0, // zsub3_then_hsub |
| 20389 | 0, // zsub3_then_ssub |
| 20390 | 0, // zsub3_then_zsub |
| 20391 | 0, // zsub3_then_zsub_hi |
| 20392 | 0, // zsub2_then_bsub |
| 20393 | 0, // zsub2_then_dsub |
| 20394 | 0, // zsub2_then_hsub |
| 20395 | 0, // zsub2_then_ssub |
| 20396 | 0, // zsub2_then_zsub |
| 20397 | 0, // zsub2_then_zsub_hi |
| 20398 | 0, // dsub0_dsub1 |
| 20399 | 0, // dsub0_dsub1_dsub2 |
| 20400 | 0, // dsub1_dsub2 |
| 20401 | 0, // dsub1_dsub2_dsub3 |
| 20402 | 0, // dsub2_dsub3 |
| 20403 | 0, // dsub_qsub1_then_dsub |
| 20404 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20405 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20406 | 0, // qsub0_qsub1 |
| 20407 | 0, // qsub0_qsub1_qsub2 |
| 20408 | 0, // qsub1_qsub2 |
| 20409 | 0, // qsub1_qsub2_qsub3 |
| 20410 | 0, // qsub2_qsub3 |
| 20411 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20412 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20413 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20414 | 58, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20415 | 58, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20416 | 58, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20417 | 58, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20418 | 58, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20419 | 58, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20420 | 58, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20421 | 58, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 20422 | 0, // sub_32_subo64_then_sub_32 |
| 20423 | 0, // dsub_zsub1_then_dsub |
| 20424 | 0, // zsub_zsub1_then_zsub |
| 20425 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20426 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20427 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20428 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20429 | 0, // zsub0_zsub1 |
| 20430 | 0, // zsub0_zsub1_zsub2 |
| 20431 | 0, // zsub1_zsub2 |
| 20432 | 0, // zsub1_zsub2_zsub3 |
| 20433 | 0, // zsub2_zsub3 |
| 20434 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20435 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20436 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20437 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20438 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20439 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20440 | }, |
| 20441 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20442 | 0, // bsub |
| 20443 | 0, // dsub |
| 20444 | 0, // dsub0 |
| 20445 | 0, // dsub1 |
| 20446 | 0, // dsub2 |
| 20447 | 0, // dsub3 |
| 20448 | 0, // hsub |
| 20449 | 0, // qhisub |
| 20450 | 0, // qsub |
| 20451 | 0, // qsub0 |
| 20452 | 0, // qsub1 |
| 20453 | 0, // qsub2 |
| 20454 | 0, // qsub3 |
| 20455 | 0, // ssub |
| 20456 | 59, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20457 | 0, // sube32 |
| 20458 | 0, // sube64 |
| 20459 | 0, // subo32 |
| 20460 | 0, // subo64 |
| 20461 | 59, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20462 | 59, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20463 | 59, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20464 | 59, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20465 | 59, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20466 | 59, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20467 | 59, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20468 | 59, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20469 | 0, // zsub |
| 20470 | 0, // zsub0 |
| 20471 | 0, // zsub1 |
| 20472 | 0, // zsub2 |
| 20473 | 0, // zsub3 |
| 20474 | 0, // zsub_hi |
| 20475 | 0, // dsub1_then_bsub |
| 20476 | 0, // dsub1_then_hsub |
| 20477 | 0, // dsub1_then_ssub |
| 20478 | 0, // dsub3_then_bsub |
| 20479 | 0, // dsub3_then_hsub |
| 20480 | 0, // dsub3_then_ssub |
| 20481 | 0, // dsub2_then_bsub |
| 20482 | 0, // dsub2_then_hsub |
| 20483 | 0, // dsub2_then_ssub |
| 20484 | 0, // qsub1_then_bsub |
| 20485 | 0, // qsub1_then_dsub |
| 20486 | 0, // qsub1_then_hsub |
| 20487 | 0, // qsub1_then_ssub |
| 20488 | 0, // qsub3_then_bsub |
| 20489 | 0, // qsub3_then_dsub |
| 20490 | 0, // qsub3_then_hsub |
| 20491 | 0, // qsub3_then_ssub |
| 20492 | 0, // qsub2_then_bsub |
| 20493 | 0, // qsub2_then_dsub |
| 20494 | 0, // qsub2_then_hsub |
| 20495 | 0, // qsub2_then_ssub |
| 20496 | 59, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20497 | 59, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20498 | 59, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20499 | 59, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20500 | 59, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20501 | 59, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20502 | 59, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20503 | 0, // subo64_then_sub_32 |
| 20504 | 0, // zsub1_then_bsub |
| 20505 | 0, // zsub1_then_dsub |
| 20506 | 0, // zsub1_then_hsub |
| 20507 | 0, // zsub1_then_ssub |
| 20508 | 0, // zsub1_then_zsub |
| 20509 | 0, // zsub1_then_zsub_hi |
| 20510 | 0, // zsub3_then_bsub |
| 20511 | 0, // zsub3_then_dsub |
| 20512 | 0, // zsub3_then_hsub |
| 20513 | 0, // zsub3_then_ssub |
| 20514 | 0, // zsub3_then_zsub |
| 20515 | 0, // zsub3_then_zsub_hi |
| 20516 | 0, // zsub2_then_bsub |
| 20517 | 0, // zsub2_then_dsub |
| 20518 | 0, // zsub2_then_hsub |
| 20519 | 0, // zsub2_then_ssub |
| 20520 | 0, // zsub2_then_zsub |
| 20521 | 0, // zsub2_then_zsub_hi |
| 20522 | 0, // dsub0_dsub1 |
| 20523 | 0, // dsub0_dsub1_dsub2 |
| 20524 | 0, // dsub1_dsub2 |
| 20525 | 0, // dsub1_dsub2_dsub3 |
| 20526 | 0, // dsub2_dsub3 |
| 20527 | 0, // dsub_qsub1_then_dsub |
| 20528 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20529 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20530 | 0, // qsub0_qsub1 |
| 20531 | 0, // qsub0_qsub1_qsub2 |
| 20532 | 0, // qsub1_qsub2 |
| 20533 | 0, // qsub1_qsub2_qsub3 |
| 20534 | 0, // qsub2_qsub3 |
| 20535 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20536 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20537 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20538 | 59, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20539 | 59, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20540 | 59, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20541 | 59, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20542 | 59, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20543 | 59, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20544 | 59, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20545 | 59, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20546 | 0, // sub_32_subo64_then_sub_32 |
| 20547 | 0, // dsub_zsub1_then_dsub |
| 20548 | 0, // zsub_zsub1_then_zsub |
| 20549 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20550 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20551 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20552 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20553 | 0, // zsub0_zsub1 |
| 20554 | 0, // zsub0_zsub1_zsub2 |
| 20555 | 0, // zsub1_zsub2 |
| 20556 | 0, // zsub1_zsub2_zsub3 |
| 20557 | 0, // zsub2_zsub3 |
| 20558 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20559 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20560 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20561 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20562 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20563 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20564 | }, |
| 20565 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20566 | 0, // bsub |
| 20567 | 0, // dsub |
| 20568 | 0, // dsub0 |
| 20569 | 0, // dsub1 |
| 20570 | 0, // dsub2 |
| 20571 | 0, // dsub3 |
| 20572 | 0, // hsub |
| 20573 | 0, // qhisub |
| 20574 | 0, // qsub |
| 20575 | 0, // qsub0 |
| 20576 | 0, // qsub1 |
| 20577 | 0, // qsub2 |
| 20578 | 0, // qsub3 |
| 20579 | 0, // ssub |
| 20580 | 60, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20581 | 0, // sube32 |
| 20582 | 0, // sube64 |
| 20583 | 0, // subo32 |
| 20584 | 0, // subo64 |
| 20585 | 60, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20586 | 60, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20587 | 60, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20588 | 60, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20589 | 60, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20590 | 60, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20591 | 60, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20592 | 60, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20593 | 0, // zsub |
| 20594 | 0, // zsub0 |
| 20595 | 0, // zsub1 |
| 20596 | 0, // zsub2 |
| 20597 | 0, // zsub3 |
| 20598 | 0, // zsub_hi |
| 20599 | 0, // dsub1_then_bsub |
| 20600 | 0, // dsub1_then_hsub |
| 20601 | 0, // dsub1_then_ssub |
| 20602 | 0, // dsub3_then_bsub |
| 20603 | 0, // dsub3_then_hsub |
| 20604 | 0, // dsub3_then_ssub |
| 20605 | 0, // dsub2_then_bsub |
| 20606 | 0, // dsub2_then_hsub |
| 20607 | 0, // dsub2_then_ssub |
| 20608 | 0, // qsub1_then_bsub |
| 20609 | 0, // qsub1_then_dsub |
| 20610 | 0, // qsub1_then_hsub |
| 20611 | 0, // qsub1_then_ssub |
| 20612 | 0, // qsub3_then_bsub |
| 20613 | 0, // qsub3_then_dsub |
| 20614 | 0, // qsub3_then_hsub |
| 20615 | 0, // qsub3_then_ssub |
| 20616 | 0, // qsub2_then_bsub |
| 20617 | 0, // qsub2_then_dsub |
| 20618 | 0, // qsub2_then_hsub |
| 20619 | 0, // qsub2_then_ssub |
| 20620 | 60, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20621 | 60, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20622 | 60, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20623 | 60, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20624 | 60, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20625 | 60, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20626 | 60, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20627 | 0, // subo64_then_sub_32 |
| 20628 | 0, // zsub1_then_bsub |
| 20629 | 0, // zsub1_then_dsub |
| 20630 | 0, // zsub1_then_hsub |
| 20631 | 0, // zsub1_then_ssub |
| 20632 | 0, // zsub1_then_zsub |
| 20633 | 0, // zsub1_then_zsub_hi |
| 20634 | 0, // zsub3_then_bsub |
| 20635 | 0, // zsub3_then_dsub |
| 20636 | 0, // zsub3_then_hsub |
| 20637 | 0, // zsub3_then_ssub |
| 20638 | 0, // zsub3_then_zsub |
| 20639 | 0, // zsub3_then_zsub_hi |
| 20640 | 0, // zsub2_then_bsub |
| 20641 | 0, // zsub2_then_dsub |
| 20642 | 0, // zsub2_then_hsub |
| 20643 | 0, // zsub2_then_ssub |
| 20644 | 0, // zsub2_then_zsub |
| 20645 | 0, // zsub2_then_zsub_hi |
| 20646 | 0, // dsub0_dsub1 |
| 20647 | 0, // dsub0_dsub1_dsub2 |
| 20648 | 0, // dsub1_dsub2 |
| 20649 | 0, // dsub1_dsub2_dsub3 |
| 20650 | 0, // dsub2_dsub3 |
| 20651 | 0, // dsub_qsub1_then_dsub |
| 20652 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20653 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20654 | 0, // qsub0_qsub1 |
| 20655 | 0, // qsub0_qsub1_qsub2 |
| 20656 | 0, // qsub1_qsub2 |
| 20657 | 0, // qsub1_qsub2_qsub3 |
| 20658 | 0, // qsub2_qsub3 |
| 20659 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20660 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20661 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20662 | 60, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20663 | 60, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20664 | 60, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20665 | 60, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20666 | 60, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20667 | 60, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20668 | 60, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20669 | 60, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20670 | 0, // sub_32_subo64_then_sub_32 |
| 20671 | 0, // dsub_zsub1_then_dsub |
| 20672 | 0, // zsub_zsub1_then_zsub |
| 20673 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20674 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20675 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20676 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20677 | 0, // zsub0_zsub1 |
| 20678 | 0, // zsub0_zsub1_zsub2 |
| 20679 | 0, // zsub1_zsub2 |
| 20680 | 0, // zsub1_zsub2_zsub3 |
| 20681 | 0, // zsub2_zsub3 |
| 20682 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20683 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20684 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20685 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20686 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20687 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20688 | }, |
| 20689 | { // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20690 | 0, // bsub |
| 20691 | 0, // dsub |
| 20692 | 0, // dsub0 |
| 20693 | 0, // dsub1 |
| 20694 | 0, // dsub2 |
| 20695 | 0, // dsub3 |
| 20696 | 0, // hsub |
| 20697 | 0, // qhisub |
| 20698 | 0, // qsub |
| 20699 | 0, // qsub0 |
| 20700 | 0, // qsub1 |
| 20701 | 0, // qsub2 |
| 20702 | 0, // qsub3 |
| 20703 | 0, // ssub |
| 20704 | 61, // sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20705 | 0, // sube32 |
| 20706 | 0, // sube64 |
| 20707 | 0, // subo32 |
| 20708 | 0, // subo64 |
| 20709 | 61, // x8sub_0 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20710 | 61, // x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20711 | 61, // x8sub_2 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20712 | 61, // x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20713 | 61, // x8sub_4 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20714 | 61, // x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20715 | 61, // x8sub_6 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20716 | 61, // x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20717 | 0, // zsub |
| 20718 | 0, // zsub0 |
| 20719 | 0, // zsub1 |
| 20720 | 0, // zsub2 |
| 20721 | 0, // zsub3 |
| 20722 | 0, // zsub_hi |
| 20723 | 0, // dsub1_then_bsub |
| 20724 | 0, // dsub1_then_hsub |
| 20725 | 0, // dsub1_then_ssub |
| 20726 | 0, // dsub3_then_bsub |
| 20727 | 0, // dsub3_then_hsub |
| 20728 | 0, // dsub3_then_ssub |
| 20729 | 0, // dsub2_then_bsub |
| 20730 | 0, // dsub2_then_hsub |
| 20731 | 0, // dsub2_then_ssub |
| 20732 | 0, // qsub1_then_bsub |
| 20733 | 0, // qsub1_then_dsub |
| 20734 | 0, // qsub1_then_hsub |
| 20735 | 0, // qsub1_then_ssub |
| 20736 | 0, // qsub3_then_bsub |
| 20737 | 0, // qsub3_then_dsub |
| 20738 | 0, // qsub3_then_hsub |
| 20739 | 0, // qsub3_then_ssub |
| 20740 | 0, // qsub2_then_bsub |
| 20741 | 0, // qsub2_then_dsub |
| 20742 | 0, // qsub2_then_hsub |
| 20743 | 0, // qsub2_then_ssub |
| 20744 | 61, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20745 | 61, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20746 | 61, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20747 | 61, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20748 | 61, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20749 | 61, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20750 | 61, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20751 | 0, // subo64_then_sub_32 |
| 20752 | 0, // zsub1_then_bsub |
| 20753 | 0, // zsub1_then_dsub |
| 20754 | 0, // zsub1_then_hsub |
| 20755 | 0, // zsub1_then_ssub |
| 20756 | 0, // zsub1_then_zsub |
| 20757 | 0, // zsub1_then_zsub_hi |
| 20758 | 0, // zsub3_then_bsub |
| 20759 | 0, // zsub3_then_dsub |
| 20760 | 0, // zsub3_then_hsub |
| 20761 | 0, // zsub3_then_ssub |
| 20762 | 0, // zsub3_then_zsub |
| 20763 | 0, // zsub3_then_zsub_hi |
| 20764 | 0, // zsub2_then_bsub |
| 20765 | 0, // zsub2_then_dsub |
| 20766 | 0, // zsub2_then_hsub |
| 20767 | 0, // zsub2_then_ssub |
| 20768 | 0, // zsub2_then_zsub |
| 20769 | 0, // zsub2_then_zsub_hi |
| 20770 | 0, // dsub0_dsub1 |
| 20771 | 0, // dsub0_dsub1_dsub2 |
| 20772 | 0, // dsub1_dsub2 |
| 20773 | 0, // dsub1_dsub2_dsub3 |
| 20774 | 0, // dsub2_dsub3 |
| 20775 | 0, // dsub_qsub1_then_dsub |
| 20776 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20777 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20778 | 0, // qsub0_qsub1 |
| 20779 | 0, // qsub0_qsub1_qsub2 |
| 20780 | 0, // qsub1_qsub2 |
| 20781 | 0, // qsub1_qsub2_qsub3 |
| 20782 | 0, // qsub2_qsub3 |
| 20783 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20784 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20785 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20786 | 61, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20787 | 61, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20788 | 61, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20789 | 61, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20790 | 61, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20791 | 61, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20792 | 61, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20793 | 61, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20794 | 0, // sub_32_subo64_then_sub_32 |
| 20795 | 0, // dsub_zsub1_then_dsub |
| 20796 | 0, // zsub_zsub1_then_zsub |
| 20797 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20798 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20799 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20800 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20801 | 0, // zsub0_zsub1 |
| 20802 | 0, // zsub0_zsub1_zsub2 |
| 20803 | 0, // zsub1_zsub2 |
| 20804 | 0, // zsub1_zsub2_zsub3 |
| 20805 | 0, // zsub2_zsub3 |
| 20806 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20807 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20808 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20809 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20810 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20811 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20812 | }, |
| 20813 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20814 | 0, // bsub |
| 20815 | 0, // dsub |
| 20816 | 0, // dsub0 |
| 20817 | 0, // dsub1 |
| 20818 | 0, // dsub2 |
| 20819 | 0, // dsub3 |
| 20820 | 0, // hsub |
| 20821 | 0, // qhisub |
| 20822 | 0, // qsub |
| 20823 | 0, // qsub0 |
| 20824 | 0, // qsub1 |
| 20825 | 0, // qsub2 |
| 20826 | 0, // qsub3 |
| 20827 | 0, // ssub |
| 20828 | 62, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20829 | 0, // sube32 |
| 20830 | 0, // sube64 |
| 20831 | 0, // subo32 |
| 20832 | 0, // subo64 |
| 20833 | 62, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20834 | 62, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20835 | 62, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20836 | 62, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20837 | 62, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20838 | 62, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20839 | 62, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20840 | 62, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20841 | 0, // zsub |
| 20842 | 0, // zsub0 |
| 20843 | 0, // zsub1 |
| 20844 | 0, // zsub2 |
| 20845 | 0, // zsub3 |
| 20846 | 0, // zsub_hi |
| 20847 | 0, // dsub1_then_bsub |
| 20848 | 0, // dsub1_then_hsub |
| 20849 | 0, // dsub1_then_ssub |
| 20850 | 0, // dsub3_then_bsub |
| 20851 | 0, // dsub3_then_hsub |
| 20852 | 0, // dsub3_then_ssub |
| 20853 | 0, // dsub2_then_bsub |
| 20854 | 0, // dsub2_then_hsub |
| 20855 | 0, // dsub2_then_ssub |
| 20856 | 0, // qsub1_then_bsub |
| 20857 | 0, // qsub1_then_dsub |
| 20858 | 0, // qsub1_then_hsub |
| 20859 | 0, // qsub1_then_ssub |
| 20860 | 0, // qsub3_then_bsub |
| 20861 | 0, // qsub3_then_dsub |
| 20862 | 0, // qsub3_then_hsub |
| 20863 | 0, // qsub3_then_ssub |
| 20864 | 0, // qsub2_then_bsub |
| 20865 | 0, // qsub2_then_dsub |
| 20866 | 0, // qsub2_then_hsub |
| 20867 | 0, // qsub2_then_ssub |
| 20868 | 62, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20869 | 62, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20870 | 62, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20871 | 62, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20872 | 62, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20873 | 62, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20874 | 62, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20875 | 0, // subo64_then_sub_32 |
| 20876 | 0, // zsub1_then_bsub |
| 20877 | 0, // zsub1_then_dsub |
| 20878 | 0, // zsub1_then_hsub |
| 20879 | 0, // zsub1_then_ssub |
| 20880 | 0, // zsub1_then_zsub |
| 20881 | 0, // zsub1_then_zsub_hi |
| 20882 | 0, // zsub3_then_bsub |
| 20883 | 0, // zsub3_then_dsub |
| 20884 | 0, // zsub3_then_hsub |
| 20885 | 0, // zsub3_then_ssub |
| 20886 | 0, // zsub3_then_zsub |
| 20887 | 0, // zsub3_then_zsub_hi |
| 20888 | 0, // zsub2_then_bsub |
| 20889 | 0, // zsub2_then_dsub |
| 20890 | 0, // zsub2_then_hsub |
| 20891 | 0, // zsub2_then_ssub |
| 20892 | 0, // zsub2_then_zsub |
| 20893 | 0, // zsub2_then_zsub_hi |
| 20894 | 0, // dsub0_dsub1 |
| 20895 | 0, // dsub0_dsub1_dsub2 |
| 20896 | 0, // dsub1_dsub2 |
| 20897 | 0, // dsub1_dsub2_dsub3 |
| 20898 | 0, // dsub2_dsub3 |
| 20899 | 0, // dsub_qsub1_then_dsub |
| 20900 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20901 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 20902 | 0, // qsub0_qsub1 |
| 20903 | 0, // qsub0_qsub1_qsub2 |
| 20904 | 0, // qsub1_qsub2 |
| 20905 | 0, // qsub1_qsub2_qsub3 |
| 20906 | 0, // qsub2_qsub3 |
| 20907 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 20908 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 20909 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 20910 | 62, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20911 | 62, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20912 | 62, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20913 | 62, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20914 | 62, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20915 | 62, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20916 | 62, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20917 | 62, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 20918 | 0, // sub_32_subo64_then_sub_32 |
| 20919 | 0, // dsub_zsub1_then_dsub |
| 20920 | 0, // zsub_zsub1_then_zsub |
| 20921 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20922 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 20923 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20924 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 20925 | 0, // zsub0_zsub1 |
| 20926 | 0, // zsub0_zsub1_zsub2 |
| 20927 | 0, // zsub1_zsub2 |
| 20928 | 0, // zsub1_zsub2_zsub3 |
| 20929 | 0, // zsub2_zsub3 |
| 20930 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 20931 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 20932 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 20933 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 20934 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 20935 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 20936 | }, |
| 20937 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20938 | 0, // bsub |
| 20939 | 0, // dsub |
| 20940 | 0, // dsub0 |
| 20941 | 0, // dsub1 |
| 20942 | 0, // dsub2 |
| 20943 | 0, // dsub3 |
| 20944 | 0, // hsub |
| 20945 | 0, // qhisub |
| 20946 | 0, // qsub |
| 20947 | 0, // qsub0 |
| 20948 | 0, // qsub1 |
| 20949 | 0, // qsub2 |
| 20950 | 0, // qsub3 |
| 20951 | 0, // ssub |
| 20952 | 63, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20953 | 0, // sube32 |
| 20954 | 0, // sube64 |
| 20955 | 0, // subo32 |
| 20956 | 0, // subo64 |
| 20957 | 63, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20958 | 63, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20959 | 63, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20960 | 63, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20961 | 63, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20962 | 63, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20963 | 63, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20964 | 63, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20965 | 0, // zsub |
| 20966 | 0, // zsub0 |
| 20967 | 0, // zsub1 |
| 20968 | 0, // zsub2 |
| 20969 | 0, // zsub3 |
| 20970 | 0, // zsub_hi |
| 20971 | 0, // dsub1_then_bsub |
| 20972 | 0, // dsub1_then_hsub |
| 20973 | 0, // dsub1_then_ssub |
| 20974 | 0, // dsub3_then_bsub |
| 20975 | 0, // dsub3_then_hsub |
| 20976 | 0, // dsub3_then_ssub |
| 20977 | 0, // dsub2_then_bsub |
| 20978 | 0, // dsub2_then_hsub |
| 20979 | 0, // dsub2_then_ssub |
| 20980 | 0, // qsub1_then_bsub |
| 20981 | 0, // qsub1_then_dsub |
| 20982 | 0, // qsub1_then_hsub |
| 20983 | 0, // qsub1_then_ssub |
| 20984 | 0, // qsub3_then_bsub |
| 20985 | 0, // qsub3_then_dsub |
| 20986 | 0, // qsub3_then_hsub |
| 20987 | 0, // qsub3_then_ssub |
| 20988 | 0, // qsub2_then_bsub |
| 20989 | 0, // qsub2_then_dsub |
| 20990 | 0, // qsub2_then_hsub |
| 20991 | 0, // qsub2_then_ssub |
| 20992 | 63, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20993 | 63, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20994 | 63, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20995 | 63, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20996 | 63, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20997 | 63, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20998 | 63, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 20999 | 0, // subo64_then_sub_32 |
| 21000 | 0, // zsub1_then_bsub |
| 21001 | 0, // zsub1_then_dsub |
| 21002 | 0, // zsub1_then_hsub |
| 21003 | 0, // zsub1_then_ssub |
| 21004 | 0, // zsub1_then_zsub |
| 21005 | 0, // zsub1_then_zsub_hi |
| 21006 | 0, // zsub3_then_bsub |
| 21007 | 0, // zsub3_then_dsub |
| 21008 | 0, // zsub3_then_hsub |
| 21009 | 0, // zsub3_then_ssub |
| 21010 | 0, // zsub3_then_zsub |
| 21011 | 0, // zsub3_then_zsub_hi |
| 21012 | 0, // zsub2_then_bsub |
| 21013 | 0, // zsub2_then_dsub |
| 21014 | 0, // zsub2_then_hsub |
| 21015 | 0, // zsub2_then_ssub |
| 21016 | 0, // zsub2_then_zsub |
| 21017 | 0, // zsub2_then_zsub_hi |
| 21018 | 0, // dsub0_dsub1 |
| 21019 | 0, // dsub0_dsub1_dsub2 |
| 21020 | 0, // dsub1_dsub2 |
| 21021 | 0, // dsub1_dsub2_dsub3 |
| 21022 | 0, // dsub2_dsub3 |
| 21023 | 0, // dsub_qsub1_then_dsub |
| 21024 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21025 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21026 | 0, // qsub0_qsub1 |
| 21027 | 0, // qsub0_qsub1_qsub2 |
| 21028 | 0, // qsub1_qsub2 |
| 21029 | 0, // qsub1_qsub2_qsub3 |
| 21030 | 0, // qsub2_qsub3 |
| 21031 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21032 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21033 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21034 | 63, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21035 | 63, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21036 | 63, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21037 | 63, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21038 | 63, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21039 | 63, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21040 | 63, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21041 | 63, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21042 | 0, // sub_32_subo64_then_sub_32 |
| 21043 | 0, // dsub_zsub1_then_dsub |
| 21044 | 0, // zsub_zsub1_then_zsub |
| 21045 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21046 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21047 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21048 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21049 | 0, // zsub0_zsub1 |
| 21050 | 0, // zsub0_zsub1_zsub2 |
| 21051 | 0, // zsub1_zsub2 |
| 21052 | 0, // zsub1_zsub2_zsub3 |
| 21053 | 0, // zsub2_zsub3 |
| 21054 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21055 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21056 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21057 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21058 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21059 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21060 | }, |
| 21061 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21062 | 0, // bsub |
| 21063 | 0, // dsub |
| 21064 | 0, // dsub0 |
| 21065 | 0, // dsub1 |
| 21066 | 0, // dsub2 |
| 21067 | 0, // dsub3 |
| 21068 | 0, // hsub |
| 21069 | 0, // qhisub |
| 21070 | 0, // qsub |
| 21071 | 0, // qsub0 |
| 21072 | 0, // qsub1 |
| 21073 | 0, // qsub2 |
| 21074 | 0, // qsub3 |
| 21075 | 0, // ssub |
| 21076 | 64, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21077 | 0, // sube32 |
| 21078 | 0, // sube64 |
| 21079 | 0, // subo32 |
| 21080 | 0, // subo64 |
| 21081 | 64, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21082 | 64, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21083 | 64, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21084 | 64, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21085 | 64, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21086 | 64, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21087 | 64, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21088 | 64, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21089 | 0, // zsub |
| 21090 | 0, // zsub0 |
| 21091 | 0, // zsub1 |
| 21092 | 0, // zsub2 |
| 21093 | 0, // zsub3 |
| 21094 | 0, // zsub_hi |
| 21095 | 0, // dsub1_then_bsub |
| 21096 | 0, // dsub1_then_hsub |
| 21097 | 0, // dsub1_then_ssub |
| 21098 | 0, // dsub3_then_bsub |
| 21099 | 0, // dsub3_then_hsub |
| 21100 | 0, // dsub3_then_ssub |
| 21101 | 0, // dsub2_then_bsub |
| 21102 | 0, // dsub2_then_hsub |
| 21103 | 0, // dsub2_then_ssub |
| 21104 | 0, // qsub1_then_bsub |
| 21105 | 0, // qsub1_then_dsub |
| 21106 | 0, // qsub1_then_hsub |
| 21107 | 0, // qsub1_then_ssub |
| 21108 | 0, // qsub3_then_bsub |
| 21109 | 0, // qsub3_then_dsub |
| 21110 | 0, // qsub3_then_hsub |
| 21111 | 0, // qsub3_then_ssub |
| 21112 | 0, // qsub2_then_bsub |
| 21113 | 0, // qsub2_then_dsub |
| 21114 | 0, // qsub2_then_hsub |
| 21115 | 0, // qsub2_then_ssub |
| 21116 | 64, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21117 | 64, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21118 | 64, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21119 | 64, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21120 | 64, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21121 | 64, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21122 | 64, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21123 | 0, // subo64_then_sub_32 |
| 21124 | 0, // zsub1_then_bsub |
| 21125 | 0, // zsub1_then_dsub |
| 21126 | 0, // zsub1_then_hsub |
| 21127 | 0, // zsub1_then_ssub |
| 21128 | 0, // zsub1_then_zsub |
| 21129 | 0, // zsub1_then_zsub_hi |
| 21130 | 0, // zsub3_then_bsub |
| 21131 | 0, // zsub3_then_dsub |
| 21132 | 0, // zsub3_then_hsub |
| 21133 | 0, // zsub3_then_ssub |
| 21134 | 0, // zsub3_then_zsub |
| 21135 | 0, // zsub3_then_zsub_hi |
| 21136 | 0, // zsub2_then_bsub |
| 21137 | 0, // zsub2_then_dsub |
| 21138 | 0, // zsub2_then_hsub |
| 21139 | 0, // zsub2_then_ssub |
| 21140 | 0, // zsub2_then_zsub |
| 21141 | 0, // zsub2_then_zsub_hi |
| 21142 | 0, // dsub0_dsub1 |
| 21143 | 0, // dsub0_dsub1_dsub2 |
| 21144 | 0, // dsub1_dsub2 |
| 21145 | 0, // dsub1_dsub2_dsub3 |
| 21146 | 0, // dsub2_dsub3 |
| 21147 | 0, // dsub_qsub1_then_dsub |
| 21148 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21149 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21150 | 0, // qsub0_qsub1 |
| 21151 | 0, // qsub0_qsub1_qsub2 |
| 21152 | 0, // qsub1_qsub2 |
| 21153 | 0, // qsub1_qsub2_qsub3 |
| 21154 | 0, // qsub2_qsub3 |
| 21155 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21156 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21157 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21158 | 64, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21159 | 64, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21160 | 64, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21161 | 64, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21162 | 64, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21163 | 64, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21164 | 64, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21165 | 64, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 21166 | 0, // sub_32_subo64_then_sub_32 |
| 21167 | 0, // dsub_zsub1_then_dsub |
| 21168 | 0, // zsub_zsub1_then_zsub |
| 21169 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21170 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21171 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21172 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21173 | 0, // zsub0_zsub1 |
| 21174 | 0, // zsub0_zsub1_zsub2 |
| 21175 | 0, // zsub1_zsub2 |
| 21176 | 0, // zsub1_zsub2_zsub3 |
| 21177 | 0, // zsub2_zsub3 |
| 21178 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21179 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21180 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21181 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21182 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21183 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21184 | }, |
| 21185 | { // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21186 | 0, // bsub |
| 21187 | 0, // dsub |
| 21188 | 0, // dsub0 |
| 21189 | 0, // dsub1 |
| 21190 | 0, // dsub2 |
| 21191 | 0, // dsub3 |
| 21192 | 0, // hsub |
| 21193 | 0, // qhisub |
| 21194 | 0, // qsub |
| 21195 | 0, // qsub0 |
| 21196 | 0, // qsub1 |
| 21197 | 0, // qsub2 |
| 21198 | 0, // qsub3 |
| 21199 | 0, // ssub |
| 21200 | 65, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21201 | 0, // sube32 |
| 21202 | 0, // sube64 |
| 21203 | 0, // subo32 |
| 21204 | 0, // subo64 |
| 21205 | 65, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21206 | 65, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21207 | 65, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21208 | 65, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21209 | 65, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21210 | 65, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21211 | 65, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21212 | 65, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21213 | 0, // zsub |
| 21214 | 0, // zsub0 |
| 21215 | 0, // zsub1 |
| 21216 | 0, // zsub2 |
| 21217 | 0, // zsub3 |
| 21218 | 0, // zsub_hi |
| 21219 | 0, // dsub1_then_bsub |
| 21220 | 0, // dsub1_then_hsub |
| 21221 | 0, // dsub1_then_ssub |
| 21222 | 0, // dsub3_then_bsub |
| 21223 | 0, // dsub3_then_hsub |
| 21224 | 0, // dsub3_then_ssub |
| 21225 | 0, // dsub2_then_bsub |
| 21226 | 0, // dsub2_then_hsub |
| 21227 | 0, // dsub2_then_ssub |
| 21228 | 0, // qsub1_then_bsub |
| 21229 | 0, // qsub1_then_dsub |
| 21230 | 0, // qsub1_then_hsub |
| 21231 | 0, // qsub1_then_ssub |
| 21232 | 0, // qsub3_then_bsub |
| 21233 | 0, // qsub3_then_dsub |
| 21234 | 0, // qsub3_then_hsub |
| 21235 | 0, // qsub3_then_ssub |
| 21236 | 0, // qsub2_then_bsub |
| 21237 | 0, // qsub2_then_dsub |
| 21238 | 0, // qsub2_then_hsub |
| 21239 | 0, // qsub2_then_ssub |
| 21240 | 65, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21241 | 65, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21242 | 65, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21243 | 65, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21244 | 65, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21245 | 65, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21246 | 65, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21247 | 0, // subo64_then_sub_32 |
| 21248 | 0, // zsub1_then_bsub |
| 21249 | 0, // zsub1_then_dsub |
| 21250 | 0, // zsub1_then_hsub |
| 21251 | 0, // zsub1_then_ssub |
| 21252 | 0, // zsub1_then_zsub |
| 21253 | 0, // zsub1_then_zsub_hi |
| 21254 | 0, // zsub3_then_bsub |
| 21255 | 0, // zsub3_then_dsub |
| 21256 | 0, // zsub3_then_hsub |
| 21257 | 0, // zsub3_then_ssub |
| 21258 | 0, // zsub3_then_zsub |
| 21259 | 0, // zsub3_then_zsub_hi |
| 21260 | 0, // zsub2_then_bsub |
| 21261 | 0, // zsub2_then_dsub |
| 21262 | 0, // zsub2_then_hsub |
| 21263 | 0, // zsub2_then_ssub |
| 21264 | 0, // zsub2_then_zsub |
| 21265 | 0, // zsub2_then_zsub_hi |
| 21266 | 0, // dsub0_dsub1 |
| 21267 | 0, // dsub0_dsub1_dsub2 |
| 21268 | 0, // dsub1_dsub2 |
| 21269 | 0, // dsub1_dsub2_dsub3 |
| 21270 | 0, // dsub2_dsub3 |
| 21271 | 0, // dsub_qsub1_then_dsub |
| 21272 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21273 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21274 | 0, // qsub0_qsub1 |
| 21275 | 0, // qsub0_qsub1_qsub2 |
| 21276 | 0, // qsub1_qsub2 |
| 21277 | 0, // qsub1_qsub2_qsub3 |
| 21278 | 0, // qsub2_qsub3 |
| 21279 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21280 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21281 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21282 | 65, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21283 | 65, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21284 | 65, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21285 | 65, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21286 | 65, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21287 | 65, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21288 | 65, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21289 | 65, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21290 | 0, // sub_32_subo64_then_sub_32 |
| 21291 | 0, // dsub_zsub1_then_dsub |
| 21292 | 0, // zsub_zsub1_then_zsub |
| 21293 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21294 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21295 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21296 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21297 | 0, // zsub0_zsub1 |
| 21298 | 0, // zsub0_zsub1_zsub2 |
| 21299 | 0, // zsub1_zsub2 |
| 21300 | 0, // zsub1_zsub2_zsub3 |
| 21301 | 0, // zsub2_zsub3 |
| 21302 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21303 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21304 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21305 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21306 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21307 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21308 | }, |
| 21309 | { // GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21310 | 0, // bsub |
| 21311 | 0, // dsub |
| 21312 | 0, // dsub0 |
| 21313 | 0, // dsub1 |
| 21314 | 0, // dsub2 |
| 21315 | 0, // dsub3 |
| 21316 | 0, // hsub |
| 21317 | 0, // qhisub |
| 21318 | 0, // qsub |
| 21319 | 0, // qsub0 |
| 21320 | 0, // qsub1 |
| 21321 | 0, // qsub2 |
| 21322 | 0, // qsub3 |
| 21323 | 0, // ssub |
| 21324 | 66, // sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21325 | 0, // sube32 |
| 21326 | 0, // sube64 |
| 21327 | 0, // subo32 |
| 21328 | 0, // subo64 |
| 21329 | 66, // x8sub_0 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21330 | 66, // x8sub_1 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21331 | 66, // x8sub_2 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21332 | 66, // x8sub_3 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21333 | 66, // x8sub_4 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21334 | 66, // x8sub_5 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21335 | 66, // x8sub_6 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21336 | 66, // x8sub_7 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21337 | 0, // zsub |
| 21338 | 0, // zsub0 |
| 21339 | 0, // zsub1 |
| 21340 | 0, // zsub2 |
| 21341 | 0, // zsub3 |
| 21342 | 0, // zsub_hi |
| 21343 | 0, // dsub1_then_bsub |
| 21344 | 0, // dsub1_then_hsub |
| 21345 | 0, // dsub1_then_ssub |
| 21346 | 0, // dsub3_then_bsub |
| 21347 | 0, // dsub3_then_hsub |
| 21348 | 0, // dsub3_then_ssub |
| 21349 | 0, // dsub2_then_bsub |
| 21350 | 0, // dsub2_then_hsub |
| 21351 | 0, // dsub2_then_ssub |
| 21352 | 0, // qsub1_then_bsub |
| 21353 | 0, // qsub1_then_dsub |
| 21354 | 0, // qsub1_then_hsub |
| 21355 | 0, // qsub1_then_ssub |
| 21356 | 0, // qsub3_then_bsub |
| 21357 | 0, // qsub3_then_dsub |
| 21358 | 0, // qsub3_then_hsub |
| 21359 | 0, // qsub3_then_ssub |
| 21360 | 0, // qsub2_then_bsub |
| 21361 | 0, // qsub2_then_dsub |
| 21362 | 0, // qsub2_then_hsub |
| 21363 | 0, // qsub2_then_ssub |
| 21364 | 66, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21365 | 66, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21366 | 66, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21367 | 66, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21368 | 66, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21369 | 66, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21370 | 66, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21371 | 0, // subo64_then_sub_32 |
| 21372 | 0, // zsub1_then_bsub |
| 21373 | 0, // zsub1_then_dsub |
| 21374 | 0, // zsub1_then_hsub |
| 21375 | 0, // zsub1_then_ssub |
| 21376 | 0, // zsub1_then_zsub |
| 21377 | 0, // zsub1_then_zsub_hi |
| 21378 | 0, // zsub3_then_bsub |
| 21379 | 0, // zsub3_then_dsub |
| 21380 | 0, // zsub3_then_hsub |
| 21381 | 0, // zsub3_then_ssub |
| 21382 | 0, // zsub3_then_zsub |
| 21383 | 0, // zsub3_then_zsub_hi |
| 21384 | 0, // zsub2_then_bsub |
| 21385 | 0, // zsub2_then_dsub |
| 21386 | 0, // zsub2_then_hsub |
| 21387 | 0, // zsub2_then_ssub |
| 21388 | 0, // zsub2_then_zsub |
| 21389 | 0, // zsub2_then_zsub_hi |
| 21390 | 0, // dsub0_dsub1 |
| 21391 | 0, // dsub0_dsub1_dsub2 |
| 21392 | 0, // dsub1_dsub2 |
| 21393 | 0, // dsub1_dsub2_dsub3 |
| 21394 | 0, // dsub2_dsub3 |
| 21395 | 0, // dsub_qsub1_then_dsub |
| 21396 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21397 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21398 | 0, // qsub0_qsub1 |
| 21399 | 0, // qsub0_qsub1_qsub2 |
| 21400 | 0, // qsub1_qsub2 |
| 21401 | 0, // qsub1_qsub2_qsub3 |
| 21402 | 0, // qsub2_qsub3 |
| 21403 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21404 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21405 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21406 | 66, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21407 | 66, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21408 | 66, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21409 | 66, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21410 | 66, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21411 | 66, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21412 | 66, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21413 | 66, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 21414 | 0, // sub_32_subo64_then_sub_32 |
| 21415 | 0, // dsub_zsub1_then_dsub |
| 21416 | 0, // zsub_zsub1_then_zsub |
| 21417 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21418 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21419 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21420 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21421 | 0, // zsub0_zsub1 |
| 21422 | 0, // zsub0_zsub1_zsub2 |
| 21423 | 0, // zsub1_zsub2 |
| 21424 | 0, // zsub1_zsub2_zsub3 |
| 21425 | 0, // zsub2_zsub3 |
| 21426 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21427 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21428 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21429 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21430 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21431 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21432 | }, |
| 21433 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21434 | 0, // bsub |
| 21435 | 0, // dsub |
| 21436 | 0, // dsub0 |
| 21437 | 0, // dsub1 |
| 21438 | 0, // dsub2 |
| 21439 | 0, // dsub3 |
| 21440 | 0, // hsub |
| 21441 | 0, // qhisub |
| 21442 | 0, // qsub |
| 21443 | 0, // qsub0 |
| 21444 | 0, // qsub1 |
| 21445 | 0, // qsub2 |
| 21446 | 0, // qsub3 |
| 21447 | 0, // ssub |
| 21448 | 67, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21449 | 0, // sube32 |
| 21450 | 0, // sube64 |
| 21451 | 0, // subo32 |
| 21452 | 0, // subo64 |
| 21453 | 67, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21454 | 67, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21455 | 67, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21456 | 67, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21457 | 67, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21458 | 67, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21459 | 67, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21460 | 67, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21461 | 0, // zsub |
| 21462 | 0, // zsub0 |
| 21463 | 0, // zsub1 |
| 21464 | 0, // zsub2 |
| 21465 | 0, // zsub3 |
| 21466 | 0, // zsub_hi |
| 21467 | 0, // dsub1_then_bsub |
| 21468 | 0, // dsub1_then_hsub |
| 21469 | 0, // dsub1_then_ssub |
| 21470 | 0, // dsub3_then_bsub |
| 21471 | 0, // dsub3_then_hsub |
| 21472 | 0, // dsub3_then_ssub |
| 21473 | 0, // dsub2_then_bsub |
| 21474 | 0, // dsub2_then_hsub |
| 21475 | 0, // dsub2_then_ssub |
| 21476 | 0, // qsub1_then_bsub |
| 21477 | 0, // qsub1_then_dsub |
| 21478 | 0, // qsub1_then_hsub |
| 21479 | 0, // qsub1_then_ssub |
| 21480 | 0, // qsub3_then_bsub |
| 21481 | 0, // qsub3_then_dsub |
| 21482 | 0, // qsub3_then_hsub |
| 21483 | 0, // qsub3_then_ssub |
| 21484 | 0, // qsub2_then_bsub |
| 21485 | 0, // qsub2_then_dsub |
| 21486 | 0, // qsub2_then_hsub |
| 21487 | 0, // qsub2_then_ssub |
| 21488 | 67, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21489 | 67, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21490 | 67, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21491 | 67, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21492 | 67, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21493 | 67, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21494 | 67, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21495 | 0, // subo64_then_sub_32 |
| 21496 | 0, // zsub1_then_bsub |
| 21497 | 0, // zsub1_then_dsub |
| 21498 | 0, // zsub1_then_hsub |
| 21499 | 0, // zsub1_then_ssub |
| 21500 | 0, // zsub1_then_zsub |
| 21501 | 0, // zsub1_then_zsub_hi |
| 21502 | 0, // zsub3_then_bsub |
| 21503 | 0, // zsub3_then_dsub |
| 21504 | 0, // zsub3_then_hsub |
| 21505 | 0, // zsub3_then_ssub |
| 21506 | 0, // zsub3_then_zsub |
| 21507 | 0, // zsub3_then_zsub_hi |
| 21508 | 0, // zsub2_then_bsub |
| 21509 | 0, // zsub2_then_dsub |
| 21510 | 0, // zsub2_then_hsub |
| 21511 | 0, // zsub2_then_ssub |
| 21512 | 0, // zsub2_then_zsub |
| 21513 | 0, // zsub2_then_zsub_hi |
| 21514 | 0, // dsub0_dsub1 |
| 21515 | 0, // dsub0_dsub1_dsub2 |
| 21516 | 0, // dsub1_dsub2 |
| 21517 | 0, // dsub1_dsub2_dsub3 |
| 21518 | 0, // dsub2_dsub3 |
| 21519 | 0, // dsub_qsub1_then_dsub |
| 21520 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21521 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21522 | 0, // qsub0_qsub1 |
| 21523 | 0, // qsub0_qsub1_qsub2 |
| 21524 | 0, // qsub1_qsub2 |
| 21525 | 0, // qsub1_qsub2_qsub3 |
| 21526 | 0, // qsub2_qsub3 |
| 21527 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21528 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21529 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21530 | 67, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21531 | 67, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21532 | 67, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21533 | 67, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21534 | 67, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21535 | 67, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21536 | 67, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21537 | 67, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21538 | 0, // sub_32_subo64_then_sub_32 |
| 21539 | 0, // dsub_zsub1_then_dsub |
| 21540 | 0, // zsub_zsub1_then_zsub |
| 21541 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21542 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21543 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21544 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21545 | 0, // zsub0_zsub1 |
| 21546 | 0, // zsub0_zsub1_zsub2 |
| 21547 | 0, // zsub1_zsub2 |
| 21548 | 0, // zsub1_zsub2_zsub3 |
| 21549 | 0, // zsub2_zsub3 |
| 21550 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21551 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21552 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21553 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21554 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21555 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21556 | }, |
| 21557 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21558 | 0, // bsub |
| 21559 | 0, // dsub |
| 21560 | 0, // dsub0 |
| 21561 | 0, // dsub1 |
| 21562 | 0, // dsub2 |
| 21563 | 0, // dsub3 |
| 21564 | 0, // hsub |
| 21565 | 0, // qhisub |
| 21566 | 0, // qsub |
| 21567 | 0, // qsub0 |
| 21568 | 0, // qsub1 |
| 21569 | 0, // qsub2 |
| 21570 | 0, // qsub3 |
| 21571 | 0, // ssub |
| 21572 | 68, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21573 | 0, // sube32 |
| 21574 | 0, // sube64 |
| 21575 | 0, // subo32 |
| 21576 | 0, // subo64 |
| 21577 | 68, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21578 | 68, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21579 | 68, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21580 | 68, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21581 | 68, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21582 | 68, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21583 | 68, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21584 | 68, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21585 | 0, // zsub |
| 21586 | 0, // zsub0 |
| 21587 | 0, // zsub1 |
| 21588 | 0, // zsub2 |
| 21589 | 0, // zsub3 |
| 21590 | 0, // zsub_hi |
| 21591 | 0, // dsub1_then_bsub |
| 21592 | 0, // dsub1_then_hsub |
| 21593 | 0, // dsub1_then_ssub |
| 21594 | 0, // dsub3_then_bsub |
| 21595 | 0, // dsub3_then_hsub |
| 21596 | 0, // dsub3_then_ssub |
| 21597 | 0, // dsub2_then_bsub |
| 21598 | 0, // dsub2_then_hsub |
| 21599 | 0, // dsub2_then_ssub |
| 21600 | 0, // qsub1_then_bsub |
| 21601 | 0, // qsub1_then_dsub |
| 21602 | 0, // qsub1_then_hsub |
| 21603 | 0, // qsub1_then_ssub |
| 21604 | 0, // qsub3_then_bsub |
| 21605 | 0, // qsub3_then_dsub |
| 21606 | 0, // qsub3_then_hsub |
| 21607 | 0, // qsub3_then_ssub |
| 21608 | 0, // qsub2_then_bsub |
| 21609 | 0, // qsub2_then_dsub |
| 21610 | 0, // qsub2_then_hsub |
| 21611 | 0, // qsub2_then_ssub |
| 21612 | 68, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21613 | 68, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21614 | 68, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21615 | 68, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21616 | 68, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21617 | 68, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21618 | 68, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21619 | 0, // subo64_then_sub_32 |
| 21620 | 0, // zsub1_then_bsub |
| 21621 | 0, // zsub1_then_dsub |
| 21622 | 0, // zsub1_then_hsub |
| 21623 | 0, // zsub1_then_ssub |
| 21624 | 0, // zsub1_then_zsub |
| 21625 | 0, // zsub1_then_zsub_hi |
| 21626 | 0, // zsub3_then_bsub |
| 21627 | 0, // zsub3_then_dsub |
| 21628 | 0, // zsub3_then_hsub |
| 21629 | 0, // zsub3_then_ssub |
| 21630 | 0, // zsub3_then_zsub |
| 21631 | 0, // zsub3_then_zsub_hi |
| 21632 | 0, // zsub2_then_bsub |
| 21633 | 0, // zsub2_then_dsub |
| 21634 | 0, // zsub2_then_hsub |
| 21635 | 0, // zsub2_then_ssub |
| 21636 | 0, // zsub2_then_zsub |
| 21637 | 0, // zsub2_then_zsub_hi |
| 21638 | 0, // dsub0_dsub1 |
| 21639 | 0, // dsub0_dsub1_dsub2 |
| 21640 | 0, // dsub1_dsub2 |
| 21641 | 0, // dsub1_dsub2_dsub3 |
| 21642 | 0, // dsub2_dsub3 |
| 21643 | 0, // dsub_qsub1_then_dsub |
| 21644 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21645 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21646 | 0, // qsub0_qsub1 |
| 21647 | 0, // qsub0_qsub1_qsub2 |
| 21648 | 0, // qsub1_qsub2 |
| 21649 | 0, // qsub1_qsub2_qsub3 |
| 21650 | 0, // qsub2_qsub3 |
| 21651 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21652 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21653 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21654 | 68, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21655 | 68, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21656 | 68, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21657 | 68, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21658 | 68, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21659 | 68, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21660 | 68, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21661 | 68, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21662 | 0, // sub_32_subo64_then_sub_32 |
| 21663 | 0, // dsub_zsub1_then_dsub |
| 21664 | 0, // zsub_zsub1_then_zsub |
| 21665 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21666 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21667 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21668 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21669 | 0, // zsub0_zsub1 |
| 21670 | 0, // zsub0_zsub1_zsub2 |
| 21671 | 0, // zsub1_zsub2 |
| 21672 | 0, // zsub1_zsub2_zsub3 |
| 21673 | 0, // zsub2_zsub3 |
| 21674 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21675 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21676 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21677 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21678 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21679 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21680 | }, |
| 21681 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21682 | 0, // bsub |
| 21683 | 0, // dsub |
| 21684 | 0, // dsub0 |
| 21685 | 0, // dsub1 |
| 21686 | 0, // dsub2 |
| 21687 | 0, // dsub3 |
| 21688 | 0, // hsub |
| 21689 | 0, // qhisub |
| 21690 | 0, // qsub |
| 21691 | 0, // qsub0 |
| 21692 | 0, // qsub1 |
| 21693 | 0, // qsub2 |
| 21694 | 0, // qsub3 |
| 21695 | 0, // ssub |
| 21696 | 69, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21697 | 0, // sube32 |
| 21698 | 0, // sube64 |
| 21699 | 0, // subo32 |
| 21700 | 0, // subo64 |
| 21701 | 69, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21702 | 69, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21703 | 69, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21704 | 69, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21705 | 69, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21706 | 69, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21707 | 69, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21708 | 69, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21709 | 0, // zsub |
| 21710 | 0, // zsub0 |
| 21711 | 0, // zsub1 |
| 21712 | 0, // zsub2 |
| 21713 | 0, // zsub3 |
| 21714 | 0, // zsub_hi |
| 21715 | 0, // dsub1_then_bsub |
| 21716 | 0, // dsub1_then_hsub |
| 21717 | 0, // dsub1_then_ssub |
| 21718 | 0, // dsub3_then_bsub |
| 21719 | 0, // dsub3_then_hsub |
| 21720 | 0, // dsub3_then_ssub |
| 21721 | 0, // dsub2_then_bsub |
| 21722 | 0, // dsub2_then_hsub |
| 21723 | 0, // dsub2_then_ssub |
| 21724 | 0, // qsub1_then_bsub |
| 21725 | 0, // qsub1_then_dsub |
| 21726 | 0, // qsub1_then_hsub |
| 21727 | 0, // qsub1_then_ssub |
| 21728 | 0, // qsub3_then_bsub |
| 21729 | 0, // qsub3_then_dsub |
| 21730 | 0, // qsub3_then_hsub |
| 21731 | 0, // qsub3_then_ssub |
| 21732 | 0, // qsub2_then_bsub |
| 21733 | 0, // qsub2_then_dsub |
| 21734 | 0, // qsub2_then_hsub |
| 21735 | 0, // qsub2_then_ssub |
| 21736 | 69, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21737 | 69, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21738 | 69, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21739 | 69, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21740 | 69, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21741 | 69, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21742 | 69, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21743 | 0, // subo64_then_sub_32 |
| 21744 | 0, // zsub1_then_bsub |
| 21745 | 0, // zsub1_then_dsub |
| 21746 | 0, // zsub1_then_hsub |
| 21747 | 0, // zsub1_then_ssub |
| 21748 | 0, // zsub1_then_zsub |
| 21749 | 0, // zsub1_then_zsub_hi |
| 21750 | 0, // zsub3_then_bsub |
| 21751 | 0, // zsub3_then_dsub |
| 21752 | 0, // zsub3_then_hsub |
| 21753 | 0, // zsub3_then_ssub |
| 21754 | 0, // zsub3_then_zsub |
| 21755 | 0, // zsub3_then_zsub_hi |
| 21756 | 0, // zsub2_then_bsub |
| 21757 | 0, // zsub2_then_dsub |
| 21758 | 0, // zsub2_then_hsub |
| 21759 | 0, // zsub2_then_ssub |
| 21760 | 0, // zsub2_then_zsub |
| 21761 | 0, // zsub2_then_zsub_hi |
| 21762 | 0, // dsub0_dsub1 |
| 21763 | 0, // dsub0_dsub1_dsub2 |
| 21764 | 0, // dsub1_dsub2 |
| 21765 | 0, // dsub1_dsub2_dsub3 |
| 21766 | 0, // dsub2_dsub3 |
| 21767 | 0, // dsub_qsub1_then_dsub |
| 21768 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21769 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21770 | 0, // qsub0_qsub1 |
| 21771 | 0, // qsub0_qsub1_qsub2 |
| 21772 | 0, // qsub1_qsub2 |
| 21773 | 0, // qsub1_qsub2_qsub3 |
| 21774 | 0, // qsub2_qsub3 |
| 21775 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21776 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21777 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21778 | 69, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21779 | 69, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21780 | 69, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21781 | 69, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21782 | 69, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21783 | 69, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21784 | 69, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21785 | 69, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21786 | 0, // sub_32_subo64_then_sub_32 |
| 21787 | 0, // dsub_zsub1_then_dsub |
| 21788 | 0, // zsub_zsub1_then_zsub |
| 21789 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21790 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21791 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21792 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21793 | 0, // zsub0_zsub1 |
| 21794 | 0, // zsub0_zsub1_zsub2 |
| 21795 | 0, // zsub1_zsub2 |
| 21796 | 0, // zsub1_zsub2_zsub3 |
| 21797 | 0, // zsub2_zsub3 |
| 21798 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21799 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21800 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21801 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21802 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21803 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21804 | }, |
| 21805 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21806 | 0, // bsub |
| 21807 | 0, // dsub |
| 21808 | 0, // dsub0 |
| 21809 | 0, // dsub1 |
| 21810 | 0, // dsub2 |
| 21811 | 0, // dsub3 |
| 21812 | 0, // hsub |
| 21813 | 0, // qhisub |
| 21814 | 0, // qsub |
| 21815 | 0, // qsub0 |
| 21816 | 0, // qsub1 |
| 21817 | 0, // qsub2 |
| 21818 | 0, // qsub3 |
| 21819 | 0, // ssub |
| 21820 | 70, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21821 | 0, // sube32 |
| 21822 | 0, // sube64 |
| 21823 | 0, // subo32 |
| 21824 | 0, // subo64 |
| 21825 | 70, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21826 | 70, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21827 | 70, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21828 | 70, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21829 | 70, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21830 | 70, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21831 | 70, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21832 | 70, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21833 | 0, // zsub |
| 21834 | 0, // zsub0 |
| 21835 | 0, // zsub1 |
| 21836 | 0, // zsub2 |
| 21837 | 0, // zsub3 |
| 21838 | 0, // zsub_hi |
| 21839 | 0, // dsub1_then_bsub |
| 21840 | 0, // dsub1_then_hsub |
| 21841 | 0, // dsub1_then_ssub |
| 21842 | 0, // dsub3_then_bsub |
| 21843 | 0, // dsub3_then_hsub |
| 21844 | 0, // dsub3_then_ssub |
| 21845 | 0, // dsub2_then_bsub |
| 21846 | 0, // dsub2_then_hsub |
| 21847 | 0, // dsub2_then_ssub |
| 21848 | 0, // qsub1_then_bsub |
| 21849 | 0, // qsub1_then_dsub |
| 21850 | 0, // qsub1_then_hsub |
| 21851 | 0, // qsub1_then_ssub |
| 21852 | 0, // qsub3_then_bsub |
| 21853 | 0, // qsub3_then_dsub |
| 21854 | 0, // qsub3_then_hsub |
| 21855 | 0, // qsub3_then_ssub |
| 21856 | 0, // qsub2_then_bsub |
| 21857 | 0, // qsub2_then_dsub |
| 21858 | 0, // qsub2_then_hsub |
| 21859 | 0, // qsub2_then_ssub |
| 21860 | 70, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21861 | 70, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21862 | 70, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21863 | 70, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21864 | 70, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21865 | 70, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21866 | 70, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21867 | 0, // subo64_then_sub_32 |
| 21868 | 0, // zsub1_then_bsub |
| 21869 | 0, // zsub1_then_dsub |
| 21870 | 0, // zsub1_then_hsub |
| 21871 | 0, // zsub1_then_ssub |
| 21872 | 0, // zsub1_then_zsub |
| 21873 | 0, // zsub1_then_zsub_hi |
| 21874 | 0, // zsub3_then_bsub |
| 21875 | 0, // zsub3_then_dsub |
| 21876 | 0, // zsub3_then_hsub |
| 21877 | 0, // zsub3_then_ssub |
| 21878 | 0, // zsub3_then_zsub |
| 21879 | 0, // zsub3_then_zsub_hi |
| 21880 | 0, // zsub2_then_bsub |
| 21881 | 0, // zsub2_then_dsub |
| 21882 | 0, // zsub2_then_hsub |
| 21883 | 0, // zsub2_then_ssub |
| 21884 | 0, // zsub2_then_zsub |
| 21885 | 0, // zsub2_then_zsub_hi |
| 21886 | 0, // dsub0_dsub1 |
| 21887 | 0, // dsub0_dsub1_dsub2 |
| 21888 | 0, // dsub1_dsub2 |
| 21889 | 0, // dsub1_dsub2_dsub3 |
| 21890 | 0, // dsub2_dsub3 |
| 21891 | 0, // dsub_qsub1_then_dsub |
| 21892 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21893 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 21894 | 0, // qsub0_qsub1 |
| 21895 | 0, // qsub0_qsub1_qsub2 |
| 21896 | 0, // qsub1_qsub2 |
| 21897 | 0, // qsub1_qsub2_qsub3 |
| 21898 | 0, // qsub2_qsub3 |
| 21899 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 21900 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 21901 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 21902 | 70, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21903 | 70, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21904 | 70, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21905 | 70, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21906 | 70, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21907 | 70, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21908 | 70, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21909 | 70, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 21910 | 0, // sub_32_subo64_then_sub_32 |
| 21911 | 0, // dsub_zsub1_then_dsub |
| 21912 | 0, // zsub_zsub1_then_zsub |
| 21913 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21914 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 21915 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21916 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 21917 | 0, // zsub0_zsub1 |
| 21918 | 0, // zsub0_zsub1_zsub2 |
| 21919 | 0, // zsub1_zsub2 |
| 21920 | 0, // zsub1_zsub2_zsub3 |
| 21921 | 0, // zsub2_zsub3 |
| 21922 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 21923 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 21924 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 21925 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 21926 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 21927 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 21928 | }, |
| 21929 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21930 | 0, // bsub |
| 21931 | 0, // dsub |
| 21932 | 0, // dsub0 |
| 21933 | 0, // dsub1 |
| 21934 | 0, // dsub2 |
| 21935 | 0, // dsub3 |
| 21936 | 0, // hsub |
| 21937 | 0, // qhisub |
| 21938 | 0, // qsub |
| 21939 | 0, // qsub0 |
| 21940 | 0, // qsub1 |
| 21941 | 0, // qsub2 |
| 21942 | 0, // qsub3 |
| 21943 | 0, // ssub |
| 21944 | 71, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21945 | 0, // sube32 |
| 21946 | 0, // sube64 |
| 21947 | 0, // subo32 |
| 21948 | 0, // subo64 |
| 21949 | 71, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21950 | 71, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21951 | 71, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21952 | 71, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21953 | 71, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21954 | 71, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21955 | 71, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21956 | 71, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21957 | 0, // zsub |
| 21958 | 0, // zsub0 |
| 21959 | 0, // zsub1 |
| 21960 | 0, // zsub2 |
| 21961 | 0, // zsub3 |
| 21962 | 0, // zsub_hi |
| 21963 | 0, // dsub1_then_bsub |
| 21964 | 0, // dsub1_then_hsub |
| 21965 | 0, // dsub1_then_ssub |
| 21966 | 0, // dsub3_then_bsub |
| 21967 | 0, // dsub3_then_hsub |
| 21968 | 0, // dsub3_then_ssub |
| 21969 | 0, // dsub2_then_bsub |
| 21970 | 0, // dsub2_then_hsub |
| 21971 | 0, // dsub2_then_ssub |
| 21972 | 0, // qsub1_then_bsub |
| 21973 | 0, // qsub1_then_dsub |
| 21974 | 0, // qsub1_then_hsub |
| 21975 | 0, // qsub1_then_ssub |
| 21976 | 0, // qsub3_then_bsub |
| 21977 | 0, // qsub3_then_dsub |
| 21978 | 0, // qsub3_then_hsub |
| 21979 | 0, // qsub3_then_ssub |
| 21980 | 0, // qsub2_then_bsub |
| 21981 | 0, // qsub2_then_dsub |
| 21982 | 0, // qsub2_then_hsub |
| 21983 | 0, // qsub2_then_ssub |
| 21984 | 71, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21985 | 71, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21986 | 71, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21987 | 71, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21988 | 71, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21989 | 71, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21990 | 71, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 21991 | 0, // subo64_then_sub_32 |
| 21992 | 0, // zsub1_then_bsub |
| 21993 | 0, // zsub1_then_dsub |
| 21994 | 0, // zsub1_then_hsub |
| 21995 | 0, // zsub1_then_ssub |
| 21996 | 0, // zsub1_then_zsub |
| 21997 | 0, // zsub1_then_zsub_hi |
| 21998 | 0, // zsub3_then_bsub |
| 21999 | 0, // zsub3_then_dsub |
| 22000 | 0, // zsub3_then_hsub |
| 22001 | 0, // zsub3_then_ssub |
| 22002 | 0, // zsub3_then_zsub |
| 22003 | 0, // zsub3_then_zsub_hi |
| 22004 | 0, // zsub2_then_bsub |
| 22005 | 0, // zsub2_then_dsub |
| 22006 | 0, // zsub2_then_hsub |
| 22007 | 0, // zsub2_then_ssub |
| 22008 | 0, // zsub2_then_zsub |
| 22009 | 0, // zsub2_then_zsub_hi |
| 22010 | 0, // dsub0_dsub1 |
| 22011 | 0, // dsub0_dsub1_dsub2 |
| 22012 | 0, // dsub1_dsub2 |
| 22013 | 0, // dsub1_dsub2_dsub3 |
| 22014 | 0, // dsub2_dsub3 |
| 22015 | 0, // dsub_qsub1_then_dsub |
| 22016 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22017 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22018 | 0, // qsub0_qsub1 |
| 22019 | 0, // qsub0_qsub1_qsub2 |
| 22020 | 0, // qsub1_qsub2 |
| 22021 | 0, // qsub1_qsub2_qsub3 |
| 22022 | 0, // qsub2_qsub3 |
| 22023 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22024 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22025 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22026 | 71, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22027 | 71, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22028 | 71, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22029 | 71, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22030 | 71, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22031 | 71, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22032 | 71, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22033 | 71, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22034 | 0, // sub_32_subo64_then_sub_32 |
| 22035 | 0, // dsub_zsub1_then_dsub |
| 22036 | 0, // zsub_zsub1_then_zsub |
| 22037 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22038 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22039 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22040 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22041 | 0, // zsub0_zsub1 |
| 22042 | 0, // zsub0_zsub1_zsub2 |
| 22043 | 0, // zsub1_zsub2 |
| 22044 | 0, // zsub1_zsub2_zsub3 |
| 22045 | 0, // zsub2_zsub3 |
| 22046 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22047 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22048 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22049 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22050 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22051 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22052 | }, |
| 22053 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22054 | 0, // bsub |
| 22055 | 0, // dsub |
| 22056 | 0, // dsub0 |
| 22057 | 0, // dsub1 |
| 22058 | 0, // dsub2 |
| 22059 | 0, // dsub3 |
| 22060 | 0, // hsub |
| 22061 | 0, // qhisub |
| 22062 | 0, // qsub |
| 22063 | 0, // qsub0 |
| 22064 | 0, // qsub1 |
| 22065 | 0, // qsub2 |
| 22066 | 0, // qsub3 |
| 22067 | 0, // ssub |
| 22068 | 72, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22069 | 0, // sube32 |
| 22070 | 0, // sube64 |
| 22071 | 0, // subo32 |
| 22072 | 0, // subo64 |
| 22073 | 72, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22074 | 72, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22075 | 72, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22076 | 72, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22077 | 72, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22078 | 72, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22079 | 72, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22080 | 72, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22081 | 0, // zsub |
| 22082 | 0, // zsub0 |
| 22083 | 0, // zsub1 |
| 22084 | 0, // zsub2 |
| 22085 | 0, // zsub3 |
| 22086 | 0, // zsub_hi |
| 22087 | 0, // dsub1_then_bsub |
| 22088 | 0, // dsub1_then_hsub |
| 22089 | 0, // dsub1_then_ssub |
| 22090 | 0, // dsub3_then_bsub |
| 22091 | 0, // dsub3_then_hsub |
| 22092 | 0, // dsub3_then_ssub |
| 22093 | 0, // dsub2_then_bsub |
| 22094 | 0, // dsub2_then_hsub |
| 22095 | 0, // dsub2_then_ssub |
| 22096 | 0, // qsub1_then_bsub |
| 22097 | 0, // qsub1_then_dsub |
| 22098 | 0, // qsub1_then_hsub |
| 22099 | 0, // qsub1_then_ssub |
| 22100 | 0, // qsub3_then_bsub |
| 22101 | 0, // qsub3_then_dsub |
| 22102 | 0, // qsub3_then_hsub |
| 22103 | 0, // qsub3_then_ssub |
| 22104 | 0, // qsub2_then_bsub |
| 22105 | 0, // qsub2_then_dsub |
| 22106 | 0, // qsub2_then_hsub |
| 22107 | 0, // qsub2_then_ssub |
| 22108 | 72, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22109 | 72, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22110 | 72, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22111 | 72, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22112 | 72, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22113 | 72, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22114 | 72, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22115 | 0, // subo64_then_sub_32 |
| 22116 | 0, // zsub1_then_bsub |
| 22117 | 0, // zsub1_then_dsub |
| 22118 | 0, // zsub1_then_hsub |
| 22119 | 0, // zsub1_then_ssub |
| 22120 | 0, // zsub1_then_zsub |
| 22121 | 0, // zsub1_then_zsub_hi |
| 22122 | 0, // zsub3_then_bsub |
| 22123 | 0, // zsub3_then_dsub |
| 22124 | 0, // zsub3_then_hsub |
| 22125 | 0, // zsub3_then_ssub |
| 22126 | 0, // zsub3_then_zsub |
| 22127 | 0, // zsub3_then_zsub_hi |
| 22128 | 0, // zsub2_then_bsub |
| 22129 | 0, // zsub2_then_dsub |
| 22130 | 0, // zsub2_then_hsub |
| 22131 | 0, // zsub2_then_ssub |
| 22132 | 0, // zsub2_then_zsub |
| 22133 | 0, // zsub2_then_zsub_hi |
| 22134 | 0, // dsub0_dsub1 |
| 22135 | 0, // dsub0_dsub1_dsub2 |
| 22136 | 0, // dsub1_dsub2 |
| 22137 | 0, // dsub1_dsub2_dsub3 |
| 22138 | 0, // dsub2_dsub3 |
| 22139 | 0, // dsub_qsub1_then_dsub |
| 22140 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22141 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22142 | 0, // qsub0_qsub1 |
| 22143 | 0, // qsub0_qsub1_qsub2 |
| 22144 | 0, // qsub1_qsub2 |
| 22145 | 0, // qsub1_qsub2_qsub3 |
| 22146 | 0, // qsub2_qsub3 |
| 22147 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22148 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22149 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22150 | 72, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22151 | 72, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22152 | 72, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22153 | 72, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22154 | 72, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22155 | 72, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22156 | 72, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22157 | 72, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22158 | 0, // sub_32_subo64_then_sub_32 |
| 22159 | 0, // dsub_zsub1_then_dsub |
| 22160 | 0, // zsub_zsub1_then_zsub |
| 22161 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22162 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22163 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22164 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22165 | 0, // zsub0_zsub1 |
| 22166 | 0, // zsub0_zsub1_zsub2 |
| 22167 | 0, // zsub1_zsub2 |
| 22168 | 0, // zsub1_zsub2_zsub3 |
| 22169 | 0, // zsub2_zsub3 |
| 22170 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22171 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22172 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22173 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22174 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22175 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22176 | }, |
| 22177 | { // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22178 | 0, // bsub |
| 22179 | 0, // dsub |
| 22180 | 0, // dsub0 |
| 22181 | 0, // dsub1 |
| 22182 | 0, // dsub2 |
| 22183 | 0, // dsub3 |
| 22184 | 0, // hsub |
| 22185 | 0, // qhisub |
| 22186 | 0, // qsub |
| 22187 | 0, // qsub0 |
| 22188 | 0, // qsub1 |
| 22189 | 0, // qsub2 |
| 22190 | 0, // qsub3 |
| 22191 | 0, // ssub |
| 22192 | 73, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22193 | 0, // sube32 |
| 22194 | 0, // sube64 |
| 22195 | 0, // subo32 |
| 22196 | 0, // subo64 |
| 22197 | 73, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22198 | 73, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22199 | 73, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22200 | 73, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22201 | 73, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22202 | 73, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22203 | 73, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22204 | 73, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22205 | 0, // zsub |
| 22206 | 0, // zsub0 |
| 22207 | 0, // zsub1 |
| 22208 | 0, // zsub2 |
| 22209 | 0, // zsub3 |
| 22210 | 0, // zsub_hi |
| 22211 | 0, // dsub1_then_bsub |
| 22212 | 0, // dsub1_then_hsub |
| 22213 | 0, // dsub1_then_ssub |
| 22214 | 0, // dsub3_then_bsub |
| 22215 | 0, // dsub3_then_hsub |
| 22216 | 0, // dsub3_then_ssub |
| 22217 | 0, // dsub2_then_bsub |
| 22218 | 0, // dsub2_then_hsub |
| 22219 | 0, // dsub2_then_ssub |
| 22220 | 0, // qsub1_then_bsub |
| 22221 | 0, // qsub1_then_dsub |
| 22222 | 0, // qsub1_then_hsub |
| 22223 | 0, // qsub1_then_ssub |
| 22224 | 0, // qsub3_then_bsub |
| 22225 | 0, // qsub3_then_dsub |
| 22226 | 0, // qsub3_then_hsub |
| 22227 | 0, // qsub3_then_ssub |
| 22228 | 0, // qsub2_then_bsub |
| 22229 | 0, // qsub2_then_dsub |
| 22230 | 0, // qsub2_then_hsub |
| 22231 | 0, // qsub2_then_ssub |
| 22232 | 73, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22233 | 73, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22234 | 73, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22235 | 73, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22236 | 73, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22237 | 73, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22238 | 73, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22239 | 0, // subo64_then_sub_32 |
| 22240 | 0, // zsub1_then_bsub |
| 22241 | 0, // zsub1_then_dsub |
| 22242 | 0, // zsub1_then_hsub |
| 22243 | 0, // zsub1_then_ssub |
| 22244 | 0, // zsub1_then_zsub |
| 22245 | 0, // zsub1_then_zsub_hi |
| 22246 | 0, // zsub3_then_bsub |
| 22247 | 0, // zsub3_then_dsub |
| 22248 | 0, // zsub3_then_hsub |
| 22249 | 0, // zsub3_then_ssub |
| 22250 | 0, // zsub3_then_zsub |
| 22251 | 0, // zsub3_then_zsub_hi |
| 22252 | 0, // zsub2_then_bsub |
| 22253 | 0, // zsub2_then_dsub |
| 22254 | 0, // zsub2_then_hsub |
| 22255 | 0, // zsub2_then_ssub |
| 22256 | 0, // zsub2_then_zsub |
| 22257 | 0, // zsub2_then_zsub_hi |
| 22258 | 0, // dsub0_dsub1 |
| 22259 | 0, // dsub0_dsub1_dsub2 |
| 22260 | 0, // dsub1_dsub2 |
| 22261 | 0, // dsub1_dsub2_dsub3 |
| 22262 | 0, // dsub2_dsub3 |
| 22263 | 0, // dsub_qsub1_then_dsub |
| 22264 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22265 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22266 | 0, // qsub0_qsub1 |
| 22267 | 0, // qsub0_qsub1_qsub2 |
| 22268 | 0, // qsub1_qsub2 |
| 22269 | 0, // qsub1_qsub2_qsub3 |
| 22270 | 0, // qsub2_qsub3 |
| 22271 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22272 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22273 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22274 | 73, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22275 | 73, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22276 | 73, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22277 | 73, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22278 | 73, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22279 | 73, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22280 | 73, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22281 | 73, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 22282 | 0, // sub_32_subo64_then_sub_32 |
| 22283 | 0, // dsub_zsub1_then_dsub |
| 22284 | 0, // zsub_zsub1_then_zsub |
| 22285 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22286 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22287 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22288 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22289 | 0, // zsub0_zsub1 |
| 22290 | 0, // zsub0_zsub1_zsub2 |
| 22291 | 0, // zsub1_zsub2 |
| 22292 | 0, // zsub1_zsub2_zsub3 |
| 22293 | 0, // zsub2_zsub3 |
| 22294 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22295 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22296 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22297 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22298 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22299 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22300 | }, |
| 22301 | { // GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22302 | 0, // bsub |
| 22303 | 0, // dsub |
| 22304 | 0, // dsub0 |
| 22305 | 0, // dsub1 |
| 22306 | 0, // dsub2 |
| 22307 | 0, // dsub3 |
| 22308 | 0, // hsub |
| 22309 | 0, // qhisub |
| 22310 | 0, // qsub |
| 22311 | 0, // qsub0 |
| 22312 | 0, // qsub1 |
| 22313 | 0, // qsub2 |
| 22314 | 0, // qsub3 |
| 22315 | 0, // ssub |
| 22316 | 74, // sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22317 | 0, // sube32 |
| 22318 | 0, // sube64 |
| 22319 | 0, // subo32 |
| 22320 | 0, // subo64 |
| 22321 | 74, // x8sub_0 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22322 | 74, // x8sub_1 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22323 | 74, // x8sub_2 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22324 | 74, // x8sub_3 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22325 | 74, // x8sub_4 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22326 | 74, // x8sub_5 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22327 | 74, // x8sub_6 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22328 | 74, // x8sub_7 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22329 | 0, // zsub |
| 22330 | 0, // zsub0 |
| 22331 | 0, // zsub1 |
| 22332 | 0, // zsub2 |
| 22333 | 0, // zsub3 |
| 22334 | 0, // zsub_hi |
| 22335 | 0, // dsub1_then_bsub |
| 22336 | 0, // dsub1_then_hsub |
| 22337 | 0, // dsub1_then_ssub |
| 22338 | 0, // dsub3_then_bsub |
| 22339 | 0, // dsub3_then_hsub |
| 22340 | 0, // dsub3_then_ssub |
| 22341 | 0, // dsub2_then_bsub |
| 22342 | 0, // dsub2_then_hsub |
| 22343 | 0, // dsub2_then_ssub |
| 22344 | 0, // qsub1_then_bsub |
| 22345 | 0, // qsub1_then_dsub |
| 22346 | 0, // qsub1_then_hsub |
| 22347 | 0, // qsub1_then_ssub |
| 22348 | 0, // qsub3_then_bsub |
| 22349 | 0, // qsub3_then_dsub |
| 22350 | 0, // qsub3_then_hsub |
| 22351 | 0, // qsub3_then_ssub |
| 22352 | 0, // qsub2_then_bsub |
| 22353 | 0, // qsub2_then_dsub |
| 22354 | 0, // qsub2_then_hsub |
| 22355 | 0, // qsub2_then_ssub |
| 22356 | 74, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22357 | 74, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22358 | 74, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22359 | 74, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22360 | 74, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22361 | 74, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22362 | 74, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22363 | 0, // subo64_then_sub_32 |
| 22364 | 0, // zsub1_then_bsub |
| 22365 | 0, // zsub1_then_dsub |
| 22366 | 0, // zsub1_then_hsub |
| 22367 | 0, // zsub1_then_ssub |
| 22368 | 0, // zsub1_then_zsub |
| 22369 | 0, // zsub1_then_zsub_hi |
| 22370 | 0, // zsub3_then_bsub |
| 22371 | 0, // zsub3_then_dsub |
| 22372 | 0, // zsub3_then_hsub |
| 22373 | 0, // zsub3_then_ssub |
| 22374 | 0, // zsub3_then_zsub |
| 22375 | 0, // zsub3_then_zsub_hi |
| 22376 | 0, // zsub2_then_bsub |
| 22377 | 0, // zsub2_then_dsub |
| 22378 | 0, // zsub2_then_hsub |
| 22379 | 0, // zsub2_then_ssub |
| 22380 | 0, // zsub2_then_zsub |
| 22381 | 0, // zsub2_then_zsub_hi |
| 22382 | 0, // dsub0_dsub1 |
| 22383 | 0, // dsub0_dsub1_dsub2 |
| 22384 | 0, // dsub1_dsub2 |
| 22385 | 0, // dsub1_dsub2_dsub3 |
| 22386 | 0, // dsub2_dsub3 |
| 22387 | 0, // dsub_qsub1_then_dsub |
| 22388 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22389 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22390 | 0, // qsub0_qsub1 |
| 22391 | 0, // qsub0_qsub1_qsub2 |
| 22392 | 0, // qsub1_qsub2 |
| 22393 | 0, // qsub1_qsub2_qsub3 |
| 22394 | 0, // qsub2_qsub3 |
| 22395 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22396 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22397 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22398 | 74, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22399 | 74, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22400 | 74, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22401 | 74, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22402 | 74, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22403 | 74, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22404 | 74, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22405 | 74, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 22406 | 0, // sub_32_subo64_then_sub_32 |
| 22407 | 0, // dsub_zsub1_then_dsub |
| 22408 | 0, // zsub_zsub1_then_zsub |
| 22409 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22410 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22411 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22412 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22413 | 0, // zsub0_zsub1 |
| 22414 | 0, // zsub0_zsub1_zsub2 |
| 22415 | 0, // zsub1_zsub2 |
| 22416 | 0, // zsub1_zsub2_zsub3 |
| 22417 | 0, // zsub2_zsub3 |
| 22418 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22419 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22420 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22421 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22422 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22423 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22424 | }, |
| 22425 | { // GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22426 | 0, // bsub |
| 22427 | 0, // dsub |
| 22428 | 0, // dsub0 |
| 22429 | 0, // dsub1 |
| 22430 | 0, // dsub2 |
| 22431 | 0, // dsub3 |
| 22432 | 0, // hsub |
| 22433 | 0, // qhisub |
| 22434 | 0, // qsub |
| 22435 | 0, // qsub0 |
| 22436 | 0, // qsub1 |
| 22437 | 0, // qsub2 |
| 22438 | 0, // qsub3 |
| 22439 | 0, // ssub |
| 22440 | 75, // sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22441 | 0, // sube32 |
| 22442 | 0, // sube64 |
| 22443 | 0, // subo32 |
| 22444 | 0, // subo64 |
| 22445 | 75, // x8sub_0 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22446 | 75, // x8sub_1 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22447 | 75, // x8sub_2 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22448 | 75, // x8sub_3 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22449 | 75, // x8sub_4 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22450 | 75, // x8sub_5 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22451 | 75, // x8sub_6 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22452 | 75, // x8sub_7 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22453 | 0, // zsub |
| 22454 | 0, // zsub0 |
| 22455 | 0, // zsub1 |
| 22456 | 0, // zsub2 |
| 22457 | 0, // zsub3 |
| 22458 | 0, // zsub_hi |
| 22459 | 0, // dsub1_then_bsub |
| 22460 | 0, // dsub1_then_hsub |
| 22461 | 0, // dsub1_then_ssub |
| 22462 | 0, // dsub3_then_bsub |
| 22463 | 0, // dsub3_then_hsub |
| 22464 | 0, // dsub3_then_ssub |
| 22465 | 0, // dsub2_then_bsub |
| 22466 | 0, // dsub2_then_hsub |
| 22467 | 0, // dsub2_then_ssub |
| 22468 | 0, // qsub1_then_bsub |
| 22469 | 0, // qsub1_then_dsub |
| 22470 | 0, // qsub1_then_hsub |
| 22471 | 0, // qsub1_then_ssub |
| 22472 | 0, // qsub3_then_bsub |
| 22473 | 0, // qsub3_then_dsub |
| 22474 | 0, // qsub3_then_hsub |
| 22475 | 0, // qsub3_then_ssub |
| 22476 | 0, // qsub2_then_bsub |
| 22477 | 0, // qsub2_then_dsub |
| 22478 | 0, // qsub2_then_hsub |
| 22479 | 0, // qsub2_then_ssub |
| 22480 | 75, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22481 | 75, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22482 | 75, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22483 | 75, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22484 | 75, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22485 | 75, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22486 | 75, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22487 | 0, // subo64_then_sub_32 |
| 22488 | 0, // zsub1_then_bsub |
| 22489 | 0, // zsub1_then_dsub |
| 22490 | 0, // zsub1_then_hsub |
| 22491 | 0, // zsub1_then_ssub |
| 22492 | 0, // zsub1_then_zsub |
| 22493 | 0, // zsub1_then_zsub_hi |
| 22494 | 0, // zsub3_then_bsub |
| 22495 | 0, // zsub3_then_dsub |
| 22496 | 0, // zsub3_then_hsub |
| 22497 | 0, // zsub3_then_ssub |
| 22498 | 0, // zsub3_then_zsub |
| 22499 | 0, // zsub3_then_zsub_hi |
| 22500 | 0, // zsub2_then_bsub |
| 22501 | 0, // zsub2_then_dsub |
| 22502 | 0, // zsub2_then_hsub |
| 22503 | 0, // zsub2_then_ssub |
| 22504 | 0, // zsub2_then_zsub |
| 22505 | 0, // zsub2_then_zsub_hi |
| 22506 | 0, // dsub0_dsub1 |
| 22507 | 0, // dsub0_dsub1_dsub2 |
| 22508 | 0, // dsub1_dsub2 |
| 22509 | 0, // dsub1_dsub2_dsub3 |
| 22510 | 0, // dsub2_dsub3 |
| 22511 | 0, // dsub_qsub1_then_dsub |
| 22512 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22513 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22514 | 0, // qsub0_qsub1 |
| 22515 | 0, // qsub0_qsub1_qsub2 |
| 22516 | 0, // qsub1_qsub2 |
| 22517 | 0, // qsub1_qsub2_qsub3 |
| 22518 | 0, // qsub2_qsub3 |
| 22519 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22520 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22521 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22522 | 75, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22523 | 75, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22524 | 75, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22525 | 75, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22526 | 75, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22527 | 75, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22528 | 75, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22529 | 75, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 22530 | 0, // sub_32_subo64_then_sub_32 |
| 22531 | 0, // dsub_zsub1_then_dsub |
| 22532 | 0, // zsub_zsub1_then_zsub |
| 22533 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22534 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22535 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22536 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22537 | 0, // zsub0_zsub1 |
| 22538 | 0, // zsub0_zsub1_zsub2 |
| 22539 | 0, // zsub1_zsub2 |
| 22540 | 0, // zsub1_zsub2_zsub3 |
| 22541 | 0, // zsub2_zsub3 |
| 22542 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22543 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22544 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22545 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22546 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22547 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22548 | }, |
| 22549 | { // GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22550 | 0, // bsub |
| 22551 | 0, // dsub |
| 22552 | 0, // dsub0 |
| 22553 | 0, // dsub1 |
| 22554 | 0, // dsub2 |
| 22555 | 0, // dsub3 |
| 22556 | 0, // hsub |
| 22557 | 0, // qhisub |
| 22558 | 0, // qsub |
| 22559 | 0, // qsub0 |
| 22560 | 0, // qsub1 |
| 22561 | 0, // qsub2 |
| 22562 | 0, // qsub3 |
| 22563 | 0, // ssub |
| 22564 | 76, // sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22565 | 0, // sube32 |
| 22566 | 0, // sube64 |
| 22567 | 0, // subo32 |
| 22568 | 0, // subo64 |
| 22569 | 76, // x8sub_0 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22570 | 76, // x8sub_1 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22571 | 76, // x8sub_2 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22572 | 76, // x8sub_3 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22573 | 76, // x8sub_4 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22574 | 76, // x8sub_5 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22575 | 76, // x8sub_6 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22576 | 76, // x8sub_7 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22577 | 0, // zsub |
| 22578 | 0, // zsub0 |
| 22579 | 0, // zsub1 |
| 22580 | 0, // zsub2 |
| 22581 | 0, // zsub3 |
| 22582 | 0, // zsub_hi |
| 22583 | 0, // dsub1_then_bsub |
| 22584 | 0, // dsub1_then_hsub |
| 22585 | 0, // dsub1_then_ssub |
| 22586 | 0, // dsub3_then_bsub |
| 22587 | 0, // dsub3_then_hsub |
| 22588 | 0, // dsub3_then_ssub |
| 22589 | 0, // dsub2_then_bsub |
| 22590 | 0, // dsub2_then_hsub |
| 22591 | 0, // dsub2_then_ssub |
| 22592 | 0, // qsub1_then_bsub |
| 22593 | 0, // qsub1_then_dsub |
| 22594 | 0, // qsub1_then_hsub |
| 22595 | 0, // qsub1_then_ssub |
| 22596 | 0, // qsub3_then_bsub |
| 22597 | 0, // qsub3_then_dsub |
| 22598 | 0, // qsub3_then_hsub |
| 22599 | 0, // qsub3_then_ssub |
| 22600 | 0, // qsub2_then_bsub |
| 22601 | 0, // qsub2_then_dsub |
| 22602 | 0, // qsub2_then_hsub |
| 22603 | 0, // qsub2_then_ssub |
| 22604 | 76, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22605 | 76, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22606 | 76, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22607 | 76, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22608 | 76, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22609 | 76, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22610 | 76, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22611 | 0, // subo64_then_sub_32 |
| 22612 | 0, // zsub1_then_bsub |
| 22613 | 0, // zsub1_then_dsub |
| 22614 | 0, // zsub1_then_hsub |
| 22615 | 0, // zsub1_then_ssub |
| 22616 | 0, // zsub1_then_zsub |
| 22617 | 0, // zsub1_then_zsub_hi |
| 22618 | 0, // zsub3_then_bsub |
| 22619 | 0, // zsub3_then_dsub |
| 22620 | 0, // zsub3_then_hsub |
| 22621 | 0, // zsub3_then_ssub |
| 22622 | 0, // zsub3_then_zsub |
| 22623 | 0, // zsub3_then_zsub_hi |
| 22624 | 0, // zsub2_then_bsub |
| 22625 | 0, // zsub2_then_dsub |
| 22626 | 0, // zsub2_then_hsub |
| 22627 | 0, // zsub2_then_ssub |
| 22628 | 0, // zsub2_then_zsub |
| 22629 | 0, // zsub2_then_zsub_hi |
| 22630 | 0, // dsub0_dsub1 |
| 22631 | 0, // dsub0_dsub1_dsub2 |
| 22632 | 0, // dsub1_dsub2 |
| 22633 | 0, // dsub1_dsub2_dsub3 |
| 22634 | 0, // dsub2_dsub3 |
| 22635 | 0, // dsub_qsub1_then_dsub |
| 22636 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22637 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22638 | 0, // qsub0_qsub1 |
| 22639 | 0, // qsub0_qsub1_qsub2 |
| 22640 | 0, // qsub1_qsub2 |
| 22641 | 0, // qsub1_qsub2_qsub3 |
| 22642 | 0, // qsub2_qsub3 |
| 22643 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22644 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22645 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22646 | 76, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22647 | 76, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22648 | 76, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22649 | 76, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22650 | 76, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22651 | 76, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22652 | 76, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22653 | 76, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 22654 | 0, // sub_32_subo64_then_sub_32 |
| 22655 | 0, // dsub_zsub1_then_dsub |
| 22656 | 0, // zsub_zsub1_then_zsub |
| 22657 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22658 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22659 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22660 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22661 | 0, // zsub0_zsub1 |
| 22662 | 0, // zsub0_zsub1_zsub2 |
| 22663 | 0, // zsub1_zsub2 |
| 22664 | 0, // zsub1_zsub2_zsub3 |
| 22665 | 0, // zsub2_zsub3 |
| 22666 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22667 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22668 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22669 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22670 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22671 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22672 | }, |
| 22673 | { // GPR64x8Class_with_sub_32_in_GPR32arg |
| 22674 | 0, // bsub |
| 22675 | 0, // dsub |
| 22676 | 0, // dsub0 |
| 22677 | 0, // dsub1 |
| 22678 | 0, // dsub2 |
| 22679 | 0, // dsub3 |
| 22680 | 0, // hsub |
| 22681 | 0, // qhisub |
| 22682 | 0, // qsub |
| 22683 | 0, // qsub0 |
| 22684 | 0, // qsub1 |
| 22685 | 0, // qsub2 |
| 22686 | 0, // qsub3 |
| 22687 | 0, // ssub |
| 22688 | 77, // sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22689 | 0, // sube32 |
| 22690 | 0, // sube64 |
| 22691 | 0, // subo32 |
| 22692 | 0, // subo64 |
| 22693 | 77, // x8sub_0 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22694 | 77, // x8sub_1 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22695 | 77, // x8sub_2 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22696 | 77, // x8sub_3 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22697 | 77, // x8sub_4 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22698 | 77, // x8sub_5 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22699 | 77, // x8sub_6 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22700 | 77, // x8sub_7 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22701 | 0, // zsub |
| 22702 | 0, // zsub0 |
| 22703 | 0, // zsub1 |
| 22704 | 0, // zsub2 |
| 22705 | 0, // zsub3 |
| 22706 | 0, // zsub_hi |
| 22707 | 0, // dsub1_then_bsub |
| 22708 | 0, // dsub1_then_hsub |
| 22709 | 0, // dsub1_then_ssub |
| 22710 | 0, // dsub3_then_bsub |
| 22711 | 0, // dsub3_then_hsub |
| 22712 | 0, // dsub3_then_ssub |
| 22713 | 0, // dsub2_then_bsub |
| 22714 | 0, // dsub2_then_hsub |
| 22715 | 0, // dsub2_then_ssub |
| 22716 | 0, // qsub1_then_bsub |
| 22717 | 0, // qsub1_then_dsub |
| 22718 | 0, // qsub1_then_hsub |
| 22719 | 0, // qsub1_then_ssub |
| 22720 | 0, // qsub3_then_bsub |
| 22721 | 0, // qsub3_then_dsub |
| 22722 | 0, // qsub3_then_hsub |
| 22723 | 0, // qsub3_then_ssub |
| 22724 | 0, // qsub2_then_bsub |
| 22725 | 0, // qsub2_then_dsub |
| 22726 | 0, // qsub2_then_hsub |
| 22727 | 0, // qsub2_then_ssub |
| 22728 | 77, // x8sub_7_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22729 | 77, // x8sub_6_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22730 | 77, // x8sub_5_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22731 | 77, // x8sub_4_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22732 | 77, // x8sub_3_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22733 | 77, // x8sub_2_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22734 | 77, // x8sub_1_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22735 | 0, // subo64_then_sub_32 |
| 22736 | 0, // zsub1_then_bsub |
| 22737 | 0, // zsub1_then_dsub |
| 22738 | 0, // zsub1_then_hsub |
| 22739 | 0, // zsub1_then_ssub |
| 22740 | 0, // zsub1_then_zsub |
| 22741 | 0, // zsub1_then_zsub_hi |
| 22742 | 0, // zsub3_then_bsub |
| 22743 | 0, // zsub3_then_dsub |
| 22744 | 0, // zsub3_then_hsub |
| 22745 | 0, // zsub3_then_ssub |
| 22746 | 0, // zsub3_then_zsub |
| 22747 | 0, // zsub3_then_zsub_hi |
| 22748 | 0, // zsub2_then_bsub |
| 22749 | 0, // zsub2_then_dsub |
| 22750 | 0, // zsub2_then_hsub |
| 22751 | 0, // zsub2_then_ssub |
| 22752 | 0, // zsub2_then_zsub |
| 22753 | 0, // zsub2_then_zsub_hi |
| 22754 | 0, // dsub0_dsub1 |
| 22755 | 0, // dsub0_dsub1_dsub2 |
| 22756 | 0, // dsub1_dsub2 |
| 22757 | 0, // dsub1_dsub2_dsub3 |
| 22758 | 0, // dsub2_dsub3 |
| 22759 | 0, // dsub_qsub1_then_dsub |
| 22760 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22761 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22762 | 0, // qsub0_qsub1 |
| 22763 | 0, // qsub0_qsub1_qsub2 |
| 22764 | 0, // qsub1_qsub2 |
| 22765 | 0, // qsub1_qsub2_qsub3 |
| 22766 | 0, // qsub2_qsub3 |
| 22767 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22768 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22769 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22770 | 77, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22771 | 77, // x8sub_0_x8sub_1 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22772 | 77, // x8sub_2_x8sub_3 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22773 | 77, // x8sub_4_x8sub_5 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22774 | 77, // x8sub_6_x8sub_7 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22775 | 77, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22776 | 77, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22777 | 77, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_sub_32_in_GPR32arg |
| 22778 | 0, // sub_32_subo64_then_sub_32 |
| 22779 | 0, // dsub_zsub1_then_dsub |
| 22780 | 0, // zsub_zsub1_then_zsub |
| 22781 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22782 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22783 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22784 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22785 | 0, // zsub0_zsub1 |
| 22786 | 0, // zsub0_zsub1_zsub2 |
| 22787 | 0, // zsub1_zsub2 |
| 22788 | 0, // zsub1_zsub2_zsub3 |
| 22789 | 0, // zsub2_zsub3 |
| 22790 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22791 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22792 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22793 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22794 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22795 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22796 | }, |
| 22797 | { // GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22798 | 0, // bsub |
| 22799 | 0, // dsub |
| 22800 | 0, // dsub0 |
| 22801 | 0, // dsub1 |
| 22802 | 0, // dsub2 |
| 22803 | 0, // dsub3 |
| 22804 | 0, // hsub |
| 22805 | 0, // qhisub |
| 22806 | 0, // qsub |
| 22807 | 0, // qsub0 |
| 22808 | 0, // qsub1 |
| 22809 | 0, // qsub2 |
| 22810 | 0, // qsub3 |
| 22811 | 0, // ssub |
| 22812 | 78, // sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22813 | 0, // sube32 |
| 22814 | 0, // sube64 |
| 22815 | 0, // subo32 |
| 22816 | 0, // subo64 |
| 22817 | 78, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22818 | 78, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22819 | 78, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22820 | 78, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22821 | 78, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22822 | 78, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22823 | 78, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22824 | 78, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22825 | 0, // zsub |
| 22826 | 0, // zsub0 |
| 22827 | 0, // zsub1 |
| 22828 | 0, // zsub2 |
| 22829 | 0, // zsub3 |
| 22830 | 0, // zsub_hi |
| 22831 | 0, // dsub1_then_bsub |
| 22832 | 0, // dsub1_then_hsub |
| 22833 | 0, // dsub1_then_ssub |
| 22834 | 0, // dsub3_then_bsub |
| 22835 | 0, // dsub3_then_hsub |
| 22836 | 0, // dsub3_then_ssub |
| 22837 | 0, // dsub2_then_bsub |
| 22838 | 0, // dsub2_then_hsub |
| 22839 | 0, // dsub2_then_ssub |
| 22840 | 0, // qsub1_then_bsub |
| 22841 | 0, // qsub1_then_dsub |
| 22842 | 0, // qsub1_then_hsub |
| 22843 | 0, // qsub1_then_ssub |
| 22844 | 0, // qsub3_then_bsub |
| 22845 | 0, // qsub3_then_dsub |
| 22846 | 0, // qsub3_then_hsub |
| 22847 | 0, // qsub3_then_ssub |
| 22848 | 0, // qsub2_then_bsub |
| 22849 | 0, // qsub2_then_dsub |
| 22850 | 0, // qsub2_then_hsub |
| 22851 | 0, // qsub2_then_ssub |
| 22852 | 78, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22853 | 78, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22854 | 78, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22855 | 78, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22856 | 78, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22857 | 78, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22858 | 78, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22859 | 0, // subo64_then_sub_32 |
| 22860 | 0, // zsub1_then_bsub |
| 22861 | 0, // zsub1_then_dsub |
| 22862 | 0, // zsub1_then_hsub |
| 22863 | 0, // zsub1_then_ssub |
| 22864 | 0, // zsub1_then_zsub |
| 22865 | 0, // zsub1_then_zsub_hi |
| 22866 | 0, // zsub3_then_bsub |
| 22867 | 0, // zsub3_then_dsub |
| 22868 | 0, // zsub3_then_hsub |
| 22869 | 0, // zsub3_then_ssub |
| 22870 | 0, // zsub3_then_zsub |
| 22871 | 0, // zsub3_then_zsub_hi |
| 22872 | 0, // zsub2_then_bsub |
| 22873 | 0, // zsub2_then_dsub |
| 22874 | 0, // zsub2_then_hsub |
| 22875 | 0, // zsub2_then_ssub |
| 22876 | 0, // zsub2_then_zsub |
| 22877 | 0, // zsub2_then_zsub_hi |
| 22878 | 0, // dsub0_dsub1 |
| 22879 | 0, // dsub0_dsub1_dsub2 |
| 22880 | 0, // dsub1_dsub2 |
| 22881 | 0, // dsub1_dsub2_dsub3 |
| 22882 | 0, // dsub2_dsub3 |
| 22883 | 0, // dsub_qsub1_then_dsub |
| 22884 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22885 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 22886 | 0, // qsub0_qsub1 |
| 22887 | 0, // qsub0_qsub1_qsub2 |
| 22888 | 0, // qsub1_qsub2 |
| 22889 | 0, // qsub1_qsub2_qsub3 |
| 22890 | 0, // qsub2_qsub3 |
| 22891 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 22892 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 22893 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 22894 | 78, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22895 | 78, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22896 | 78, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22897 | 78, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22898 | 78, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22899 | 78, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22900 | 78, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22901 | 78, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 22902 | 0, // sub_32_subo64_then_sub_32 |
| 22903 | 0, // dsub_zsub1_then_dsub |
| 22904 | 0, // zsub_zsub1_then_zsub |
| 22905 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22906 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 22907 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22908 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 22909 | 0, // zsub0_zsub1 |
| 22910 | 0, // zsub0_zsub1_zsub2 |
| 22911 | 0, // zsub1_zsub2 |
| 22912 | 0, // zsub1_zsub2_zsub3 |
| 22913 | 0, // zsub2_zsub3 |
| 22914 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 22915 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 22916 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 22917 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 22918 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 22919 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 22920 | }, |
| 22921 | { // GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22922 | 0, // bsub |
| 22923 | 0, // dsub |
| 22924 | 0, // dsub0 |
| 22925 | 0, // dsub1 |
| 22926 | 0, // dsub2 |
| 22927 | 0, // dsub3 |
| 22928 | 0, // hsub |
| 22929 | 0, // qhisub |
| 22930 | 0, // qsub |
| 22931 | 0, // qsub0 |
| 22932 | 0, // qsub1 |
| 22933 | 0, // qsub2 |
| 22934 | 0, // qsub3 |
| 22935 | 0, // ssub |
| 22936 | 79, // sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22937 | 0, // sube32 |
| 22938 | 0, // sube64 |
| 22939 | 0, // subo32 |
| 22940 | 0, // subo64 |
| 22941 | 79, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22942 | 79, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22943 | 79, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22944 | 79, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22945 | 79, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22946 | 79, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22947 | 79, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22948 | 79, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22949 | 0, // zsub |
| 22950 | 0, // zsub0 |
| 22951 | 0, // zsub1 |
| 22952 | 0, // zsub2 |
| 22953 | 0, // zsub3 |
| 22954 | 0, // zsub_hi |
| 22955 | 0, // dsub1_then_bsub |
| 22956 | 0, // dsub1_then_hsub |
| 22957 | 0, // dsub1_then_ssub |
| 22958 | 0, // dsub3_then_bsub |
| 22959 | 0, // dsub3_then_hsub |
| 22960 | 0, // dsub3_then_ssub |
| 22961 | 0, // dsub2_then_bsub |
| 22962 | 0, // dsub2_then_hsub |
| 22963 | 0, // dsub2_then_ssub |
| 22964 | 0, // qsub1_then_bsub |
| 22965 | 0, // qsub1_then_dsub |
| 22966 | 0, // qsub1_then_hsub |
| 22967 | 0, // qsub1_then_ssub |
| 22968 | 0, // qsub3_then_bsub |
| 22969 | 0, // qsub3_then_dsub |
| 22970 | 0, // qsub3_then_hsub |
| 22971 | 0, // qsub3_then_ssub |
| 22972 | 0, // qsub2_then_bsub |
| 22973 | 0, // qsub2_then_dsub |
| 22974 | 0, // qsub2_then_hsub |
| 22975 | 0, // qsub2_then_ssub |
| 22976 | 79, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22977 | 79, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22978 | 79, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22979 | 79, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22980 | 79, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22981 | 79, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22982 | 79, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 22983 | 0, // subo64_then_sub_32 |
| 22984 | 0, // zsub1_then_bsub |
| 22985 | 0, // zsub1_then_dsub |
| 22986 | 0, // zsub1_then_hsub |
| 22987 | 0, // zsub1_then_ssub |
| 22988 | 0, // zsub1_then_zsub |
| 22989 | 0, // zsub1_then_zsub_hi |
| 22990 | 0, // zsub3_then_bsub |
| 22991 | 0, // zsub3_then_dsub |
| 22992 | 0, // zsub3_then_hsub |
| 22993 | 0, // zsub3_then_ssub |
| 22994 | 0, // zsub3_then_zsub |
| 22995 | 0, // zsub3_then_zsub_hi |
| 22996 | 0, // zsub2_then_bsub |
| 22997 | 0, // zsub2_then_dsub |
| 22998 | 0, // zsub2_then_hsub |
| 22999 | 0, // zsub2_then_ssub |
| 23000 | 0, // zsub2_then_zsub |
| 23001 | 0, // zsub2_then_zsub_hi |
| 23002 | 0, // dsub0_dsub1 |
| 23003 | 0, // dsub0_dsub1_dsub2 |
| 23004 | 0, // dsub1_dsub2 |
| 23005 | 0, // dsub1_dsub2_dsub3 |
| 23006 | 0, // dsub2_dsub3 |
| 23007 | 0, // dsub_qsub1_then_dsub |
| 23008 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23009 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23010 | 0, // qsub0_qsub1 |
| 23011 | 0, // qsub0_qsub1_qsub2 |
| 23012 | 0, // qsub1_qsub2 |
| 23013 | 0, // qsub1_qsub2_qsub3 |
| 23014 | 0, // qsub2_qsub3 |
| 23015 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23016 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23017 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23018 | 79, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23019 | 79, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23020 | 79, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23021 | 79, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23022 | 79, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23023 | 79, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23024 | 79, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23025 | 79, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 23026 | 0, // sub_32_subo64_then_sub_32 |
| 23027 | 0, // dsub_zsub1_then_dsub |
| 23028 | 0, // zsub_zsub1_then_zsub |
| 23029 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23030 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23031 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23032 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23033 | 0, // zsub0_zsub1 |
| 23034 | 0, // zsub0_zsub1_zsub2 |
| 23035 | 0, // zsub1_zsub2 |
| 23036 | 0, // zsub1_zsub2_zsub3 |
| 23037 | 0, // zsub2_zsub3 |
| 23038 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23039 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23040 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23041 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23042 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23043 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23044 | }, |
| 23045 | { // rtcGPR64 |
| 23046 | 0, // bsub |
| 23047 | 0, // dsub |
| 23048 | 0, // dsub0 |
| 23049 | 0, // dsub1 |
| 23050 | 0, // dsub2 |
| 23051 | 0, // dsub3 |
| 23052 | 0, // hsub |
| 23053 | 0, // qhisub |
| 23054 | 0, // qsub |
| 23055 | 0, // qsub0 |
| 23056 | 0, // qsub1 |
| 23057 | 0, // qsub2 |
| 23058 | 0, // qsub3 |
| 23059 | 0, // ssub |
| 23060 | 80, // sub_32 -> rtcGPR64 |
| 23061 | 0, // sube32 |
| 23062 | 0, // sube64 |
| 23063 | 0, // subo32 |
| 23064 | 0, // subo64 |
| 23065 | 0, // x8sub_0 |
| 23066 | 0, // x8sub_1 |
| 23067 | 0, // x8sub_2 |
| 23068 | 0, // x8sub_3 |
| 23069 | 0, // x8sub_4 |
| 23070 | 0, // x8sub_5 |
| 23071 | 0, // x8sub_6 |
| 23072 | 0, // x8sub_7 |
| 23073 | 0, // zsub |
| 23074 | 0, // zsub0 |
| 23075 | 0, // zsub1 |
| 23076 | 0, // zsub2 |
| 23077 | 0, // zsub3 |
| 23078 | 0, // zsub_hi |
| 23079 | 0, // dsub1_then_bsub |
| 23080 | 0, // dsub1_then_hsub |
| 23081 | 0, // dsub1_then_ssub |
| 23082 | 0, // dsub3_then_bsub |
| 23083 | 0, // dsub3_then_hsub |
| 23084 | 0, // dsub3_then_ssub |
| 23085 | 0, // dsub2_then_bsub |
| 23086 | 0, // dsub2_then_hsub |
| 23087 | 0, // dsub2_then_ssub |
| 23088 | 0, // qsub1_then_bsub |
| 23089 | 0, // qsub1_then_dsub |
| 23090 | 0, // qsub1_then_hsub |
| 23091 | 0, // qsub1_then_ssub |
| 23092 | 0, // qsub3_then_bsub |
| 23093 | 0, // qsub3_then_dsub |
| 23094 | 0, // qsub3_then_hsub |
| 23095 | 0, // qsub3_then_ssub |
| 23096 | 0, // qsub2_then_bsub |
| 23097 | 0, // qsub2_then_dsub |
| 23098 | 0, // qsub2_then_hsub |
| 23099 | 0, // qsub2_then_ssub |
| 23100 | 0, // x8sub_7_then_sub_32 |
| 23101 | 0, // x8sub_6_then_sub_32 |
| 23102 | 0, // x8sub_5_then_sub_32 |
| 23103 | 0, // x8sub_4_then_sub_32 |
| 23104 | 0, // x8sub_3_then_sub_32 |
| 23105 | 0, // x8sub_2_then_sub_32 |
| 23106 | 0, // x8sub_1_then_sub_32 |
| 23107 | 0, // subo64_then_sub_32 |
| 23108 | 0, // zsub1_then_bsub |
| 23109 | 0, // zsub1_then_dsub |
| 23110 | 0, // zsub1_then_hsub |
| 23111 | 0, // zsub1_then_ssub |
| 23112 | 0, // zsub1_then_zsub |
| 23113 | 0, // zsub1_then_zsub_hi |
| 23114 | 0, // zsub3_then_bsub |
| 23115 | 0, // zsub3_then_dsub |
| 23116 | 0, // zsub3_then_hsub |
| 23117 | 0, // zsub3_then_ssub |
| 23118 | 0, // zsub3_then_zsub |
| 23119 | 0, // zsub3_then_zsub_hi |
| 23120 | 0, // zsub2_then_bsub |
| 23121 | 0, // zsub2_then_dsub |
| 23122 | 0, // zsub2_then_hsub |
| 23123 | 0, // zsub2_then_ssub |
| 23124 | 0, // zsub2_then_zsub |
| 23125 | 0, // zsub2_then_zsub_hi |
| 23126 | 0, // dsub0_dsub1 |
| 23127 | 0, // dsub0_dsub1_dsub2 |
| 23128 | 0, // dsub1_dsub2 |
| 23129 | 0, // dsub1_dsub2_dsub3 |
| 23130 | 0, // dsub2_dsub3 |
| 23131 | 0, // dsub_qsub1_then_dsub |
| 23132 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23133 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23134 | 0, // qsub0_qsub1 |
| 23135 | 0, // qsub0_qsub1_qsub2 |
| 23136 | 0, // qsub1_qsub2 |
| 23137 | 0, // qsub1_qsub2_qsub3 |
| 23138 | 0, // qsub2_qsub3 |
| 23139 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23140 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23141 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23142 | 0, // sub_32_x8sub_1_then_sub_32 |
| 23143 | 0, // x8sub_0_x8sub_1 |
| 23144 | 0, // x8sub_2_x8sub_3 |
| 23145 | 0, // x8sub_4_x8sub_5 |
| 23146 | 0, // x8sub_6_x8sub_7 |
| 23147 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 23148 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 23149 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 23150 | 0, // sub_32_subo64_then_sub_32 |
| 23151 | 0, // dsub_zsub1_then_dsub |
| 23152 | 0, // zsub_zsub1_then_zsub |
| 23153 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23154 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23155 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23156 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23157 | 0, // zsub0_zsub1 |
| 23158 | 0, // zsub0_zsub1_zsub2 |
| 23159 | 0, // zsub1_zsub2 |
| 23160 | 0, // zsub1_zsub2_zsub3 |
| 23161 | 0, // zsub2_zsub3 |
| 23162 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23163 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23164 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23165 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23166 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23167 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23168 | }, |
| 23169 | { // GPR64sponly |
| 23170 | 0, // bsub |
| 23171 | 0, // dsub |
| 23172 | 0, // dsub0 |
| 23173 | 0, // dsub1 |
| 23174 | 0, // dsub2 |
| 23175 | 0, // dsub3 |
| 23176 | 0, // hsub |
| 23177 | 0, // qhisub |
| 23178 | 0, // qsub |
| 23179 | 0, // qsub0 |
| 23180 | 0, // qsub1 |
| 23181 | 0, // qsub2 |
| 23182 | 0, // qsub3 |
| 23183 | 0, // ssub |
| 23184 | 81, // sub_32 -> GPR64sponly |
| 23185 | 0, // sube32 |
| 23186 | 0, // sube64 |
| 23187 | 0, // subo32 |
| 23188 | 0, // subo64 |
| 23189 | 0, // x8sub_0 |
| 23190 | 0, // x8sub_1 |
| 23191 | 0, // x8sub_2 |
| 23192 | 0, // x8sub_3 |
| 23193 | 0, // x8sub_4 |
| 23194 | 0, // x8sub_5 |
| 23195 | 0, // x8sub_6 |
| 23196 | 0, // x8sub_7 |
| 23197 | 0, // zsub |
| 23198 | 0, // zsub0 |
| 23199 | 0, // zsub1 |
| 23200 | 0, // zsub2 |
| 23201 | 0, // zsub3 |
| 23202 | 0, // zsub_hi |
| 23203 | 0, // dsub1_then_bsub |
| 23204 | 0, // dsub1_then_hsub |
| 23205 | 0, // dsub1_then_ssub |
| 23206 | 0, // dsub3_then_bsub |
| 23207 | 0, // dsub3_then_hsub |
| 23208 | 0, // dsub3_then_ssub |
| 23209 | 0, // dsub2_then_bsub |
| 23210 | 0, // dsub2_then_hsub |
| 23211 | 0, // dsub2_then_ssub |
| 23212 | 0, // qsub1_then_bsub |
| 23213 | 0, // qsub1_then_dsub |
| 23214 | 0, // qsub1_then_hsub |
| 23215 | 0, // qsub1_then_ssub |
| 23216 | 0, // qsub3_then_bsub |
| 23217 | 0, // qsub3_then_dsub |
| 23218 | 0, // qsub3_then_hsub |
| 23219 | 0, // qsub3_then_ssub |
| 23220 | 0, // qsub2_then_bsub |
| 23221 | 0, // qsub2_then_dsub |
| 23222 | 0, // qsub2_then_hsub |
| 23223 | 0, // qsub2_then_ssub |
| 23224 | 0, // x8sub_7_then_sub_32 |
| 23225 | 0, // x8sub_6_then_sub_32 |
| 23226 | 0, // x8sub_5_then_sub_32 |
| 23227 | 0, // x8sub_4_then_sub_32 |
| 23228 | 0, // x8sub_3_then_sub_32 |
| 23229 | 0, // x8sub_2_then_sub_32 |
| 23230 | 0, // x8sub_1_then_sub_32 |
| 23231 | 0, // subo64_then_sub_32 |
| 23232 | 0, // zsub1_then_bsub |
| 23233 | 0, // zsub1_then_dsub |
| 23234 | 0, // zsub1_then_hsub |
| 23235 | 0, // zsub1_then_ssub |
| 23236 | 0, // zsub1_then_zsub |
| 23237 | 0, // zsub1_then_zsub_hi |
| 23238 | 0, // zsub3_then_bsub |
| 23239 | 0, // zsub3_then_dsub |
| 23240 | 0, // zsub3_then_hsub |
| 23241 | 0, // zsub3_then_ssub |
| 23242 | 0, // zsub3_then_zsub |
| 23243 | 0, // zsub3_then_zsub_hi |
| 23244 | 0, // zsub2_then_bsub |
| 23245 | 0, // zsub2_then_dsub |
| 23246 | 0, // zsub2_then_hsub |
| 23247 | 0, // zsub2_then_ssub |
| 23248 | 0, // zsub2_then_zsub |
| 23249 | 0, // zsub2_then_zsub_hi |
| 23250 | 0, // dsub0_dsub1 |
| 23251 | 0, // dsub0_dsub1_dsub2 |
| 23252 | 0, // dsub1_dsub2 |
| 23253 | 0, // dsub1_dsub2_dsub3 |
| 23254 | 0, // dsub2_dsub3 |
| 23255 | 0, // dsub_qsub1_then_dsub |
| 23256 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23257 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23258 | 0, // qsub0_qsub1 |
| 23259 | 0, // qsub0_qsub1_qsub2 |
| 23260 | 0, // qsub1_qsub2 |
| 23261 | 0, // qsub1_qsub2_qsub3 |
| 23262 | 0, // qsub2_qsub3 |
| 23263 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23264 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23265 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23266 | 0, // sub_32_x8sub_1_then_sub_32 |
| 23267 | 0, // x8sub_0_x8sub_1 |
| 23268 | 0, // x8sub_2_x8sub_3 |
| 23269 | 0, // x8sub_4_x8sub_5 |
| 23270 | 0, // x8sub_6_x8sub_7 |
| 23271 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 23272 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 23273 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 23274 | 0, // sub_32_subo64_then_sub_32 |
| 23275 | 0, // dsub_zsub1_then_dsub |
| 23276 | 0, // zsub_zsub1_then_zsub |
| 23277 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23278 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23279 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23280 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23281 | 0, // zsub0_zsub1 |
| 23282 | 0, // zsub0_zsub1_zsub2 |
| 23283 | 0, // zsub1_zsub2 |
| 23284 | 0, // zsub1_zsub2_zsub3 |
| 23285 | 0, // zsub2_zsub3 |
| 23286 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23287 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23288 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23289 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23290 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23291 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23292 | }, |
| 23293 | { // GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23294 | 0, // bsub |
| 23295 | 0, // dsub |
| 23296 | 0, // dsub0 |
| 23297 | 0, // dsub1 |
| 23298 | 0, // dsub2 |
| 23299 | 0, // dsub3 |
| 23300 | 0, // hsub |
| 23301 | 0, // qhisub |
| 23302 | 0, // qsub |
| 23303 | 0, // qsub0 |
| 23304 | 0, // qsub1 |
| 23305 | 0, // qsub2 |
| 23306 | 0, // qsub3 |
| 23307 | 0, // ssub |
| 23308 | 82, // sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23309 | 0, // sube32 |
| 23310 | 0, // sube64 |
| 23311 | 0, // subo32 |
| 23312 | 0, // subo64 |
| 23313 | 82, // x8sub_0 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23314 | 82, // x8sub_1 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23315 | 82, // x8sub_2 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23316 | 82, // x8sub_3 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23317 | 82, // x8sub_4 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23318 | 82, // x8sub_5 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23319 | 82, // x8sub_6 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23320 | 82, // x8sub_7 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23321 | 0, // zsub |
| 23322 | 0, // zsub0 |
| 23323 | 0, // zsub1 |
| 23324 | 0, // zsub2 |
| 23325 | 0, // zsub3 |
| 23326 | 0, // zsub_hi |
| 23327 | 0, // dsub1_then_bsub |
| 23328 | 0, // dsub1_then_hsub |
| 23329 | 0, // dsub1_then_ssub |
| 23330 | 0, // dsub3_then_bsub |
| 23331 | 0, // dsub3_then_hsub |
| 23332 | 0, // dsub3_then_ssub |
| 23333 | 0, // dsub2_then_bsub |
| 23334 | 0, // dsub2_then_hsub |
| 23335 | 0, // dsub2_then_ssub |
| 23336 | 0, // qsub1_then_bsub |
| 23337 | 0, // qsub1_then_dsub |
| 23338 | 0, // qsub1_then_hsub |
| 23339 | 0, // qsub1_then_ssub |
| 23340 | 0, // qsub3_then_bsub |
| 23341 | 0, // qsub3_then_dsub |
| 23342 | 0, // qsub3_then_hsub |
| 23343 | 0, // qsub3_then_ssub |
| 23344 | 0, // qsub2_then_bsub |
| 23345 | 0, // qsub2_then_dsub |
| 23346 | 0, // qsub2_then_hsub |
| 23347 | 0, // qsub2_then_ssub |
| 23348 | 82, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23349 | 82, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23350 | 82, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23351 | 82, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23352 | 82, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23353 | 82, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23354 | 82, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23355 | 0, // subo64_then_sub_32 |
| 23356 | 0, // zsub1_then_bsub |
| 23357 | 0, // zsub1_then_dsub |
| 23358 | 0, // zsub1_then_hsub |
| 23359 | 0, // zsub1_then_ssub |
| 23360 | 0, // zsub1_then_zsub |
| 23361 | 0, // zsub1_then_zsub_hi |
| 23362 | 0, // zsub3_then_bsub |
| 23363 | 0, // zsub3_then_dsub |
| 23364 | 0, // zsub3_then_hsub |
| 23365 | 0, // zsub3_then_ssub |
| 23366 | 0, // zsub3_then_zsub |
| 23367 | 0, // zsub3_then_zsub_hi |
| 23368 | 0, // zsub2_then_bsub |
| 23369 | 0, // zsub2_then_dsub |
| 23370 | 0, // zsub2_then_hsub |
| 23371 | 0, // zsub2_then_ssub |
| 23372 | 0, // zsub2_then_zsub |
| 23373 | 0, // zsub2_then_zsub_hi |
| 23374 | 0, // dsub0_dsub1 |
| 23375 | 0, // dsub0_dsub1_dsub2 |
| 23376 | 0, // dsub1_dsub2 |
| 23377 | 0, // dsub1_dsub2_dsub3 |
| 23378 | 0, // dsub2_dsub3 |
| 23379 | 0, // dsub_qsub1_then_dsub |
| 23380 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23381 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23382 | 0, // qsub0_qsub1 |
| 23383 | 0, // qsub0_qsub1_qsub2 |
| 23384 | 0, // qsub1_qsub2 |
| 23385 | 0, // qsub1_qsub2_qsub3 |
| 23386 | 0, // qsub2_qsub3 |
| 23387 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23388 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23389 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23390 | 82, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23391 | 82, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23392 | 82, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23393 | 82, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23394 | 82, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23395 | 82, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23396 | 82, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23397 | 82, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 23398 | 0, // sub_32_subo64_then_sub_32 |
| 23399 | 0, // dsub_zsub1_then_dsub |
| 23400 | 0, // zsub_zsub1_then_zsub |
| 23401 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23402 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23403 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23404 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23405 | 0, // zsub0_zsub1 |
| 23406 | 0, // zsub0_zsub1_zsub2 |
| 23407 | 0, // zsub1_zsub2 |
| 23408 | 0, // zsub1_zsub2_zsub3 |
| 23409 | 0, // zsub2_zsub3 |
| 23410 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23411 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23412 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23413 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23414 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23415 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23416 | }, |
| 23417 | { // GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23418 | 0, // bsub |
| 23419 | 0, // dsub |
| 23420 | 0, // dsub0 |
| 23421 | 0, // dsub1 |
| 23422 | 0, // dsub2 |
| 23423 | 0, // dsub3 |
| 23424 | 0, // hsub |
| 23425 | 0, // qhisub |
| 23426 | 0, // qsub |
| 23427 | 0, // qsub0 |
| 23428 | 0, // qsub1 |
| 23429 | 0, // qsub2 |
| 23430 | 0, // qsub3 |
| 23431 | 0, // ssub |
| 23432 | 83, // sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23433 | 0, // sube32 |
| 23434 | 0, // sube64 |
| 23435 | 0, // subo32 |
| 23436 | 0, // subo64 |
| 23437 | 83, // x8sub_0 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23438 | 83, // x8sub_1 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23439 | 83, // x8sub_2 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23440 | 83, // x8sub_3 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23441 | 83, // x8sub_4 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23442 | 83, // x8sub_5 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23443 | 83, // x8sub_6 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23444 | 83, // x8sub_7 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23445 | 0, // zsub |
| 23446 | 0, // zsub0 |
| 23447 | 0, // zsub1 |
| 23448 | 0, // zsub2 |
| 23449 | 0, // zsub3 |
| 23450 | 0, // zsub_hi |
| 23451 | 0, // dsub1_then_bsub |
| 23452 | 0, // dsub1_then_hsub |
| 23453 | 0, // dsub1_then_ssub |
| 23454 | 0, // dsub3_then_bsub |
| 23455 | 0, // dsub3_then_hsub |
| 23456 | 0, // dsub3_then_ssub |
| 23457 | 0, // dsub2_then_bsub |
| 23458 | 0, // dsub2_then_hsub |
| 23459 | 0, // dsub2_then_ssub |
| 23460 | 0, // qsub1_then_bsub |
| 23461 | 0, // qsub1_then_dsub |
| 23462 | 0, // qsub1_then_hsub |
| 23463 | 0, // qsub1_then_ssub |
| 23464 | 0, // qsub3_then_bsub |
| 23465 | 0, // qsub3_then_dsub |
| 23466 | 0, // qsub3_then_hsub |
| 23467 | 0, // qsub3_then_ssub |
| 23468 | 0, // qsub2_then_bsub |
| 23469 | 0, // qsub2_then_dsub |
| 23470 | 0, // qsub2_then_hsub |
| 23471 | 0, // qsub2_then_ssub |
| 23472 | 83, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23473 | 83, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23474 | 83, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23475 | 83, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23476 | 83, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23477 | 83, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23478 | 83, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23479 | 0, // subo64_then_sub_32 |
| 23480 | 0, // zsub1_then_bsub |
| 23481 | 0, // zsub1_then_dsub |
| 23482 | 0, // zsub1_then_hsub |
| 23483 | 0, // zsub1_then_ssub |
| 23484 | 0, // zsub1_then_zsub |
| 23485 | 0, // zsub1_then_zsub_hi |
| 23486 | 0, // zsub3_then_bsub |
| 23487 | 0, // zsub3_then_dsub |
| 23488 | 0, // zsub3_then_hsub |
| 23489 | 0, // zsub3_then_ssub |
| 23490 | 0, // zsub3_then_zsub |
| 23491 | 0, // zsub3_then_zsub_hi |
| 23492 | 0, // zsub2_then_bsub |
| 23493 | 0, // zsub2_then_dsub |
| 23494 | 0, // zsub2_then_hsub |
| 23495 | 0, // zsub2_then_ssub |
| 23496 | 0, // zsub2_then_zsub |
| 23497 | 0, // zsub2_then_zsub_hi |
| 23498 | 0, // dsub0_dsub1 |
| 23499 | 0, // dsub0_dsub1_dsub2 |
| 23500 | 0, // dsub1_dsub2 |
| 23501 | 0, // dsub1_dsub2_dsub3 |
| 23502 | 0, // dsub2_dsub3 |
| 23503 | 0, // dsub_qsub1_then_dsub |
| 23504 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23505 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23506 | 0, // qsub0_qsub1 |
| 23507 | 0, // qsub0_qsub1_qsub2 |
| 23508 | 0, // qsub1_qsub2 |
| 23509 | 0, // qsub1_qsub2_qsub3 |
| 23510 | 0, // qsub2_qsub3 |
| 23511 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23512 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23513 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23514 | 83, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23515 | 83, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23516 | 83, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23517 | 83, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23518 | 83, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23519 | 83, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23520 | 83, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23521 | 83, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 23522 | 0, // sub_32_subo64_then_sub_32 |
| 23523 | 0, // dsub_zsub1_then_dsub |
| 23524 | 0, // zsub_zsub1_then_zsub |
| 23525 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23526 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23527 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23528 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23529 | 0, // zsub0_zsub1 |
| 23530 | 0, // zsub0_zsub1_zsub2 |
| 23531 | 0, // zsub1_zsub2 |
| 23532 | 0, // zsub1_zsub2_zsub3 |
| 23533 | 0, // zsub2_zsub3 |
| 23534 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23535 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23536 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23537 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23538 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23539 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23540 | }, |
| 23541 | { // GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23542 | 0, // bsub |
| 23543 | 0, // dsub |
| 23544 | 0, // dsub0 |
| 23545 | 0, // dsub1 |
| 23546 | 0, // dsub2 |
| 23547 | 0, // dsub3 |
| 23548 | 0, // hsub |
| 23549 | 0, // qhisub |
| 23550 | 0, // qsub |
| 23551 | 0, // qsub0 |
| 23552 | 0, // qsub1 |
| 23553 | 0, // qsub2 |
| 23554 | 0, // qsub3 |
| 23555 | 0, // ssub |
| 23556 | 84, // sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23557 | 0, // sube32 |
| 23558 | 0, // sube64 |
| 23559 | 0, // subo32 |
| 23560 | 0, // subo64 |
| 23561 | 84, // x8sub_0 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23562 | 84, // x8sub_1 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23563 | 84, // x8sub_2 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23564 | 84, // x8sub_3 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23565 | 84, // x8sub_4 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23566 | 84, // x8sub_5 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23567 | 84, // x8sub_6 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23568 | 84, // x8sub_7 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23569 | 0, // zsub |
| 23570 | 0, // zsub0 |
| 23571 | 0, // zsub1 |
| 23572 | 0, // zsub2 |
| 23573 | 0, // zsub3 |
| 23574 | 0, // zsub_hi |
| 23575 | 0, // dsub1_then_bsub |
| 23576 | 0, // dsub1_then_hsub |
| 23577 | 0, // dsub1_then_ssub |
| 23578 | 0, // dsub3_then_bsub |
| 23579 | 0, // dsub3_then_hsub |
| 23580 | 0, // dsub3_then_ssub |
| 23581 | 0, // dsub2_then_bsub |
| 23582 | 0, // dsub2_then_hsub |
| 23583 | 0, // dsub2_then_ssub |
| 23584 | 0, // qsub1_then_bsub |
| 23585 | 0, // qsub1_then_dsub |
| 23586 | 0, // qsub1_then_hsub |
| 23587 | 0, // qsub1_then_ssub |
| 23588 | 0, // qsub3_then_bsub |
| 23589 | 0, // qsub3_then_dsub |
| 23590 | 0, // qsub3_then_hsub |
| 23591 | 0, // qsub3_then_ssub |
| 23592 | 0, // qsub2_then_bsub |
| 23593 | 0, // qsub2_then_dsub |
| 23594 | 0, // qsub2_then_hsub |
| 23595 | 0, // qsub2_then_ssub |
| 23596 | 84, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23597 | 84, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23598 | 84, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23599 | 84, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23600 | 84, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23601 | 84, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23602 | 84, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23603 | 0, // subo64_then_sub_32 |
| 23604 | 0, // zsub1_then_bsub |
| 23605 | 0, // zsub1_then_dsub |
| 23606 | 0, // zsub1_then_hsub |
| 23607 | 0, // zsub1_then_ssub |
| 23608 | 0, // zsub1_then_zsub |
| 23609 | 0, // zsub1_then_zsub_hi |
| 23610 | 0, // zsub3_then_bsub |
| 23611 | 0, // zsub3_then_dsub |
| 23612 | 0, // zsub3_then_hsub |
| 23613 | 0, // zsub3_then_ssub |
| 23614 | 0, // zsub3_then_zsub |
| 23615 | 0, // zsub3_then_zsub_hi |
| 23616 | 0, // zsub2_then_bsub |
| 23617 | 0, // zsub2_then_dsub |
| 23618 | 0, // zsub2_then_hsub |
| 23619 | 0, // zsub2_then_ssub |
| 23620 | 0, // zsub2_then_zsub |
| 23621 | 0, // zsub2_then_zsub_hi |
| 23622 | 0, // dsub0_dsub1 |
| 23623 | 0, // dsub0_dsub1_dsub2 |
| 23624 | 0, // dsub1_dsub2 |
| 23625 | 0, // dsub1_dsub2_dsub3 |
| 23626 | 0, // dsub2_dsub3 |
| 23627 | 0, // dsub_qsub1_then_dsub |
| 23628 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23629 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23630 | 0, // qsub0_qsub1 |
| 23631 | 0, // qsub0_qsub1_qsub2 |
| 23632 | 0, // qsub1_qsub2 |
| 23633 | 0, // qsub1_qsub2_qsub3 |
| 23634 | 0, // qsub2_qsub3 |
| 23635 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23636 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23637 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23638 | 84, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23639 | 84, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23640 | 84, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23641 | 84, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23642 | 84, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23643 | 84, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23644 | 84, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23645 | 84, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 23646 | 0, // sub_32_subo64_then_sub_32 |
| 23647 | 0, // dsub_zsub1_then_dsub |
| 23648 | 0, // zsub_zsub1_then_zsub |
| 23649 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23650 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23651 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23652 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23653 | 0, // zsub0_zsub1 |
| 23654 | 0, // zsub0_zsub1_zsub2 |
| 23655 | 0, // zsub1_zsub2 |
| 23656 | 0, // zsub1_zsub2_zsub3 |
| 23657 | 0, // zsub2_zsub3 |
| 23658 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23659 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23660 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23661 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23662 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23663 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23664 | }, |
| 23665 | { // GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23666 | 0, // bsub |
| 23667 | 0, // dsub |
| 23668 | 0, // dsub0 |
| 23669 | 0, // dsub1 |
| 23670 | 0, // dsub2 |
| 23671 | 0, // dsub3 |
| 23672 | 0, // hsub |
| 23673 | 0, // qhisub |
| 23674 | 0, // qsub |
| 23675 | 0, // qsub0 |
| 23676 | 0, // qsub1 |
| 23677 | 0, // qsub2 |
| 23678 | 0, // qsub3 |
| 23679 | 0, // ssub |
| 23680 | 85, // sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23681 | 0, // sube32 |
| 23682 | 0, // sube64 |
| 23683 | 0, // subo32 |
| 23684 | 0, // subo64 |
| 23685 | 85, // x8sub_0 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23686 | 85, // x8sub_1 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23687 | 85, // x8sub_2 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23688 | 85, // x8sub_3 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23689 | 85, // x8sub_4 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23690 | 85, // x8sub_5 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23691 | 85, // x8sub_6 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23692 | 85, // x8sub_7 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23693 | 0, // zsub |
| 23694 | 0, // zsub0 |
| 23695 | 0, // zsub1 |
| 23696 | 0, // zsub2 |
| 23697 | 0, // zsub3 |
| 23698 | 0, // zsub_hi |
| 23699 | 0, // dsub1_then_bsub |
| 23700 | 0, // dsub1_then_hsub |
| 23701 | 0, // dsub1_then_ssub |
| 23702 | 0, // dsub3_then_bsub |
| 23703 | 0, // dsub3_then_hsub |
| 23704 | 0, // dsub3_then_ssub |
| 23705 | 0, // dsub2_then_bsub |
| 23706 | 0, // dsub2_then_hsub |
| 23707 | 0, // dsub2_then_ssub |
| 23708 | 0, // qsub1_then_bsub |
| 23709 | 0, // qsub1_then_dsub |
| 23710 | 0, // qsub1_then_hsub |
| 23711 | 0, // qsub1_then_ssub |
| 23712 | 0, // qsub3_then_bsub |
| 23713 | 0, // qsub3_then_dsub |
| 23714 | 0, // qsub3_then_hsub |
| 23715 | 0, // qsub3_then_ssub |
| 23716 | 0, // qsub2_then_bsub |
| 23717 | 0, // qsub2_then_dsub |
| 23718 | 0, // qsub2_then_hsub |
| 23719 | 0, // qsub2_then_ssub |
| 23720 | 85, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23721 | 85, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23722 | 85, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23723 | 85, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23724 | 85, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23725 | 85, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23726 | 85, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23727 | 0, // subo64_then_sub_32 |
| 23728 | 0, // zsub1_then_bsub |
| 23729 | 0, // zsub1_then_dsub |
| 23730 | 0, // zsub1_then_hsub |
| 23731 | 0, // zsub1_then_ssub |
| 23732 | 0, // zsub1_then_zsub |
| 23733 | 0, // zsub1_then_zsub_hi |
| 23734 | 0, // zsub3_then_bsub |
| 23735 | 0, // zsub3_then_dsub |
| 23736 | 0, // zsub3_then_hsub |
| 23737 | 0, // zsub3_then_ssub |
| 23738 | 0, // zsub3_then_zsub |
| 23739 | 0, // zsub3_then_zsub_hi |
| 23740 | 0, // zsub2_then_bsub |
| 23741 | 0, // zsub2_then_dsub |
| 23742 | 0, // zsub2_then_hsub |
| 23743 | 0, // zsub2_then_ssub |
| 23744 | 0, // zsub2_then_zsub |
| 23745 | 0, // zsub2_then_zsub_hi |
| 23746 | 0, // dsub0_dsub1 |
| 23747 | 0, // dsub0_dsub1_dsub2 |
| 23748 | 0, // dsub1_dsub2 |
| 23749 | 0, // dsub1_dsub2_dsub3 |
| 23750 | 0, // dsub2_dsub3 |
| 23751 | 0, // dsub_qsub1_then_dsub |
| 23752 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23753 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23754 | 0, // qsub0_qsub1 |
| 23755 | 0, // qsub0_qsub1_qsub2 |
| 23756 | 0, // qsub1_qsub2 |
| 23757 | 0, // qsub1_qsub2_qsub3 |
| 23758 | 0, // qsub2_qsub3 |
| 23759 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23760 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23761 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23762 | 85, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23763 | 85, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23764 | 85, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23765 | 85, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23766 | 85, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23767 | 85, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23768 | 85, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23769 | 85, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 23770 | 0, // sub_32_subo64_then_sub_32 |
| 23771 | 0, // dsub_zsub1_then_dsub |
| 23772 | 0, // zsub_zsub1_then_zsub |
| 23773 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23774 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23775 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23776 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23777 | 0, // zsub0_zsub1 |
| 23778 | 0, // zsub0_zsub1_zsub2 |
| 23779 | 0, // zsub1_zsub2 |
| 23780 | 0, // zsub1_zsub2_zsub3 |
| 23781 | 0, // zsub2_zsub3 |
| 23782 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23783 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23784 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23785 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23786 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23787 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23788 | }, |
| 23789 | { // GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23790 | 0, // bsub |
| 23791 | 0, // dsub |
| 23792 | 0, // dsub0 |
| 23793 | 0, // dsub1 |
| 23794 | 0, // dsub2 |
| 23795 | 0, // dsub3 |
| 23796 | 0, // hsub |
| 23797 | 0, // qhisub |
| 23798 | 0, // qsub |
| 23799 | 0, // qsub0 |
| 23800 | 0, // qsub1 |
| 23801 | 0, // qsub2 |
| 23802 | 0, // qsub3 |
| 23803 | 0, // ssub |
| 23804 | 86, // sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23805 | 0, // sube32 |
| 23806 | 0, // sube64 |
| 23807 | 0, // subo32 |
| 23808 | 0, // subo64 |
| 23809 | 86, // x8sub_0 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23810 | 86, // x8sub_1 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23811 | 86, // x8sub_2 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23812 | 86, // x8sub_3 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23813 | 86, // x8sub_4 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23814 | 86, // x8sub_5 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23815 | 86, // x8sub_6 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23816 | 86, // x8sub_7 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23817 | 0, // zsub |
| 23818 | 0, // zsub0 |
| 23819 | 0, // zsub1 |
| 23820 | 0, // zsub2 |
| 23821 | 0, // zsub3 |
| 23822 | 0, // zsub_hi |
| 23823 | 0, // dsub1_then_bsub |
| 23824 | 0, // dsub1_then_hsub |
| 23825 | 0, // dsub1_then_ssub |
| 23826 | 0, // dsub3_then_bsub |
| 23827 | 0, // dsub3_then_hsub |
| 23828 | 0, // dsub3_then_ssub |
| 23829 | 0, // dsub2_then_bsub |
| 23830 | 0, // dsub2_then_hsub |
| 23831 | 0, // dsub2_then_ssub |
| 23832 | 0, // qsub1_then_bsub |
| 23833 | 0, // qsub1_then_dsub |
| 23834 | 0, // qsub1_then_hsub |
| 23835 | 0, // qsub1_then_ssub |
| 23836 | 0, // qsub3_then_bsub |
| 23837 | 0, // qsub3_then_dsub |
| 23838 | 0, // qsub3_then_hsub |
| 23839 | 0, // qsub3_then_ssub |
| 23840 | 0, // qsub2_then_bsub |
| 23841 | 0, // qsub2_then_dsub |
| 23842 | 0, // qsub2_then_hsub |
| 23843 | 0, // qsub2_then_ssub |
| 23844 | 86, // x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23845 | 86, // x8sub_6_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23846 | 86, // x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23847 | 86, // x8sub_4_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23848 | 86, // x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23849 | 86, // x8sub_2_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23850 | 86, // x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23851 | 0, // subo64_then_sub_32 |
| 23852 | 0, // zsub1_then_bsub |
| 23853 | 0, // zsub1_then_dsub |
| 23854 | 0, // zsub1_then_hsub |
| 23855 | 0, // zsub1_then_ssub |
| 23856 | 0, // zsub1_then_zsub |
| 23857 | 0, // zsub1_then_zsub_hi |
| 23858 | 0, // zsub3_then_bsub |
| 23859 | 0, // zsub3_then_dsub |
| 23860 | 0, // zsub3_then_hsub |
| 23861 | 0, // zsub3_then_ssub |
| 23862 | 0, // zsub3_then_zsub |
| 23863 | 0, // zsub3_then_zsub_hi |
| 23864 | 0, // zsub2_then_bsub |
| 23865 | 0, // zsub2_then_dsub |
| 23866 | 0, // zsub2_then_hsub |
| 23867 | 0, // zsub2_then_ssub |
| 23868 | 0, // zsub2_then_zsub |
| 23869 | 0, // zsub2_then_zsub_hi |
| 23870 | 0, // dsub0_dsub1 |
| 23871 | 0, // dsub0_dsub1_dsub2 |
| 23872 | 0, // dsub1_dsub2 |
| 23873 | 0, // dsub1_dsub2_dsub3 |
| 23874 | 0, // dsub2_dsub3 |
| 23875 | 0, // dsub_qsub1_then_dsub |
| 23876 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23877 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 23878 | 0, // qsub0_qsub1 |
| 23879 | 0, // qsub0_qsub1_qsub2 |
| 23880 | 0, // qsub1_qsub2 |
| 23881 | 0, // qsub1_qsub2_qsub3 |
| 23882 | 0, // qsub2_qsub3 |
| 23883 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 23884 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 23885 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 23886 | 86, // sub_32_x8sub_1_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23887 | 86, // x8sub_0_x8sub_1 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23888 | 86, // x8sub_2_x8sub_3 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23889 | 86, // x8sub_4_x8sub_5 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23890 | 86, // x8sub_6_x8sub_7 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23891 | 86, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23892 | 86, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23893 | 86, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 -> GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 23894 | 0, // sub_32_subo64_then_sub_32 |
| 23895 | 0, // dsub_zsub1_then_dsub |
| 23896 | 0, // zsub_zsub1_then_zsub |
| 23897 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23898 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 23899 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23900 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 23901 | 0, // zsub0_zsub1 |
| 23902 | 0, // zsub0_zsub1_zsub2 |
| 23903 | 0, // zsub1_zsub2 |
| 23904 | 0, // zsub1_zsub2_zsub3 |
| 23905 | 0, // zsub2_zsub3 |
| 23906 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 23907 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 23908 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 23909 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 23910 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 23911 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 23912 | }, |
| 23913 | { // DD |
| 23914 | 87, // bsub -> DD |
| 23915 | 0, // dsub |
| 23916 | 87, // dsub0 -> DD |
| 23917 | 87, // dsub1 -> DD |
| 23918 | 0, // dsub2 |
| 23919 | 0, // dsub3 |
| 23920 | 87, // hsub -> DD |
| 23921 | 0, // qhisub |
| 23922 | 0, // qsub |
| 23923 | 0, // qsub0 |
| 23924 | 0, // qsub1 |
| 23925 | 0, // qsub2 |
| 23926 | 0, // qsub3 |
| 23927 | 87, // ssub -> DD |
| 23928 | 0, // sub_32 |
| 23929 | 0, // sube32 |
| 23930 | 0, // sube64 |
| 23931 | 0, // subo32 |
| 23932 | 0, // subo64 |
| 23933 | 0, // x8sub_0 |
| 23934 | 0, // x8sub_1 |
| 23935 | 0, // x8sub_2 |
| 23936 | 0, // x8sub_3 |
| 23937 | 0, // x8sub_4 |
| 23938 | 0, // x8sub_5 |
| 23939 | 0, // x8sub_6 |
| 23940 | 0, // x8sub_7 |
| 23941 | 0, // zsub |
| 23942 | 0, // zsub0 |
| 23943 | 0, // zsub1 |
| 23944 | 0, // zsub2 |
| 23945 | 0, // zsub3 |
| 23946 | 0, // zsub_hi |
| 23947 | 87, // dsub1_then_bsub -> DD |
| 23948 | 87, // dsub1_then_hsub -> DD |
| 23949 | 87, // dsub1_then_ssub -> DD |
| 23950 | 0, // dsub3_then_bsub |
| 23951 | 0, // dsub3_then_hsub |
| 23952 | 0, // dsub3_then_ssub |
| 23953 | 0, // dsub2_then_bsub |
| 23954 | 0, // dsub2_then_hsub |
| 23955 | 0, // dsub2_then_ssub |
| 23956 | 0, // qsub1_then_bsub |
| 23957 | 0, // qsub1_then_dsub |
| 23958 | 0, // qsub1_then_hsub |
| 23959 | 0, // qsub1_then_ssub |
| 23960 | 0, // qsub3_then_bsub |
| 23961 | 0, // qsub3_then_dsub |
| 23962 | 0, // qsub3_then_hsub |
| 23963 | 0, // qsub3_then_ssub |
| 23964 | 0, // qsub2_then_bsub |
| 23965 | 0, // qsub2_then_dsub |
| 23966 | 0, // qsub2_then_hsub |
| 23967 | 0, // qsub2_then_ssub |
| 23968 | 0, // x8sub_7_then_sub_32 |
| 23969 | 0, // x8sub_6_then_sub_32 |
| 23970 | 0, // x8sub_5_then_sub_32 |
| 23971 | 0, // x8sub_4_then_sub_32 |
| 23972 | 0, // x8sub_3_then_sub_32 |
| 23973 | 0, // x8sub_2_then_sub_32 |
| 23974 | 0, // x8sub_1_then_sub_32 |
| 23975 | 0, // subo64_then_sub_32 |
| 23976 | 0, // zsub1_then_bsub |
| 23977 | 0, // zsub1_then_dsub |
| 23978 | 0, // zsub1_then_hsub |
| 23979 | 0, // zsub1_then_ssub |
| 23980 | 0, // zsub1_then_zsub |
| 23981 | 0, // zsub1_then_zsub_hi |
| 23982 | 0, // zsub3_then_bsub |
| 23983 | 0, // zsub3_then_dsub |
| 23984 | 0, // zsub3_then_hsub |
| 23985 | 0, // zsub3_then_ssub |
| 23986 | 0, // zsub3_then_zsub |
| 23987 | 0, // zsub3_then_zsub_hi |
| 23988 | 0, // zsub2_then_bsub |
| 23989 | 0, // zsub2_then_dsub |
| 23990 | 0, // zsub2_then_hsub |
| 23991 | 0, // zsub2_then_ssub |
| 23992 | 0, // zsub2_then_zsub |
| 23993 | 0, // zsub2_then_zsub_hi |
| 23994 | 0, // dsub0_dsub1 |
| 23995 | 0, // dsub0_dsub1_dsub2 |
| 23996 | 0, // dsub1_dsub2 |
| 23997 | 0, // dsub1_dsub2_dsub3 |
| 23998 | 0, // dsub2_dsub3 |
| 23999 | 0, // dsub_qsub1_then_dsub |
| 24000 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24001 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24002 | 0, // qsub0_qsub1 |
| 24003 | 0, // qsub0_qsub1_qsub2 |
| 24004 | 0, // qsub1_qsub2 |
| 24005 | 0, // qsub1_qsub2_qsub3 |
| 24006 | 0, // qsub2_qsub3 |
| 24007 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24008 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24009 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24010 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24011 | 0, // x8sub_0_x8sub_1 |
| 24012 | 0, // x8sub_2_x8sub_3 |
| 24013 | 0, // x8sub_4_x8sub_5 |
| 24014 | 0, // x8sub_6_x8sub_7 |
| 24015 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24016 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24017 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24018 | 0, // sub_32_subo64_then_sub_32 |
| 24019 | 0, // dsub_zsub1_then_dsub |
| 24020 | 0, // zsub_zsub1_then_zsub |
| 24021 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24022 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24023 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24024 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24025 | 0, // zsub0_zsub1 |
| 24026 | 0, // zsub0_zsub1_zsub2 |
| 24027 | 0, // zsub1_zsub2 |
| 24028 | 0, // zsub1_zsub2_zsub3 |
| 24029 | 0, // zsub2_zsub3 |
| 24030 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24031 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24032 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24033 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24034 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24035 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24036 | }, |
| 24037 | { // DD_with_dsub0_in_FPR64_lo |
| 24038 | 88, // bsub -> DD_with_dsub0_in_FPR64_lo |
| 24039 | 0, // dsub |
| 24040 | 88, // dsub0 -> DD_with_dsub0_in_FPR64_lo |
| 24041 | 88, // dsub1 -> DD_with_dsub0_in_FPR64_lo |
| 24042 | 0, // dsub2 |
| 24043 | 0, // dsub3 |
| 24044 | 88, // hsub -> DD_with_dsub0_in_FPR64_lo |
| 24045 | 0, // qhisub |
| 24046 | 0, // qsub |
| 24047 | 0, // qsub0 |
| 24048 | 0, // qsub1 |
| 24049 | 0, // qsub2 |
| 24050 | 0, // qsub3 |
| 24051 | 88, // ssub -> DD_with_dsub0_in_FPR64_lo |
| 24052 | 0, // sub_32 |
| 24053 | 0, // sube32 |
| 24054 | 0, // sube64 |
| 24055 | 0, // subo32 |
| 24056 | 0, // subo64 |
| 24057 | 0, // x8sub_0 |
| 24058 | 0, // x8sub_1 |
| 24059 | 0, // x8sub_2 |
| 24060 | 0, // x8sub_3 |
| 24061 | 0, // x8sub_4 |
| 24062 | 0, // x8sub_5 |
| 24063 | 0, // x8sub_6 |
| 24064 | 0, // x8sub_7 |
| 24065 | 0, // zsub |
| 24066 | 0, // zsub0 |
| 24067 | 0, // zsub1 |
| 24068 | 0, // zsub2 |
| 24069 | 0, // zsub3 |
| 24070 | 0, // zsub_hi |
| 24071 | 88, // dsub1_then_bsub -> DD_with_dsub0_in_FPR64_lo |
| 24072 | 88, // dsub1_then_hsub -> DD_with_dsub0_in_FPR64_lo |
| 24073 | 88, // dsub1_then_ssub -> DD_with_dsub0_in_FPR64_lo |
| 24074 | 0, // dsub3_then_bsub |
| 24075 | 0, // dsub3_then_hsub |
| 24076 | 0, // dsub3_then_ssub |
| 24077 | 0, // dsub2_then_bsub |
| 24078 | 0, // dsub2_then_hsub |
| 24079 | 0, // dsub2_then_ssub |
| 24080 | 0, // qsub1_then_bsub |
| 24081 | 0, // qsub1_then_dsub |
| 24082 | 0, // qsub1_then_hsub |
| 24083 | 0, // qsub1_then_ssub |
| 24084 | 0, // qsub3_then_bsub |
| 24085 | 0, // qsub3_then_dsub |
| 24086 | 0, // qsub3_then_hsub |
| 24087 | 0, // qsub3_then_ssub |
| 24088 | 0, // qsub2_then_bsub |
| 24089 | 0, // qsub2_then_dsub |
| 24090 | 0, // qsub2_then_hsub |
| 24091 | 0, // qsub2_then_ssub |
| 24092 | 0, // x8sub_7_then_sub_32 |
| 24093 | 0, // x8sub_6_then_sub_32 |
| 24094 | 0, // x8sub_5_then_sub_32 |
| 24095 | 0, // x8sub_4_then_sub_32 |
| 24096 | 0, // x8sub_3_then_sub_32 |
| 24097 | 0, // x8sub_2_then_sub_32 |
| 24098 | 0, // x8sub_1_then_sub_32 |
| 24099 | 0, // subo64_then_sub_32 |
| 24100 | 0, // zsub1_then_bsub |
| 24101 | 0, // zsub1_then_dsub |
| 24102 | 0, // zsub1_then_hsub |
| 24103 | 0, // zsub1_then_ssub |
| 24104 | 0, // zsub1_then_zsub |
| 24105 | 0, // zsub1_then_zsub_hi |
| 24106 | 0, // zsub3_then_bsub |
| 24107 | 0, // zsub3_then_dsub |
| 24108 | 0, // zsub3_then_hsub |
| 24109 | 0, // zsub3_then_ssub |
| 24110 | 0, // zsub3_then_zsub |
| 24111 | 0, // zsub3_then_zsub_hi |
| 24112 | 0, // zsub2_then_bsub |
| 24113 | 0, // zsub2_then_dsub |
| 24114 | 0, // zsub2_then_hsub |
| 24115 | 0, // zsub2_then_ssub |
| 24116 | 0, // zsub2_then_zsub |
| 24117 | 0, // zsub2_then_zsub_hi |
| 24118 | 0, // dsub0_dsub1 |
| 24119 | 0, // dsub0_dsub1_dsub2 |
| 24120 | 0, // dsub1_dsub2 |
| 24121 | 0, // dsub1_dsub2_dsub3 |
| 24122 | 0, // dsub2_dsub3 |
| 24123 | 0, // dsub_qsub1_then_dsub |
| 24124 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24125 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24126 | 0, // qsub0_qsub1 |
| 24127 | 0, // qsub0_qsub1_qsub2 |
| 24128 | 0, // qsub1_qsub2 |
| 24129 | 0, // qsub1_qsub2_qsub3 |
| 24130 | 0, // qsub2_qsub3 |
| 24131 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24132 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24133 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24134 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24135 | 0, // x8sub_0_x8sub_1 |
| 24136 | 0, // x8sub_2_x8sub_3 |
| 24137 | 0, // x8sub_4_x8sub_5 |
| 24138 | 0, // x8sub_6_x8sub_7 |
| 24139 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24140 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24141 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24142 | 0, // sub_32_subo64_then_sub_32 |
| 24143 | 0, // dsub_zsub1_then_dsub |
| 24144 | 0, // zsub_zsub1_then_zsub |
| 24145 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24146 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24147 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24148 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24149 | 0, // zsub0_zsub1 |
| 24150 | 0, // zsub0_zsub1_zsub2 |
| 24151 | 0, // zsub1_zsub2 |
| 24152 | 0, // zsub1_zsub2_zsub3 |
| 24153 | 0, // zsub2_zsub3 |
| 24154 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24155 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24156 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24157 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24158 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24159 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24160 | }, |
| 24161 | { // DD_with_dsub1_in_FPR64_lo |
| 24162 | 89, // bsub -> DD_with_dsub1_in_FPR64_lo |
| 24163 | 0, // dsub |
| 24164 | 89, // dsub0 -> DD_with_dsub1_in_FPR64_lo |
| 24165 | 89, // dsub1 -> DD_with_dsub1_in_FPR64_lo |
| 24166 | 0, // dsub2 |
| 24167 | 0, // dsub3 |
| 24168 | 89, // hsub -> DD_with_dsub1_in_FPR64_lo |
| 24169 | 0, // qhisub |
| 24170 | 0, // qsub |
| 24171 | 0, // qsub0 |
| 24172 | 0, // qsub1 |
| 24173 | 0, // qsub2 |
| 24174 | 0, // qsub3 |
| 24175 | 89, // ssub -> DD_with_dsub1_in_FPR64_lo |
| 24176 | 0, // sub_32 |
| 24177 | 0, // sube32 |
| 24178 | 0, // sube64 |
| 24179 | 0, // subo32 |
| 24180 | 0, // subo64 |
| 24181 | 0, // x8sub_0 |
| 24182 | 0, // x8sub_1 |
| 24183 | 0, // x8sub_2 |
| 24184 | 0, // x8sub_3 |
| 24185 | 0, // x8sub_4 |
| 24186 | 0, // x8sub_5 |
| 24187 | 0, // x8sub_6 |
| 24188 | 0, // x8sub_7 |
| 24189 | 0, // zsub |
| 24190 | 0, // zsub0 |
| 24191 | 0, // zsub1 |
| 24192 | 0, // zsub2 |
| 24193 | 0, // zsub3 |
| 24194 | 0, // zsub_hi |
| 24195 | 89, // dsub1_then_bsub -> DD_with_dsub1_in_FPR64_lo |
| 24196 | 89, // dsub1_then_hsub -> DD_with_dsub1_in_FPR64_lo |
| 24197 | 89, // dsub1_then_ssub -> DD_with_dsub1_in_FPR64_lo |
| 24198 | 0, // dsub3_then_bsub |
| 24199 | 0, // dsub3_then_hsub |
| 24200 | 0, // dsub3_then_ssub |
| 24201 | 0, // dsub2_then_bsub |
| 24202 | 0, // dsub2_then_hsub |
| 24203 | 0, // dsub2_then_ssub |
| 24204 | 0, // qsub1_then_bsub |
| 24205 | 0, // qsub1_then_dsub |
| 24206 | 0, // qsub1_then_hsub |
| 24207 | 0, // qsub1_then_ssub |
| 24208 | 0, // qsub3_then_bsub |
| 24209 | 0, // qsub3_then_dsub |
| 24210 | 0, // qsub3_then_hsub |
| 24211 | 0, // qsub3_then_ssub |
| 24212 | 0, // qsub2_then_bsub |
| 24213 | 0, // qsub2_then_dsub |
| 24214 | 0, // qsub2_then_hsub |
| 24215 | 0, // qsub2_then_ssub |
| 24216 | 0, // x8sub_7_then_sub_32 |
| 24217 | 0, // x8sub_6_then_sub_32 |
| 24218 | 0, // x8sub_5_then_sub_32 |
| 24219 | 0, // x8sub_4_then_sub_32 |
| 24220 | 0, // x8sub_3_then_sub_32 |
| 24221 | 0, // x8sub_2_then_sub_32 |
| 24222 | 0, // x8sub_1_then_sub_32 |
| 24223 | 0, // subo64_then_sub_32 |
| 24224 | 0, // zsub1_then_bsub |
| 24225 | 0, // zsub1_then_dsub |
| 24226 | 0, // zsub1_then_hsub |
| 24227 | 0, // zsub1_then_ssub |
| 24228 | 0, // zsub1_then_zsub |
| 24229 | 0, // zsub1_then_zsub_hi |
| 24230 | 0, // zsub3_then_bsub |
| 24231 | 0, // zsub3_then_dsub |
| 24232 | 0, // zsub3_then_hsub |
| 24233 | 0, // zsub3_then_ssub |
| 24234 | 0, // zsub3_then_zsub |
| 24235 | 0, // zsub3_then_zsub_hi |
| 24236 | 0, // zsub2_then_bsub |
| 24237 | 0, // zsub2_then_dsub |
| 24238 | 0, // zsub2_then_hsub |
| 24239 | 0, // zsub2_then_ssub |
| 24240 | 0, // zsub2_then_zsub |
| 24241 | 0, // zsub2_then_zsub_hi |
| 24242 | 0, // dsub0_dsub1 |
| 24243 | 0, // dsub0_dsub1_dsub2 |
| 24244 | 0, // dsub1_dsub2 |
| 24245 | 0, // dsub1_dsub2_dsub3 |
| 24246 | 0, // dsub2_dsub3 |
| 24247 | 0, // dsub_qsub1_then_dsub |
| 24248 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24249 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24250 | 0, // qsub0_qsub1 |
| 24251 | 0, // qsub0_qsub1_qsub2 |
| 24252 | 0, // qsub1_qsub2 |
| 24253 | 0, // qsub1_qsub2_qsub3 |
| 24254 | 0, // qsub2_qsub3 |
| 24255 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24256 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24257 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24258 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24259 | 0, // x8sub_0_x8sub_1 |
| 24260 | 0, // x8sub_2_x8sub_3 |
| 24261 | 0, // x8sub_4_x8sub_5 |
| 24262 | 0, // x8sub_6_x8sub_7 |
| 24263 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24264 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24265 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24266 | 0, // sub_32_subo64_then_sub_32 |
| 24267 | 0, // dsub_zsub1_then_dsub |
| 24268 | 0, // zsub_zsub1_then_zsub |
| 24269 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24270 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24271 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24272 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24273 | 0, // zsub0_zsub1 |
| 24274 | 0, // zsub0_zsub1_zsub2 |
| 24275 | 0, // zsub1_zsub2 |
| 24276 | 0, // zsub1_zsub2_zsub3 |
| 24277 | 0, // zsub2_zsub3 |
| 24278 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24279 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24280 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24281 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24282 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24283 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24284 | }, |
| 24285 | { // XSeqPairsClass |
| 24286 | 0, // bsub |
| 24287 | 0, // dsub |
| 24288 | 0, // dsub0 |
| 24289 | 0, // dsub1 |
| 24290 | 0, // dsub2 |
| 24291 | 0, // dsub3 |
| 24292 | 0, // hsub |
| 24293 | 0, // qhisub |
| 24294 | 0, // qsub |
| 24295 | 0, // qsub0 |
| 24296 | 0, // qsub1 |
| 24297 | 0, // qsub2 |
| 24298 | 0, // qsub3 |
| 24299 | 0, // ssub |
| 24300 | 90, // sub_32 -> XSeqPairsClass |
| 24301 | 0, // sube32 |
| 24302 | 90, // sube64 -> XSeqPairsClass |
| 24303 | 0, // subo32 |
| 24304 | 90, // subo64 -> XSeqPairsClass |
| 24305 | 0, // x8sub_0 |
| 24306 | 0, // x8sub_1 |
| 24307 | 0, // x8sub_2 |
| 24308 | 0, // x8sub_3 |
| 24309 | 0, // x8sub_4 |
| 24310 | 0, // x8sub_5 |
| 24311 | 0, // x8sub_6 |
| 24312 | 0, // x8sub_7 |
| 24313 | 0, // zsub |
| 24314 | 0, // zsub0 |
| 24315 | 0, // zsub1 |
| 24316 | 0, // zsub2 |
| 24317 | 0, // zsub3 |
| 24318 | 0, // zsub_hi |
| 24319 | 0, // dsub1_then_bsub |
| 24320 | 0, // dsub1_then_hsub |
| 24321 | 0, // dsub1_then_ssub |
| 24322 | 0, // dsub3_then_bsub |
| 24323 | 0, // dsub3_then_hsub |
| 24324 | 0, // dsub3_then_ssub |
| 24325 | 0, // dsub2_then_bsub |
| 24326 | 0, // dsub2_then_hsub |
| 24327 | 0, // dsub2_then_ssub |
| 24328 | 0, // qsub1_then_bsub |
| 24329 | 0, // qsub1_then_dsub |
| 24330 | 0, // qsub1_then_hsub |
| 24331 | 0, // qsub1_then_ssub |
| 24332 | 0, // qsub3_then_bsub |
| 24333 | 0, // qsub3_then_dsub |
| 24334 | 0, // qsub3_then_hsub |
| 24335 | 0, // qsub3_then_ssub |
| 24336 | 0, // qsub2_then_bsub |
| 24337 | 0, // qsub2_then_dsub |
| 24338 | 0, // qsub2_then_hsub |
| 24339 | 0, // qsub2_then_ssub |
| 24340 | 0, // x8sub_7_then_sub_32 |
| 24341 | 0, // x8sub_6_then_sub_32 |
| 24342 | 0, // x8sub_5_then_sub_32 |
| 24343 | 0, // x8sub_4_then_sub_32 |
| 24344 | 0, // x8sub_3_then_sub_32 |
| 24345 | 0, // x8sub_2_then_sub_32 |
| 24346 | 0, // x8sub_1_then_sub_32 |
| 24347 | 90, // subo64_then_sub_32 -> XSeqPairsClass |
| 24348 | 0, // zsub1_then_bsub |
| 24349 | 0, // zsub1_then_dsub |
| 24350 | 0, // zsub1_then_hsub |
| 24351 | 0, // zsub1_then_ssub |
| 24352 | 0, // zsub1_then_zsub |
| 24353 | 0, // zsub1_then_zsub_hi |
| 24354 | 0, // zsub3_then_bsub |
| 24355 | 0, // zsub3_then_dsub |
| 24356 | 0, // zsub3_then_hsub |
| 24357 | 0, // zsub3_then_ssub |
| 24358 | 0, // zsub3_then_zsub |
| 24359 | 0, // zsub3_then_zsub_hi |
| 24360 | 0, // zsub2_then_bsub |
| 24361 | 0, // zsub2_then_dsub |
| 24362 | 0, // zsub2_then_hsub |
| 24363 | 0, // zsub2_then_ssub |
| 24364 | 0, // zsub2_then_zsub |
| 24365 | 0, // zsub2_then_zsub_hi |
| 24366 | 0, // dsub0_dsub1 |
| 24367 | 0, // dsub0_dsub1_dsub2 |
| 24368 | 0, // dsub1_dsub2 |
| 24369 | 0, // dsub1_dsub2_dsub3 |
| 24370 | 0, // dsub2_dsub3 |
| 24371 | 0, // dsub_qsub1_then_dsub |
| 24372 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24373 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24374 | 0, // qsub0_qsub1 |
| 24375 | 0, // qsub0_qsub1_qsub2 |
| 24376 | 0, // qsub1_qsub2 |
| 24377 | 0, // qsub1_qsub2_qsub3 |
| 24378 | 0, // qsub2_qsub3 |
| 24379 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24380 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24381 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24382 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24383 | 0, // x8sub_0_x8sub_1 |
| 24384 | 0, // x8sub_2_x8sub_3 |
| 24385 | 0, // x8sub_4_x8sub_5 |
| 24386 | 0, // x8sub_6_x8sub_7 |
| 24387 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24388 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24389 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24390 | 90, // sub_32_subo64_then_sub_32 -> XSeqPairsClass |
| 24391 | 0, // dsub_zsub1_then_dsub |
| 24392 | 0, // zsub_zsub1_then_zsub |
| 24393 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24394 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24395 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24396 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24397 | 0, // zsub0_zsub1 |
| 24398 | 0, // zsub0_zsub1_zsub2 |
| 24399 | 0, // zsub1_zsub2 |
| 24400 | 0, // zsub1_zsub2_zsub3 |
| 24401 | 0, // zsub2_zsub3 |
| 24402 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24403 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24404 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24405 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24406 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24407 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24408 | }, |
| 24409 | { // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24410 | 91, // bsub -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24411 | 0, // dsub |
| 24412 | 91, // dsub0 -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24413 | 91, // dsub1 -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24414 | 0, // dsub2 |
| 24415 | 0, // dsub3 |
| 24416 | 91, // hsub -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24417 | 0, // qhisub |
| 24418 | 0, // qsub |
| 24419 | 0, // qsub0 |
| 24420 | 0, // qsub1 |
| 24421 | 0, // qsub2 |
| 24422 | 0, // qsub3 |
| 24423 | 91, // ssub -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24424 | 0, // sub_32 |
| 24425 | 0, // sube32 |
| 24426 | 0, // sube64 |
| 24427 | 0, // subo32 |
| 24428 | 0, // subo64 |
| 24429 | 0, // x8sub_0 |
| 24430 | 0, // x8sub_1 |
| 24431 | 0, // x8sub_2 |
| 24432 | 0, // x8sub_3 |
| 24433 | 0, // x8sub_4 |
| 24434 | 0, // x8sub_5 |
| 24435 | 0, // x8sub_6 |
| 24436 | 0, // x8sub_7 |
| 24437 | 0, // zsub |
| 24438 | 0, // zsub0 |
| 24439 | 0, // zsub1 |
| 24440 | 0, // zsub2 |
| 24441 | 0, // zsub3 |
| 24442 | 0, // zsub_hi |
| 24443 | 91, // dsub1_then_bsub -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24444 | 91, // dsub1_then_hsub -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24445 | 91, // dsub1_then_ssub -> DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 24446 | 0, // dsub3_then_bsub |
| 24447 | 0, // dsub3_then_hsub |
| 24448 | 0, // dsub3_then_ssub |
| 24449 | 0, // dsub2_then_bsub |
| 24450 | 0, // dsub2_then_hsub |
| 24451 | 0, // dsub2_then_ssub |
| 24452 | 0, // qsub1_then_bsub |
| 24453 | 0, // qsub1_then_dsub |
| 24454 | 0, // qsub1_then_hsub |
| 24455 | 0, // qsub1_then_ssub |
| 24456 | 0, // qsub3_then_bsub |
| 24457 | 0, // qsub3_then_dsub |
| 24458 | 0, // qsub3_then_hsub |
| 24459 | 0, // qsub3_then_ssub |
| 24460 | 0, // qsub2_then_bsub |
| 24461 | 0, // qsub2_then_dsub |
| 24462 | 0, // qsub2_then_hsub |
| 24463 | 0, // qsub2_then_ssub |
| 24464 | 0, // x8sub_7_then_sub_32 |
| 24465 | 0, // x8sub_6_then_sub_32 |
| 24466 | 0, // x8sub_5_then_sub_32 |
| 24467 | 0, // x8sub_4_then_sub_32 |
| 24468 | 0, // x8sub_3_then_sub_32 |
| 24469 | 0, // x8sub_2_then_sub_32 |
| 24470 | 0, // x8sub_1_then_sub_32 |
| 24471 | 0, // subo64_then_sub_32 |
| 24472 | 0, // zsub1_then_bsub |
| 24473 | 0, // zsub1_then_dsub |
| 24474 | 0, // zsub1_then_hsub |
| 24475 | 0, // zsub1_then_ssub |
| 24476 | 0, // zsub1_then_zsub |
| 24477 | 0, // zsub1_then_zsub_hi |
| 24478 | 0, // zsub3_then_bsub |
| 24479 | 0, // zsub3_then_dsub |
| 24480 | 0, // zsub3_then_hsub |
| 24481 | 0, // zsub3_then_ssub |
| 24482 | 0, // zsub3_then_zsub |
| 24483 | 0, // zsub3_then_zsub_hi |
| 24484 | 0, // zsub2_then_bsub |
| 24485 | 0, // zsub2_then_dsub |
| 24486 | 0, // zsub2_then_hsub |
| 24487 | 0, // zsub2_then_ssub |
| 24488 | 0, // zsub2_then_zsub |
| 24489 | 0, // zsub2_then_zsub_hi |
| 24490 | 0, // dsub0_dsub1 |
| 24491 | 0, // dsub0_dsub1_dsub2 |
| 24492 | 0, // dsub1_dsub2 |
| 24493 | 0, // dsub1_dsub2_dsub3 |
| 24494 | 0, // dsub2_dsub3 |
| 24495 | 0, // dsub_qsub1_then_dsub |
| 24496 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24497 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24498 | 0, // qsub0_qsub1 |
| 24499 | 0, // qsub0_qsub1_qsub2 |
| 24500 | 0, // qsub1_qsub2 |
| 24501 | 0, // qsub1_qsub2_qsub3 |
| 24502 | 0, // qsub2_qsub3 |
| 24503 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24504 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24505 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24506 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24507 | 0, // x8sub_0_x8sub_1 |
| 24508 | 0, // x8sub_2_x8sub_3 |
| 24509 | 0, // x8sub_4_x8sub_5 |
| 24510 | 0, // x8sub_6_x8sub_7 |
| 24511 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24512 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24513 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24514 | 0, // sub_32_subo64_then_sub_32 |
| 24515 | 0, // dsub_zsub1_then_dsub |
| 24516 | 0, // zsub_zsub1_then_zsub |
| 24517 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24518 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24519 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24520 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24521 | 0, // zsub0_zsub1 |
| 24522 | 0, // zsub0_zsub1_zsub2 |
| 24523 | 0, // zsub1_zsub2 |
| 24524 | 0, // zsub1_zsub2_zsub3 |
| 24525 | 0, // zsub2_zsub3 |
| 24526 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24527 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24528 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24529 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24530 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24531 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24532 | }, |
| 24533 | { // XSeqPairsClass_with_subo64_in_GPR64common |
| 24534 | 0, // bsub |
| 24535 | 0, // dsub |
| 24536 | 0, // dsub0 |
| 24537 | 0, // dsub1 |
| 24538 | 0, // dsub2 |
| 24539 | 0, // dsub3 |
| 24540 | 0, // hsub |
| 24541 | 0, // qhisub |
| 24542 | 0, // qsub |
| 24543 | 0, // qsub0 |
| 24544 | 0, // qsub1 |
| 24545 | 0, // qsub2 |
| 24546 | 0, // qsub3 |
| 24547 | 0, // ssub |
| 24548 | 92, // sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common |
| 24549 | 0, // sube32 |
| 24550 | 92, // sube64 -> XSeqPairsClass_with_subo64_in_GPR64common |
| 24551 | 0, // subo32 |
| 24552 | 92, // subo64 -> XSeqPairsClass_with_subo64_in_GPR64common |
| 24553 | 0, // x8sub_0 |
| 24554 | 0, // x8sub_1 |
| 24555 | 0, // x8sub_2 |
| 24556 | 0, // x8sub_3 |
| 24557 | 0, // x8sub_4 |
| 24558 | 0, // x8sub_5 |
| 24559 | 0, // x8sub_6 |
| 24560 | 0, // x8sub_7 |
| 24561 | 0, // zsub |
| 24562 | 0, // zsub0 |
| 24563 | 0, // zsub1 |
| 24564 | 0, // zsub2 |
| 24565 | 0, // zsub3 |
| 24566 | 0, // zsub_hi |
| 24567 | 0, // dsub1_then_bsub |
| 24568 | 0, // dsub1_then_hsub |
| 24569 | 0, // dsub1_then_ssub |
| 24570 | 0, // dsub3_then_bsub |
| 24571 | 0, // dsub3_then_hsub |
| 24572 | 0, // dsub3_then_ssub |
| 24573 | 0, // dsub2_then_bsub |
| 24574 | 0, // dsub2_then_hsub |
| 24575 | 0, // dsub2_then_ssub |
| 24576 | 0, // qsub1_then_bsub |
| 24577 | 0, // qsub1_then_dsub |
| 24578 | 0, // qsub1_then_hsub |
| 24579 | 0, // qsub1_then_ssub |
| 24580 | 0, // qsub3_then_bsub |
| 24581 | 0, // qsub3_then_dsub |
| 24582 | 0, // qsub3_then_hsub |
| 24583 | 0, // qsub3_then_ssub |
| 24584 | 0, // qsub2_then_bsub |
| 24585 | 0, // qsub2_then_dsub |
| 24586 | 0, // qsub2_then_hsub |
| 24587 | 0, // qsub2_then_ssub |
| 24588 | 0, // x8sub_7_then_sub_32 |
| 24589 | 0, // x8sub_6_then_sub_32 |
| 24590 | 0, // x8sub_5_then_sub_32 |
| 24591 | 0, // x8sub_4_then_sub_32 |
| 24592 | 0, // x8sub_3_then_sub_32 |
| 24593 | 0, // x8sub_2_then_sub_32 |
| 24594 | 0, // x8sub_1_then_sub_32 |
| 24595 | 92, // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common |
| 24596 | 0, // zsub1_then_bsub |
| 24597 | 0, // zsub1_then_dsub |
| 24598 | 0, // zsub1_then_hsub |
| 24599 | 0, // zsub1_then_ssub |
| 24600 | 0, // zsub1_then_zsub |
| 24601 | 0, // zsub1_then_zsub_hi |
| 24602 | 0, // zsub3_then_bsub |
| 24603 | 0, // zsub3_then_dsub |
| 24604 | 0, // zsub3_then_hsub |
| 24605 | 0, // zsub3_then_ssub |
| 24606 | 0, // zsub3_then_zsub |
| 24607 | 0, // zsub3_then_zsub_hi |
| 24608 | 0, // zsub2_then_bsub |
| 24609 | 0, // zsub2_then_dsub |
| 24610 | 0, // zsub2_then_hsub |
| 24611 | 0, // zsub2_then_ssub |
| 24612 | 0, // zsub2_then_zsub |
| 24613 | 0, // zsub2_then_zsub_hi |
| 24614 | 0, // dsub0_dsub1 |
| 24615 | 0, // dsub0_dsub1_dsub2 |
| 24616 | 0, // dsub1_dsub2 |
| 24617 | 0, // dsub1_dsub2_dsub3 |
| 24618 | 0, // dsub2_dsub3 |
| 24619 | 0, // dsub_qsub1_then_dsub |
| 24620 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24621 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24622 | 0, // qsub0_qsub1 |
| 24623 | 0, // qsub0_qsub1_qsub2 |
| 24624 | 0, // qsub1_qsub2 |
| 24625 | 0, // qsub1_qsub2_qsub3 |
| 24626 | 0, // qsub2_qsub3 |
| 24627 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24628 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24629 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24630 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24631 | 0, // x8sub_0_x8sub_1 |
| 24632 | 0, // x8sub_2_x8sub_3 |
| 24633 | 0, // x8sub_4_x8sub_5 |
| 24634 | 0, // x8sub_6_x8sub_7 |
| 24635 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24636 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24637 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24638 | 92, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64common |
| 24639 | 0, // dsub_zsub1_then_dsub |
| 24640 | 0, // zsub_zsub1_then_zsub |
| 24641 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24642 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24643 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24644 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24645 | 0, // zsub0_zsub1 |
| 24646 | 0, // zsub0_zsub1_zsub2 |
| 24647 | 0, // zsub1_zsub2 |
| 24648 | 0, // zsub1_zsub2_zsub3 |
| 24649 | 0, // zsub2_zsub3 |
| 24650 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24651 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24652 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24653 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24654 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24655 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24656 | }, |
| 24657 | { // XSeqPairsClass_with_subo64_in_GPR64noip |
| 24658 | 0, // bsub |
| 24659 | 0, // dsub |
| 24660 | 0, // dsub0 |
| 24661 | 0, // dsub1 |
| 24662 | 0, // dsub2 |
| 24663 | 0, // dsub3 |
| 24664 | 0, // hsub |
| 24665 | 0, // qhisub |
| 24666 | 0, // qsub |
| 24667 | 0, // qsub0 |
| 24668 | 0, // qsub1 |
| 24669 | 0, // qsub2 |
| 24670 | 0, // qsub3 |
| 24671 | 0, // ssub |
| 24672 | 93, // sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip |
| 24673 | 0, // sube32 |
| 24674 | 93, // sube64 -> XSeqPairsClass_with_subo64_in_GPR64noip |
| 24675 | 0, // subo32 |
| 24676 | 93, // subo64 -> XSeqPairsClass_with_subo64_in_GPR64noip |
| 24677 | 0, // x8sub_0 |
| 24678 | 0, // x8sub_1 |
| 24679 | 0, // x8sub_2 |
| 24680 | 0, // x8sub_3 |
| 24681 | 0, // x8sub_4 |
| 24682 | 0, // x8sub_5 |
| 24683 | 0, // x8sub_6 |
| 24684 | 0, // x8sub_7 |
| 24685 | 0, // zsub |
| 24686 | 0, // zsub0 |
| 24687 | 0, // zsub1 |
| 24688 | 0, // zsub2 |
| 24689 | 0, // zsub3 |
| 24690 | 0, // zsub_hi |
| 24691 | 0, // dsub1_then_bsub |
| 24692 | 0, // dsub1_then_hsub |
| 24693 | 0, // dsub1_then_ssub |
| 24694 | 0, // dsub3_then_bsub |
| 24695 | 0, // dsub3_then_hsub |
| 24696 | 0, // dsub3_then_ssub |
| 24697 | 0, // dsub2_then_bsub |
| 24698 | 0, // dsub2_then_hsub |
| 24699 | 0, // dsub2_then_ssub |
| 24700 | 0, // qsub1_then_bsub |
| 24701 | 0, // qsub1_then_dsub |
| 24702 | 0, // qsub1_then_hsub |
| 24703 | 0, // qsub1_then_ssub |
| 24704 | 0, // qsub3_then_bsub |
| 24705 | 0, // qsub3_then_dsub |
| 24706 | 0, // qsub3_then_hsub |
| 24707 | 0, // qsub3_then_ssub |
| 24708 | 0, // qsub2_then_bsub |
| 24709 | 0, // qsub2_then_dsub |
| 24710 | 0, // qsub2_then_hsub |
| 24711 | 0, // qsub2_then_ssub |
| 24712 | 0, // x8sub_7_then_sub_32 |
| 24713 | 0, // x8sub_6_then_sub_32 |
| 24714 | 0, // x8sub_5_then_sub_32 |
| 24715 | 0, // x8sub_4_then_sub_32 |
| 24716 | 0, // x8sub_3_then_sub_32 |
| 24717 | 0, // x8sub_2_then_sub_32 |
| 24718 | 0, // x8sub_1_then_sub_32 |
| 24719 | 93, // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip |
| 24720 | 0, // zsub1_then_bsub |
| 24721 | 0, // zsub1_then_dsub |
| 24722 | 0, // zsub1_then_hsub |
| 24723 | 0, // zsub1_then_ssub |
| 24724 | 0, // zsub1_then_zsub |
| 24725 | 0, // zsub1_then_zsub_hi |
| 24726 | 0, // zsub3_then_bsub |
| 24727 | 0, // zsub3_then_dsub |
| 24728 | 0, // zsub3_then_hsub |
| 24729 | 0, // zsub3_then_ssub |
| 24730 | 0, // zsub3_then_zsub |
| 24731 | 0, // zsub3_then_zsub_hi |
| 24732 | 0, // zsub2_then_bsub |
| 24733 | 0, // zsub2_then_dsub |
| 24734 | 0, // zsub2_then_hsub |
| 24735 | 0, // zsub2_then_ssub |
| 24736 | 0, // zsub2_then_zsub |
| 24737 | 0, // zsub2_then_zsub_hi |
| 24738 | 0, // dsub0_dsub1 |
| 24739 | 0, // dsub0_dsub1_dsub2 |
| 24740 | 0, // dsub1_dsub2 |
| 24741 | 0, // dsub1_dsub2_dsub3 |
| 24742 | 0, // dsub2_dsub3 |
| 24743 | 0, // dsub_qsub1_then_dsub |
| 24744 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24745 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24746 | 0, // qsub0_qsub1 |
| 24747 | 0, // qsub0_qsub1_qsub2 |
| 24748 | 0, // qsub1_qsub2 |
| 24749 | 0, // qsub1_qsub2_qsub3 |
| 24750 | 0, // qsub2_qsub3 |
| 24751 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24752 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24753 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24754 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24755 | 0, // x8sub_0_x8sub_1 |
| 24756 | 0, // x8sub_2_x8sub_3 |
| 24757 | 0, // x8sub_4_x8sub_5 |
| 24758 | 0, // x8sub_6_x8sub_7 |
| 24759 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24760 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24761 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24762 | 93, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip |
| 24763 | 0, // dsub_zsub1_then_dsub |
| 24764 | 0, // zsub_zsub1_then_zsub |
| 24765 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24766 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24767 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24768 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24769 | 0, // zsub0_zsub1 |
| 24770 | 0, // zsub0_zsub1_zsub2 |
| 24771 | 0, // zsub1_zsub2 |
| 24772 | 0, // zsub1_zsub2_zsub3 |
| 24773 | 0, // zsub2_zsub3 |
| 24774 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24775 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24776 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24777 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24778 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24779 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24780 | }, |
| 24781 | { // XSeqPairsClass_with_sube64_in_GPR64noip |
| 24782 | 0, // bsub |
| 24783 | 0, // dsub |
| 24784 | 0, // dsub0 |
| 24785 | 0, // dsub1 |
| 24786 | 0, // dsub2 |
| 24787 | 0, // dsub3 |
| 24788 | 0, // hsub |
| 24789 | 0, // qhisub |
| 24790 | 0, // qsub |
| 24791 | 0, // qsub0 |
| 24792 | 0, // qsub1 |
| 24793 | 0, // qsub2 |
| 24794 | 0, // qsub3 |
| 24795 | 0, // ssub |
| 24796 | 94, // sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip |
| 24797 | 0, // sube32 |
| 24798 | 94, // sube64 -> XSeqPairsClass_with_sube64_in_GPR64noip |
| 24799 | 0, // subo32 |
| 24800 | 94, // subo64 -> XSeqPairsClass_with_sube64_in_GPR64noip |
| 24801 | 0, // x8sub_0 |
| 24802 | 0, // x8sub_1 |
| 24803 | 0, // x8sub_2 |
| 24804 | 0, // x8sub_3 |
| 24805 | 0, // x8sub_4 |
| 24806 | 0, // x8sub_5 |
| 24807 | 0, // x8sub_6 |
| 24808 | 0, // x8sub_7 |
| 24809 | 0, // zsub |
| 24810 | 0, // zsub0 |
| 24811 | 0, // zsub1 |
| 24812 | 0, // zsub2 |
| 24813 | 0, // zsub3 |
| 24814 | 0, // zsub_hi |
| 24815 | 0, // dsub1_then_bsub |
| 24816 | 0, // dsub1_then_hsub |
| 24817 | 0, // dsub1_then_ssub |
| 24818 | 0, // dsub3_then_bsub |
| 24819 | 0, // dsub3_then_hsub |
| 24820 | 0, // dsub3_then_ssub |
| 24821 | 0, // dsub2_then_bsub |
| 24822 | 0, // dsub2_then_hsub |
| 24823 | 0, // dsub2_then_ssub |
| 24824 | 0, // qsub1_then_bsub |
| 24825 | 0, // qsub1_then_dsub |
| 24826 | 0, // qsub1_then_hsub |
| 24827 | 0, // qsub1_then_ssub |
| 24828 | 0, // qsub3_then_bsub |
| 24829 | 0, // qsub3_then_dsub |
| 24830 | 0, // qsub3_then_hsub |
| 24831 | 0, // qsub3_then_ssub |
| 24832 | 0, // qsub2_then_bsub |
| 24833 | 0, // qsub2_then_dsub |
| 24834 | 0, // qsub2_then_hsub |
| 24835 | 0, // qsub2_then_ssub |
| 24836 | 0, // x8sub_7_then_sub_32 |
| 24837 | 0, // x8sub_6_then_sub_32 |
| 24838 | 0, // x8sub_5_then_sub_32 |
| 24839 | 0, // x8sub_4_then_sub_32 |
| 24840 | 0, // x8sub_3_then_sub_32 |
| 24841 | 0, // x8sub_2_then_sub_32 |
| 24842 | 0, // x8sub_1_then_sub_32 |
| 24843 | 94, // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip |
| 24844 | 0, // zsub1_then_bsub |
| 24845 | 0, // zsub1_then_dsub |
| 24846 | 0, // zsub1_then_hsub |
| 24847 | 0, // zsub1_then_ssub |
| 24848 | 0, // zsub1_then_zsub |
| 24849 | 0, // zsub1_then_zsub_hi |
| 24850 | 0, // zsub3_then_bsub |
| 24851 | 0, // zsub3_then_dsub |
| 24852 | 0, // zsub3_then_hsub |
| 24853 | 0, // zsub3_then_ssub |
| 24854 | 0, // zsub3_then_zsub |
| 24855 | 0, // zsub3_then_zsub_hi |
| 24856 | 0, // zsub2_then_bsub |
| 24857 | 0, // zsub2_then_dsub |
| 24858 | 0, // zsub2_then_hsub |
| 24859 | 0, // zsub2_then_ssub |
| 24860 | 0, // zsub2_then_zsub |
| 24861 | 0, // zsub2_then_zsub_hi |
| 24862 | 0, // dsub0_dsub1 |
| 24863 | 0, // dsub0_dsub1_dsub2 |
| 24864 | 0, // dsub1_dsub2 |
| 24865 | 0, // dsub1_dsub2_dsub3 |
| 24866 | 0, // dsub2_dsub3 |
| 24867 | 0, // dsub_qsub1_then_dsub |
| 24868 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24869 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24870 | 0, // qsub0_qsub1 |
| 24871 | 0, // qsub0_qsub1_qsub2 |
| 24872 | 0, // qsub1_qsub2 |
| 24873 | 0, // qsub1_qsub2_qsub3 |
| 24874 | 0, // qsub2_qsub3 |
| 24875 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 24876 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24877 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 24878 | 0, // sub_32_x8sub_1_then_sub_32 |
| 24879 | 0, // x8sub_0_x8sub_1 |
| 24880 | 0, // x8sub_2_x8sub_3 |
| 24881 | 0, // x8sub_4_x8sub_5 |
| 24882 | 0, // x8sub_6_x8sub_7 |
| 24883 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 24884 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 24885 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 24886 | 94, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip |
| 24887 | 0, // dsub_zsub1_then_dsub |
| 24888 | 0, // zsub_zsub1_then_zsub |
| 24889 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24890 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 24891 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24892 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 24893 | 0, // zsub0_zsub1 |
| 24894 | 0, // zsub0_zsub1_zsub2 |
| 24895 | 0, // zsub1_zsub2 |
| 24896 | 0, // zsub1_zsub2_zsub3 |
| 24897 | 0, // zsub2_zsub3 |
| 24898 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 24899 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 24900 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 24901 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 24902 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 24903 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 24904 | }, |
| 24905 | { // XSeqPairsClass_with_sube64_in_tcGPR64 |
| 24906 | 0, // bsub |
| 24907 | 0, // dsub |
| 24908 | 0, // dsub0 |
| 24909 | 0, // dsub1 |
| 24910 | 0, // dsub2 |
| 24911 | 0, // dsub3 |
| 24912 | 0, // hsub |
| 24913 | 0, // qhisub |
| 24914 | 0, // qsub |
| 24915 | 0, // qsub0 |
| 24916 | 0, // qsub1 |
| 24917 | 0, // qsub2 |
| 24918 | 0, // qsub3 |
| 24919 | 0, // ssub |
| 24920 | 95, // sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64 |
| 24921 | 0, // sube32 |
| 24922 | 95, // sube64 -> XSeqPairsClass_with_sube64_in_tcGPR64 |
| 24923 | 0, // subo32 |
| 24924 | 95, // subo64 -> XSeqPairsClass_with_sube64_in_tcGPR64 |
| 24925 | 0, // x8sub_0 |
| 24926 | 0, // x8sub_1 |
| 24927 | 0, // x8sub_2 |
| 24928 | 0, // x8sub_3 |
| 24929 | 0, // x8sub_4 |
| 24930 | 0, // x8sub_5 |
| 24931 | 0, // x8sub_6 |
| 24932 | 0, // x8sub_7 |
| 24933 | 0, // zsub |
| 24934 | 0, // zsub0 |
| 24935 | 0, // zsub1 |
| 24936 | 0, // zsub2 |
| 24937 | 0, // zsub3 |
| 24938 | 0, // zsub_hi |
| 24939 | 0, // dsub1_then_bsub |
| 24940 | 0, // dsub1_then_hsub |
| 24941 | 0, // dsub1_then_ssub |
| 24942 | 0, // dsub3_then_bsub |
| 24943 | 0, // dsub3_then_hsub |
| 24944 | 0, // dsub3_then_ssub |
| 24945 | 0, // dsub2_then_bsub |
| 24946 | 0, // dsub2_then_hsub |
| 24947 | 0, // dsub2_then_ssub |
| 24948 | 0, // qsub1_then_bsub |
| 24949 | 0, // qsub1_then_dsub |
| 24950 | 0, // qsub1_then_hsub |
| 24951 | 0, // qsub1_then_ssub |
| 24952 | 0, // qsub3_then_bsub |
| 24953 | 0, // qsub3_then_dsub |
| 24954 | 0, // qsub3_then_hsub |
| 24955 | 0, // qsub3_then_ssub |
| 24956 | 0, // qsub2_then_bsub |
| 24957 | 0, // qsub2_then_dsub |
| 24958 | 0, // qsub2_then_hsub |
| 24959 | 0, // qsub2_then_ssub |
| 24960 | 0, // x8sub_7_then_sub_32 |
| 24961 | 0, // x8sub_6_then_sub_32 |
| 24962 | 0, // x8sub_5_then_sub_32 |
| 24963 | 0, // x8sub_4_then_sub_32 |
| 24964 | 0, // x8sub_3_then_sub_32 |
| 24965 | 0, // x8sub_2_then_sub_32 |
| 24966 | 0, // x8sub_1_then_sub_32 |
| 24967 | 95, // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64 |
| 24968 | 0, // zsub1_then_bsub |
| 24969 | 0, // zsub1_then_dsub |
| 24970 | 0, // zsub1_then_hsub |
| 24971 | 0, // zsub1_then_ssub |
| 24972 | 0, // zsub1_then_zsub |
| 24973 | 0, // zsub1_then_zsub_hi |
| 24974 | 0, // zsub3_then_bsub |
| 24975 | 0, // zsub3_then_dsub |
| 24976 | 0, // zsub3_then_hsub |
| 24977 | 0, // zsub3_then_ssub |
| 24978 | 0, // zsub3_then_zsub |
| 24979 | 0, // zsub3_then_zsub_hi |
| 24980 | 0, // zsub2_then_bsub |
| 24981 | 0, // zsub2_then_dsub |
| 24982 | 0, // zsub2_then_hsub |
| 24983 | 0, // zsub2_then_ssub |
| 24984 | 0, // zsub2_then_zsub |
| 24985 | 0, // zsub2_then_zsub_hi |
| 24986 | 0, // dsub0_dsub1 |
| 24987 | 0, // dsub0_dsub1_dsub2 |
| 24988 | 0, // dsub1_dsub2 |
| 24989 | 0, // dsub1_dsub2_dsub3 |
| 24990 | 0, // dsub2_dsub3 |
| 24991 | 0, // dsub_qsub1_then_dsub |
| 24992 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 24993 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 24994 | 0, // qsub0_qsub1 |
| 24995 | 0, // qsub0_qsub1_qsub2 |
| 24996 | 0, // qsub1_qsub2 |
| 24997 | 0, // qsub1_qsub2_qsub3 |
| 24998 | 0, // qsub2_qsub3 |
| 24999 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25000 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25001 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25002 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25003 | 0, // x8sub_0_x8sub_1 |
| 25004 | 0, // x8sub_2_x8sub_3 |
| 25005 | 0, // x8sub_4_x8sub_5 |
| 25006 | 0, // x8sub_6_x8sub_7 |
| 25007 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25008 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25009 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25010 | 95, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_tcGPR64 |
| 25011 | 0, // dsub_zsub1_then_dsub |
| 25012 | 0, // zsub_zsub1_then_zsub |
| 25013 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25014 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25015 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25016 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25017 | 0, // zsub0_zsub1 |
| 25018 | 0, // zsub0_zsub1_zsub2 |
| 25019 | 0, // zsub1_zsub2 |
| 25020 | 0, // zsub1_zsub2_zsub3 |
| 25021 | 0, // zsub2_zsub3 |
| 25022 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25023 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25024 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25025 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25026 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25027 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25028 | }, |
| 25029 | { // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 25030 | 0, // bsub |
| 25031 | 0, // dsub |
| 25032 | 0, // dsub0 |
| 25033 | 0, // dsub1 |
| 25034 | 0, // dsub2 |
| 25035 | 0, // dsub3 |
| 25036 | 0, // hsub |
| 25037 | 0, // qhisub |
| 25038 | 0, // qsub |
| 25039 | 0, // qsub0 |
| 25040 | 0, // qsub1 |
| 25041 | 0, // qsub2 |
| 25042 | 0, // qsub3 |
| 25043 | 0, // ssub |
| 25044 | 96, // sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 25045 | 0, // sube32 |
| 25046 | 96, // sube64 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 25047 | 0, // subo32 |
| 25048 | 96, // subo64 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 25049 | 0, // x8sub_0 |
| 25050 | 0, // x8sub_1 |
| 25051 | 0, // x8sub_2 |
| 25052 | 0, // x8sub_3 |
| 25053 | 0, // x8sub_4 |
| 25054 | 0, // x8sub_5 |
| 25055 | 0, // x8sub_6 |
| 25056 | 0, // x8sub_7 |
| 25057 | 0, // zsub |
| 25058 | 0, // zsub0 |
| 25059 | 0, // zsub1 |
| 25060 | 0, // zsub2 |
| 25061 | 0, // zsub3 |
| 25062 | 0, // zsub_hi |
| 25063 | 0, // dsub1_then_bsub |
| 25064 | 0, // dsub1_then_hsub |
| 25065 | 0, // dsub1_then_ssub |
| 25066 | 0, // dsub3_then_bsub |
| 25067 | 0, // dsub3_then_hsub |
| 25068 | 0, // dsub3_then_ssub |
| 25069 | 0, // dsub2_then_bsub |
| 25070 | 0, // dsub2_then_hsub |
| 25071 | 0, // dsub2_then_ssub |
| 25072 | 0, // qsub1_then_bsub |
| 25073 | 0, // qsub1_then_dsub |
| 25074 | 0, // qsub1_then_hsub |
| 25075 | 0, // qsub1_then_ssub |
| 25076 | 0, // qsub3_then_bsub |
| 25077 | 0, // qsub3_then_dsub |
| 25078 | 0, // qsub3_then_hsub |
| 25079 | 0, // qsub3_then_ssub |
| 25080 | 0, // qsub2_then_bsub |
| 25081 | 0, // qsub2_then_dsub |
| 25082 | 0, // qsub2_then_hsub |
| 25083 | 0, // qsub2_then_ssub |
| 25084 | 0, // x8sub_7_then_sub_32 |
| 25085 | 0, // x8sub_6_then_sub_32 |
| 25086 | 0, // x8sub_5_then_sub_32 |
| 25087 | 0, // x8sub_4_then_sub_32 |
| 25088 | 0, // x8sub_3_then_sub_32 |
| 25089 | 0, // x8sub_2_then_sub_32 |
| 25090 | 0, // x8sub_1_then_sub_32 |
| 25091 | 96, // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 25092 | 0, // zsub1_then_bsub |
| 25093 | 0, // zsub1_then_dsub |
| 25094 | 0, // zsub1_then_hsub |
| 25095 | 0, // zsub1_then_ssub |
| 25096 | 0, // zsub1_then_zsub |
| 25097 | 0, // zsub1_then_zsub_hi |
| 25098 | 0, // zsub3_then_bsub |
| 25099 | 0, // zsub3_then_dsub |
| 25100 | 0, // zsub3_then_hsub |
| 25101 | 0, // zsub3_then_ssub |
| 25102 | 0, // zsub3_then_zsub |
| 25103 | 0, // zsub3_then_zsub_hi |
| 25104 | 0, // zsub2_then_bsub |
| 25105 | 0, // zsub2_then_dsub |
| 25106 | 0, // zsub2_then_hsub |
| 25107 | 0, // zsub2_then_ssub |
| 25108 | 0, // zsub2_then_zsub |
| 25109 | 0, // zsub2_then_zsub_hi |
| 25110 | 0, // dsub0_dsub1 |
| 25111 | 0, // dsub0_dsub1_dsub2 |
| 25112 | 0, // dsub1_dsub2 |
| 25113 | 0, // dsub1_dsub2_dsub3 |
| 25114 | 0, // dsub2_dsub3 |
| 25115 | 0, // dsub_qsub1_then_dsub |
| 25116 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25117 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25118 | 0, // qsub0_qsub1 |
| 25119 | 0, // qsub0_qsub1_qsub2 |
| 25120 | 0, // qsub1_qsub2 |
| 25121 | 0, // qsub1_qsub2_qsub3 |
| 25122 | 0, // qsub2_qsub3 |
| 25123 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25124 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25125 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25126 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25127 | 0, // x8sub_0_x8sub_1 |
| 25128 | 0, // x8sub_2_x8sub_3 |
| 25129 | 0, // x8sub_4_x8sub_5 |
| 25130 | 0, // x8sub_6_x8sub_7 |
| 25131 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25132 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25133 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25134 | 96, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 25135 | 0, // dsub_zsub1_then_dsub |
| 25136 | 0, // zsub_zsub1_then_zsub |
| 25137 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25138 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25139 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25140 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25141 | 0, // zsub0_zsub1 |
| 25142 | 0, // zsub0_zsub1_zsub2 |
| 25143 | 0, // zsub1_zsub2 |
| 25144 | 0, // zsub1_zsub2_zsub3 |
| 25145 | 0, // zsub2_zsub3 |
| 25146 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25147 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25148 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25149 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25150 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25151 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25152 | }, |
| 25153 | { // XSeqPairsClass_with_subo64_in_tcGPR64 |
| 25154 | 0, // bsub |
| 25155 | 0, // dsub |
| 25156 | 0, // dsub0 |
| 25157 | 0, // dsub1 |
| 25158 | 0, // dsub2 |
| 25159 | 0, // dsub3 |
| 25160 | 0, // hsub |
| 25161 | 0, // qhisub |
| 25162 | 0, // qsub |
| 25163 | 0, // qsub0 |
| 25164 | 0, // qsub1 |
| 25165 | 0, // qsub2 |
| 25166 | 0, // qsub3 |
| 25167 | 0, // ssub |
| 25168 | 97, // sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64 |
| 25169 | 0, // sube32 |
| 25170 | 97, // sube64 -> XSeqPairsClass_with_subo64_in_tcGPR64 |
| 25171 | 0, // subo32 |
| 25172 | 97, // subo64 -> XSeqPairsClass_with_subo64_in_tcGPR64 |
| 25173 | 0, // x8sub_0 |
| 25174 | 0, // x8sub_1 |
| 25175 | 0, // x8sub_2 |
| 25176 | 0, // x8sub_3 |
| 25177 | 0, // x8sub_4 |
| 25178 | 0, // x8sub_5 |
| 25179 | 0, // x8sub_6 |
| 25180 | 0, // x8sub_7 |
| 25181 | 0, // zsub |
| 25182 | 0, // zsub0 |
| 25183 | 0, // zsub1 |
| 25184 | 0, // zsub2 |
| 25185 | 0, // zsub3 |
| 25186 | 0, // zsub_hi |
| 25187 | 0, // dsub1_then_bsub |
| 25188 | 0, // dsub1_then_hsub |
| 25189 | 0, // dsub1_then_ssub |
| 25190 | 0, // dsub3_then_bsub |
| 25191 | 0, // dsub3_then_hsub |
| 25192 | 0, // dsub3_then_ssub |
| 25193 | 0, // dsub2_then_bsub |
| 25194 | 0, // dsub2_then_hsub |
| 25195 | 0, // dsub2_then_ssub |
| 25196 | 0, // qsub1_then_bsub |
| 25197 | 0, // qsub1_then_dsub |
| 25198 | 0, // qsub1_then_hsub |
| 25199 | 0, // qsub1_then_ssub |
| 25200 | 0, // qsub3_then_bsub |
| 25201 | 0, // qsub3_then_dsub |
| 25202 | 0, // qsub3_then_hsub |
| 25203 | 0, // qsub3_then_ssub |
| 25204 | 0, // qsub2_then_bsub |
| 25205 | 0, // qsub2_then_dsub |
| 25206 | 0, // qsub2_then_hsub |
| 25207 | 0, // qsub2_then_ssub |
| 25208 | 0, // x8sub_7_then_sub_32 |
| 25209 | 0, // x8sub_6_then_sub_32 |
| 25210 | 0, // x8sub_5_then_sub_32 |
| 25211 | 0, // x8sub_4_then_sub_32 |
| 25212 | 0, // x8sub_3_then_sub_32 |
| 25213 | 0, // x8sub_2_then_sub_32 |
| 25214 | 0, // x8sub_1_then_sub_32 |
| 25215 | 97, // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64 |
| 25216 | 0, // zsub1_then_bsub |
| 25217 | 0, // zsub1_then_dsub |
| 25218 | 0, // zsub1_then_hsub |
| 25219 | 0, // zsub1_then_ssub |
| 25220 | 0, // zsub1_then_zsub |
| 25221 | 0, // zsub1_then_zsub_hi |
| 25222 | 0, // zsub3_then_bsub |
| 25223 | 0, // zsub3_then_dsub |
| 25224 | 0, // zsub3_then_hsub |
| 25225 | 0, // zsub3_then_ssub |
| 25226 | 0, // zsub3_then_zsub |
| 25227 | 0, // zsub3_then_zsub_hi |
| 25228 | 0, // zsub2_then_bsub |
| 25229 | 0, // zsub2_then_dsub |
| 25230 | 0, // zsub2_then_hsub |
| 25231 | 0, // zsub2_then_ssub |
| 25232 | 0, // zsub2_then_zsub |
| 25233 | 0, // zsub2_then_zsub_hi |
| 25234 | 0, // dsub0_dsub1 |
| 25235 | 0, // dsub0_dsub1_dsub2 |
| 25236 | 0, // dsub1_dsub2 |
| 25237 | 0, // dsub1_dsub2_dsub3 |
| 25238 | 0, // dsub2_dsub3 |
| 25239 | 0, // dsub_qsub1_then_dsub |
| 25240 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25241 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25242 | 0, // qsub0_qsub1 |
| 25243 | 0, // qsub0_qsub1_qsub2 |
| 25244 | 0, // qsub1_qsub2 |
| 25245 | 0, // qsub1_qsub2_qsub3 |
| 25246 | 0, // qsub2_qsub3 |
| 25247 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25248 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25249 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25250 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25251 | 0, // x8sub_0_x8sub_1 |
| 25252 | 0, // x8sub_2_x8sub_3 |
| 25253 | 0, // x8sub_4_x8sub_5 |
| 25254 | 0, // x8sub_6_x8sub_7 |
| 25255 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25256 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25257 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25258 | 97, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_tcGPR64 |
| 25259 | 0, // dsub_zsub1_then_dsub |
| 25260 | 0, // zsub_zsub1_then_zsub |
| 25261 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25262 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25263 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25264 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25265 | 0, // zsub0_zsub1 |
| 25266 | 0, // zsub0_zsub1_zsub2 |
| 25267 | 0, // zsub1_zsub2 |
| 25268 | 0, // zsub1_zsub2_zsub3 |
| 25269 | 0, // zsub2_zsub3 |
| 25270 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25271 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25272 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25273 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25274 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25275 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25276 | }, |
| 25277 | { // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 25278 | 0, // bsub |
| 25279 | 0, // dsub |
| 25280 | 0, // dsub0 |
| 25281 | 0, // dsub1 |
| 25282 | 0, // dsub2 |
| 25283 | 0, // dsub3 |
| 25284 | 0, // hsub |
| 25285 | 0, // qhisub |
| 25286 | 0, // qsub |
| 25287 | 0, // qsub0 |
| 25288 | 0, // qsub1 |
| 25289 | 0, // qsub2 |
| 25290 | 0, // qsub3 |
| 25291 | 0, // ssub |
| 25292 | 98, // sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 25293 | 0, // sube32 |
| 25294 | 98, // sube64 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 25295 | 0, // subo32 |
| 25296 | 98, // subo64 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 25297 | 0, // x8sub_0 |
| 25298 | 0, // x8sub_1 |
| 25299 | 0, // x8sub_2 |
| 25300 | 0, // x8sub_3 |
| 25301 | 0, // x8sub_4 |
| 25302 | 0, // x8sub_5 |
| 25303 | 0, // x8sub_6 |
| 25304 | 0, // x8sub_7 |
| 25305 | 0, // zsub |
| 25306 | 0, // zsub0 |
| 25307 | 0, // zsub1 |
| 25308 | 0, // zsub2 |
| 25309 | 0, // zsub3 |
| 25310 | 0, // zsub_hi |
| 25311 | 0, // dsub1_then_bsub |
| 25312 | 0, // dsub1_then_hsub |
| 25313 | 0, // dsub1_then_ssub |
| 25314 | 0, // dsub3_then_bsub |
| 25315 | 0, // dsub3_then_hsub |
| 25316 | 0, // dsub3_then_ssub |
| 25317 | 0, // dsub2_then_bsub |
| 25318 | 0, // dsub2_then_hsub |
| 25319 | 0, // dsub2_then_ssub |
| 25320 | 0, // qsub1_then_bsub |
| 25321 | 0, // qsub1_then_dsub |
| 25322 | 0, // qsub1_then_hsub |
| 25323 | 0, // qsub1_then_ssub |
| 25324 | 0, // qsub3_then_bsub |
| 25325 | 0, // qsub3_then_dsub |
| 25326 | 0, // qsub3_then_hsub |
| 25327 | 0, // qsub3_then_ssub |
| 25328 | 0, // qsub2_then_bsub |
| 25329 | 0, // qsub2_then_dsub |
| 25330 | 0, // qsub2_then_hsub |
| 25331 | 0, // qsub2_then_ssub |
| 25332 | 0, // x8sub_7_then_sub_32 |
| 25333 | 0, // x8sub_6_then_sub_32 |
| 25334 | 0, // x8sub_5_then_sub_32 |
| 25335 | 0, // x8sub_4_then_sub_32 |
| 25336 | 0, // x8sub_3_then_sub_32 |
| 25337 | 0, // x8sub_2_then_sub_32 |
| 25338 | 0, // x8sub_1_then_sub_32 |
| 25339 | 98, // subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 25340 | 0, // zsub1_then_bsub |
| 25341 | 0, // zsub1_then_dsub |
| 25342 | 0, // zsub1_then_hsub |
| 25343 | 0, // zsub1_then_ssub |
| 25344 | 0, // zsub1_then_zsub |
| 25345 | 0, // zsub1_then_zsub_hi |
| 25346 | 0, // zsub3_then_bsub |
| 25347 | 0, // zsub3_then_dsub |
| 25348 | 0, // zsub3_then_hsub |
| 25349 | 0, // zsub3_then_ssub |
| 25350 | 0, // zsub3_then_zsub |
| 25351 | 0, // zsub3_then_zsub_hi |
| 25352 | 0, // zsub2_then_bsub |
| 25353 | 0, // zsub2_then_dsub |
| 25354 | 0, // zsub2_then_hsub |
| 25355 | 0, // zsub2_then_ssub |
| 25356 | 0, // zsub2_then_zsub |
| 25357 | 0, // zsub2_then_zsub_hi |
| 25358 | 0, // dsub0_dsub1 |
| 25359 | 0, // dsub0_dsub1_dsub2 |
| 25360 | 0, // dsub1_dsub2 |
| 25361 | 0, // dsub1_dsub2_dsub3 |
| 25362 | 0, // dsub2_dsub3 |
| 25363 | 0, // dsub_qsub1_then_dsub |
| 25364 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25365 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25366 | 0, // qsub0_qsub1 |
| 25367 | 0, // qsub0_qsub1_qsub2 |
| 25368 | 0, // qsub1_qsub2 |
| 25369 | 0, // qsub1_qsub2_qsub3 |
| 25370 | 0, // qsub2_qsub3 |
| 25371 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25372 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25373 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25374 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25375 | 0, // x8sub_0_x8sub_1 |
| 25376 | 0, // x8sub_2_x8sub_3 |
| 25377 | 0, // x8sub_4_x8sub_5 |
| 25378 | 0, // x8sub_6_x8sub_7 |
| 25379 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25380 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25381 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25382 | 98, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 25383 | 0, // dsub_zsub1_then_dsub |
| 25384 | 0, // zsub_zsub1_then_zsub |
| 25385 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25386 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25387 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25388 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25389 | 0, // zsub0_zsub1 |
| 25390 | 0, // zsub0_zsub1_zsub2 |
| 25391 | 0, // zsub1_zsub2 |
| 25392 | 0, // zsub1_zsub2_zsub3 |
| 25393 | 0, // zsub2_zsub3 |
| 25394 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25395 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25396 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25397 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25398 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25399 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25400 | }, |
| 25401 | { // XSeqPairsClass_with_sub_32_in_GPR32arg |
| 25402 | 0, // bsub |
| 25403 | 0, // dsub |
| 25404 | 0, // dsub0 |
| 25405 | 0, // dsub1 |
| 25406 | 0, // dsub2 |
| 25407 | 0, // dsub3 |
| 25408 | 0, // hsub |
| 25409 | 0, // qhisub |
| 25410 | 0, // qsub |
| 25411 | 0, // qsub0 |
| 25412 | 0, // qsub1 |
| 25413 | 0, // qsub2 |
| 25414 | 0, // qsub3 |
| 25415 | 0, // ssub |
| 25416 | 99, // sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32arg |
| 25417 | 0, // sube32 |
| 25418 | 99, // sube64 -> XSeqPairsClass_with_sub_32_in_GPR32arg |
| 25419 | 0, // subo32 |
| 25420 | 99, // subo64 -> XSeqPairsClass_with_sub_32_in_GPR32arg |
| 25421 | 0, // x8sub_0 |
| 25422 | 0, // x8sub_1 |
| 25423 | 0, // x8sub_2 |
| 25424 | 0, // x8sub_3 |
| 25425 | 0, // x8sub_4 |
| 25426 | 0, // x8sub_5 |
| 25427 | 0, // x8sub_6 |
| 25428 | 0, // x8sub_7 |
| 25429 | 0, // zsub |
| 25430 | 0, // zsub0 |
| 25431 | 0, // zsub1 |
| 25432 | 0, // zsub2 |
| 25433 | 0, // zsub3 |
| 25434 | 0, // zsub_hi |
| 25435 | 0, // dsub1_then_bsub |
| 25436 | 0, // dsub1_then_hsub |
| 25437 | 0, // dsub1_then_ssub |
| 25438 | 0, // dsub3_then_bsub |
| 25439 | 0, // dsub3_then_hsub |
| 25440 | 0, // dsub3_then_ssub |
| 25441 | 0, // dsub2_then_bsub |
| 25442 | 0, // dsub2_then_hsub |
| 25443 | 0, // dsub2_then_ssub |
| 25444 | 0, // qsub1_then_bsub |
| 25445 | 0, // qsub1_then_dsub |
| 25446 | 0, // qsub1_then_hsub |
| 25447 | 0, // qsub1_then_ssub |
| 25448 | 0, // qsub3_then_bsub |
| 25449 | 0, // qsub3_then_dsub |
| 25450 | 0, // qsub3_then_hsub |
| 25451 | 0, // qsub3_then_ssub |
| 25452 | 0, // qsub2_then_bsub |
| 25453 | 0, // qsub2_then_dsub |
| 25454 | 0, // qsub2_then_hsub |
| 25455 | 0, // qsub2_then_ssub |
| 25456 | 0, // x8sub_7_then_sub_32 |
| 25457 | 0, // x8sub_6_then_sub_32 |
| 25458 | 0, // x8sub_5_then_sub_32 |
| 25459 | 0, // x8sub_4_then_sub_32 |
| 25460 | 0, // x8sub_3_then_sub_32 |
| 25461 | 0, // x8sub_2_then_sub_32 |
| 25462 | 0, // x8sub_1_then_sub_32 |
| 25463 | 99, // subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32arg |
| 25464 | 0, // zsub1_then_bsub |
| 25465 | 0, // zsub1_then_dsub |
| 25466 | 0, // zsub1_then_hsub |
| 25467 | 0, // zsub1_then_ssub |
| 25468 | 0, // zsub1_then_zsub |
| 25469 | 0, // zsub1_then_zsub_hi |
| 25470 | 0, // zsub3_then_bsub |
| 25471 | 0, // zsub3_then_dsub |
| 25472 | 0, // zsub3_then_hsub |
| 25473 | 0, // zsub3_then_ssub |
| 25474 | 0, // zsub3_then_zsub |
| 25475 | 0, // zsub3_then_zsub_hi |
| 25476 | 0, // zsub2_then_bsub |
| 25477 | 0, // zsub2_then_dsub |
| 25478 | 0, // zsub2_then_hsub |
| 25479 | 0, // zsub2_then_ssub |
| 25480 | 0, // zsub2_then_zsub |
| 25481 | 0, // zsub2_then_zsub_hi |
| 25482 | 0, // dsub0_dsub1 |
| 25483 | 0, // dsub0_dsub1_dsub2 |
| 25484 | 0, // dsub1_dsub2 |
| 25485 | 0, // dsub1_dsub2_dsub3 |
| 25486 | 0, // dsub2_dsub3 |
| 25487 | 0, // dsub_qsub1_then_dsub |
| 25488 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25489 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25490 | 0, // qsub0_qsub1 |
| 25491 | 0, // qsub0_qsub1_qsub2 |
| 25492 | 0, // qsub1_qsub2 |
| 25493 | 0, // qsub1_qsub2_qsub3 |
| 25494 | 0, // qsub2_qsub3 |
| 25495 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25496 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25497 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25498 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25499 | 0, // x8sub_0_x8sub_1 |
| 25500 | 0, // x8sub_2_x8sub_3 |
| 25501 | 0, // x8sub_4_x8sub_5 |
| 25502 | 0, // x8sub_6_x8sub_7 |
| 25503 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25504 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25505 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25506 | 99, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sub_32_in_GPR32arg |
| 25507 | 0, // dsub_zsub1_then_dsub |
| 25508 | 0, // zsub_zsub1_then_zsub |
| 25509 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25510 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25511 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25512 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25513 | 0, // zsub0_zsub1 |
| 25514 | 0, // zsub0_zsub1_zsub2 |
| 25515 | 0, // zsub1_zsub2 |
| 25516 | 0, // zsub1_zsub2_zsub3 |
| 25517 | 0, // zsub2_zsub3 |
| 25518 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25519 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25520 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25521 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25522 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25523 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25524 | }, |
| 25525 | { // XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 25526 | 0, // bsub |
| 25527 | 0, // dsub |
| 25528 | 0, // dsub0 |
| 25529 | 0, // dsub1 |
| 25530 | 0, // dsub2 |
| 25531 | 0, // dsub3 |
| 25532 | 0, // hsub |
| 25533 | 0, // qhisub |
| 25534 | 0, // qsub |
| 25535 | 0, // qsub0 |
| 25536 | 0, // qsub1 |
| 25537 | 0, // qsub2 |
| 25538 | 0, // qsub3 |
| 25539 | 0, // ssub |
| 25540 | 100, // sub_32 -> XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 25541 | 0, // sube32 |
| 25542 | 100, // sube64 -> XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 25543 | 0, // subo32 |
| 25544 | 100, // subo64 -> XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 25545 | 0, // x8sub_0 |
| 25546 | 0, // x8sub_1 |
| 25547 | 0, // x8sub_2 |
| 25548 | 0, // x8sub_3 |
| 25549 | 0, // x8sub_4 |
| 25550 | 0, // x8sub_5 |
| 25551 | 0, // x8sub_6 |
| 25552 | 0, // x8sub_7 |
| 25553 | 0, // zsub |
| 25554 | 0, // zsub0 |
| 25555 | 0, // zsub1 |
| 25556 | 0, // zsub2 |
| 25557 | 0, // zsub3 |
| 25558 | 0, // zsub_hi |
| 25559 | 0, // dsub1_then_bsub |
| 25560 | 0, // dsub1_then_hsub |
| 25561 | 0, // dsub1_then_ssub |
| 25562 | 0, // dsub3_then_bsub |
| 25563 | 0, // dsub3_then_hsub |
| 25564 | 0, // dsub3_then_ssub |
| 25565 | 0, // dsub2_then_bsub |
| 25566 | 0, // dsub2_then_hsub |
| 25567 | 0, // dsub2_then_ssub |
| 25568 | 0, // qsub1_then_bsub |
| 25569 | 0, // qsub1_then_dsub |
| 25570 | 0, // qsub1_then_hsub |
| 25571 | 0, // qsub1_then_ssub |
| 25572 | 0, // qsub3_then_bsub |
| 25573 | 0, // qsub3_then_dsub |
| 25574 | 0, // qsub3_then_hsub |
| 25575 | 0, // qsub3_then_ssub |
| 25576 | 0, // qsub2_then_bsub |
| 25577 | 0, // qsub2_then_dsub |
| 25578 | 0, // qsub2_then_hsub |
| 25579 | 0, // qsub2_then_ssub |
| 25580 | 0, // x8sub_7_then_sub_32 |
| 25581 | 0, // x8sub_6_then_sub_32 |
| 25582 | 0, // x8sub_5_then_sub_32 |
| 25583 | 0, // x8sub_4_then_sub_32 |
| 25584 | 0, // x8sub_3_then_sub_32 |
| 25585 | 0, // x8sub_2_then_sub_32 |
| 25586 | 0, // x8sub_1_then_sub_32 |
| 25587 | 100, // subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 25588 | 0, // zsub1_then_bsub |
| 25589 | 0, // zsub1_then_dsub |
| 25590 | 0, // zsub1_then_hsub |
| 25591 | 0, // zsub1_then_ssub |
| 25592 | 0, // zsub1_then_zsub |
| 25593 | 0, // zsub1_then_zsub_hi |
| 25594 | 0, // zsub3_then_bsub |
| 25595 | 0, // zsub3_then_dsub |
| 25596 | 0, // zsub3_then_hsub |
| 25597 | 0, // zsub3_then_ssub |
| 25598 | 0, // zsub3_then_zsub |
| 25599 | 0, // zsub3_then_zsub_hi |
| 25600 | 0, // zsub2_then_bsub |
| 25601 | 0, // zsub2_then_dsub |
| 25602 | 0, // zsub2_then_hsub |
| 25603 | 0, // zsub2_then_ssub |
| 25604 | 0, // zsub2_then_zsub |
| 25605 | 0, // zsub2_then_zsub_hi |
| 25606 | 0, // dsub0_dsub1 |
| 25607 | 0, // dsub0_dsub1_dsub2 |
| 25608 | 0, // dsub1_dsub2 |
| 25609 | 0, // dsub1_dsub2_dsub3 |
| 25610 | 0, // dsub2_dsub3 |
| 25611 | 0, // dsub_qsub1_then_dsub |
| 25612 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25613 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25614 | 0, // qsub0_qsub1 |
| 25615 | 0, // qsub0_qsub1_qsub2 |
| 25616 | 0, // qsub1_qsub2 |
| 25617 | 0, // qsub1_qsub2_qsub3 |
| 25618 | 0, // qsub2_qsub3 |
| 25619 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25620 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25621 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25622 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25623 | 0, // x8sub_0_x8sub_1 |
| 25624 | 0, // x8sub_2_x8sub_3 |
| 25625 | 0, // x8sub_4_x8sub_5 |
| 25626 | 0, // x8sub_6_x8sub_7 |
| 25627 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25628 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25629 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25630 | 100, // sub_32_subo64_then_sub_32 -> XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 25631 | 0, // dsub_zsub1_then_dsub |
| 25632 | 0, // zsub_zsub1_then_zsub |
| 25633 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25634 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25635 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25636 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25637 | 0, // zsub0_zsub1 |
| 25638 | 0, // zsub0_zsub1_zsub2 |
| 25639 | 0, // zsub1_zsub2 |
| 25640 | 0, // zsub1_zsub2_zsub3 |
| 25641 | 0, // zsub2_zsub3 |
| 25642 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25643 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25644 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25645 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25646 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25647 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25648 | }, |
| 25649 | { // FPR128 |
| 25650 | 101, // bsub -> FPR128 |
| 25651 | 101, // dsub -> FPR128 |
| 25652 | 0, // dsub0 |
| 25653 | 0, // dsub1 |
| 25654 | 0, // dsub2 |
| 25655 | 0, // dsub3 |
| 25656 | 101, // hsub -> FPR128 |
| 25657 | 0, // qhisub |
| 25658 | 0, // qsub |
| 25659 | 0, // qsub0 |
| 25660 | 0, // qsub1 |
| 25661 | 0, // qsub2 |
| 25662 | 0, // qsub3 |
| 25663 | 101, // ssub -> FPR128 |
| 25664 | 0, // sub_32 |
| 25665 | 0, // sube32 |
| 25666 | 0, // sube64 |
| 25667 | 0, // subo32 |
| 25668 | 0, // subo64 |
| 25669 | 0, // x8sub_0 |
| 25670 | 0, // x8sub_1 |
| 25671 | 0, // x8sub_2 |
| 25672 | 0, // x8sub_3 |
| 25673 | 0, // x8sub_4 |
| 25674 | 0, // x8sub_5 |
| 25675 | 0, // x8sub_6 |
| 25676 | 0, // x8sub_7 |
| 25677 | 0, // zsub |
| 25678 | 0, // zsub0 |
| 25679 | 0, // zsub1 |
| 25680 | 0, // zsub2 |
| 25681 | 0, // zsub3 |
| 25682 | 0, // zsub_hi |
| 25683 | 0, // dsub1_then_bsub |
| 25684 | 0, // dsub1_then_hsub |
| 25685 | 0, // dsub1_then_ssub |
| 25686 | 0, // dsub3_then_bsub |
| 25687 | 0, // dsub3_then_hsub |
| 25688 | 0, // dsub3_then_ssub |
| 25689 | 0, // dsub2_then_bsub |
| 25690 | 0, // dsub2_then_hsub |
| 25691 | 0, // dsub2_then_ssub |
| 25692 | 0, // qsub1_then_bsub |
| 25693 | 0, // qsub1_then_dsub |
| 25694 | 0, // qsub1_then_hsub |
| 25695 | 0, // qsub1_then_ssub |
| 25696 | 0, // qsub3_then_bsub |
| 25697 | 0, // qsub3_then_dsub |
| 25698 | 0, // qsub3_then_hsub |
| 25699 | 0, // qsub3_then_ssub |
| 25700 | 0, // qsub2_then_bsub |
| 25701 | 0, // qsub2_then_dsub |
| 25702 | 0, // qsub2_then_hsub |
| 25703 | 0, // qsub2_then_ssub |
| 25704 | 0, // x8sub_7_then_sub_32 |
| 25705 | 0, // x8sub_6_then_sub_32 |
| 25706 | 0, // x8sub_5_then_sub_32 |
| 25707 | 0, // x8sub_4_then_sub_32 |
| 25708 | 0, // x8sub_3_then_sub_32 |
| 25709 | 0, // x8sub_2_then_sub_32 |
| 25710 | 0, // x8sub_1_then_sub_32 |
| 25711 | 0, // subo64_then_sub_32 |
| 25712 | 0, // zsub1_then_bsub |
| 25713 | 0, // zsub1_then_dsub |
| 25714 | 0, // zsub1_then_hsub |
| 25715 | 0, // zsub1_then_ssub |
| 25716 | 0, // zsub1_then_zsub |
| 25717 | 0, // zsub1_then_zsub_hi |
| 25718 | 0, // zsub3_then_bsub |
| 25719 | 0, // zsub3_then_dsub |
| 25720 | 0, // zsub3_then_hsub |
| 25721 | 0, // zsub3_then_ssub |
| 25722 | 0, // zsub3_then_zsub |
| 25723 | 0, // zsub3_then_zsub_hi |
| 25724 | 0, // zsub2_then_bsub |
| 25725 | 0, // zsub2_then_dsub |
| 25726 | 0, // zsub2_then_hsub |
| 25727 | 0, // zsub2_then_ssub |
| 25728 | 0, // zsub2_then_zsub |
| 25729 | 0, // zsub2_then_zsub_hi |
| 25730 | 0, // dsub0_dsub1 |
| 25731 | 0, // dsub0_dsub1_dsub2 |
| 25732 | 0, // dsub1_dsub2 |
| 25733 | 0, // dsub1_dsub2_dsub3 |
| 25734 | 0, // dsub2_dsub3 |
| 25735 | 0, // dsub_qsub1_then_dsub |
| 25736 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25737 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25738 | 0, // qsub0_qsub1 |
| 25739 | 0, // qsub0_qsub1_qsub2 |
| 25740 | 0, // qsub1_qsub2 |
| 25741 | 0, // qsub1_qsub2_qsub3 |
| 25742 | 0, // qsub2_qsub3 |
| 25743 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25744 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25745 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25746 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25747 | 0, // x8sub_0_x8sub_1 |
| 25748 | 0, // x8sub_2_x8sub_3 |
| 25749 | 0, // x8sub_4_x8sub_5 |
| 25750 | 0, // x8sub_6_x8sub_7 |
| 25751 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25752 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25753 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25754 | 0, // sub_32_subo64_then_sub_32 |
| 25755 | 0, // dsub_zsub1_then_dsub |
| 25756 | 0, // zsub_zsub1_then_zsub |
| 25757 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25758 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25759 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25760 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25761 | 0, // zsub0_zsub1 |
| 25762 | 0, // zsub0_zsub1_zsub2 |
| 25763 | 0, // zsub1_zsub2 |
| 25764 | 0, // zsub1_zsub2_zsub3 |
| 25765 | 0, // zsub2_zsub3 |
| 25766 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25767 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25768 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25769 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25770 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25771 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25772 | }, |
| 25773 | { // ZPR |
| 25774 | 102, // bsub -> ZPR |
| 25775 | 102, // dsub -> ZPR |
| 25776 | 0, // dsub0 |
| 25777 | 0, // dsub1 |
| 25778 | 0, // dsub2 |
| 25779 | 0, // dsub3 |
| 25780 | 102, // hsub -> ZPR |
| 25781 | 0, // qhisub |
| 25782 | 0, // qsub |
| 25783 | 0, // qsub0 |
| 25784 | 0, // qsub1 |
| 25785 | 0, // qsub2 |
| 25786 | 0, // qsub3 |
| 25787 | 102, // ssub -> ZPR |
| 25788 | 0, // sub_32 |
| 25789 | 0, // sube32 |
| 25790 | 0, // sube64 |
| 25791 | 0, // subo32 |
| 25792 | 0, // subo64 |
| 25793 | 0, // x8sub_0 |
| 25794 | 0, // x8sub_1 |
| 25795 | 0, // x8sub_2 |
| 25796 | 0, // x8sub_3 |
| 25797 | 0, // x8sub_4 |
| 25798 | 0, // x8sub_5 |
| 25799 | 0, // x8sub_6 |
| 25800 | 0, // x8sub_7 |
| 25801 | 102, // zsub -> ZPR |
| 25802 | 0, // zsub0 |
| 25803 | 0, // zsub1 |
| 25804 | 0, // zsub2 |
| 25805 | 0, // zsub3 |
| 25806 | 102, // zsub_hi -> ZPR |
| 25807 | 0, // dsub1_then_bsub |
| 25808 | 0, // dsub1_then_hsub |
| 25809 | 0, // dsub1_then_ssub |
| 25810 | 0, // dsub3_then_bsub |
| 25811 | 0, // dsub3_then_hsub |
| 25812 | 0, // dsub3_then_ssub |
| 25813 | 0, // dsub2_then_bsub |
| 25814 | 0, // dsub2_then_hsub |
| 25815 | 0, // dsub2_then_ssub |
| 25816 | 0, // qsub1_then_bsub |
| 25817 | 0, // qsub1_then_dsub |
| 25818 | 0, // qsub1_then_hsub |
| 25819 | 0, // qsub1_then_ssub |
| 25820 | 0, // qsub3_then_bsub |
| 25821 | 0, // qsub3_then_dsub |
| 25822 | 0, // qsub3_then_hsub |
| 25823 | 0, // qsub3_then_ssub |
| 25824 | 0, // qsub2_then_bsub |
| 25825 | 0, // qsub2_then_dsub |
| 25826 | 0, // qsub2_then_hsub |
| 25827 | 0, // qsub2_then_ssub |
| 25828 | 0, // x8sub_7_then_sub_32 |
| 25829 | 0, // x8sub_6_then_sub_32 |
| 25830 | 0, // x8sub_5_then_sub_32 |
| 25831 | 0, // x8sub_4_then_sub_32 |
| 25832 | 0, // x8sub_3_then_sub_32 |
| 25833 | 0, // x8sub_2_then_sub_32 |
| 25834 | 0, // x8sub_1_then_sub_32 |
| 25835 | 0, // subo64_then_sub_32 |
| 25836 | 0, // zsub1_then_bsub |
| 25837 | 0, // zsub1_then_dsub |
| 25838 | 0, // zsub1_then_hsub |
| 25839 | 0, // zsub1_then_ssub |
| 25840 | 0, // zsub1_then_zsub |
| 25841 | 0, // zsub1_then_zsub_hi |
| 25842 | 0, // zsub3_then_bsub |
| 25843 | 0, // zsub3_then_dsub |
| 25844 | 0, // zsub3_then_hsub |
| 25845 | 0, // zsub3_then_ssub |
| 25846 | 0, // zsub3_then_zsub |
| 25847 | 0, // zsub3_then_zsub_hi |
| 25848 | 0, // zsub2_then_bsub |
| 25849 | 0, // zsub2_then_dsub |
| 25850 | 0, // zsub2_then_hsub |
| 25851 | 0, // zsub2_then_ssub |
| 25852 | 0, // zsub2_then_zsub |
| 25853 | 0, // zsub2_then_zsub_hi |
| 25854 | 0, // dsub0_dsub1 |
| 25855 | 0, // dsub0_dsub1_dsub2 |
| 25856 | 0, // dsub1_dsub2 |
| 25857 | 0, // dsub1_dsub2_dsub3 |
| 25858 | 0, // dsub2_dsub3 |
| 25859 | 0, // dsub_qsub1_then_dsub |
| 25860 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25861 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25862 | 0, // qsub0_qsub1 |
| 25863 | 0, // qsub0_qsub1_qsub2 |
| 25864 | 0, // qsub1_qsub2 |
| 25865 | 0, // qsub1_qsub2_qsub3 |
| 25866 | 0, // qsub2_qsub3 |
| 25867 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25868 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25869 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25870 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25871 | 0, // x8sub_0_x8sub_1 |
| 25872 | 0, // x8sub_2_x8sub_3 |
| 25873 | 0, // x8sub_4_x8sub_5 |
| 25874 | 0, // x8sub_6_x8sub_7 |
| 25875 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 25876 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 25877 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 25878 | 0, // sub_32_subo64_then_sub_32 |
| 25879 | 0, // dsub_zsub1_then_dsub |
| 25880 | 0, // zsub_zsub1_then_zsub |
| 25881 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25882 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 25883 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25884 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 25885 | 0, // zsub0_zsub1 |
| 25886 | 0, // zsub0_zsub1_zsub2 |
| 25887 | 0, // zsub1_zsub2 |
| 25888 | 0, // zsub1_zsub2_zsub3 |
| 25889 | 0, // zsub2_zsub3 |
| 25890 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 25891 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 25892 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 25893 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 25894 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 25895 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 25896 | }, |
| 25897 | { // FPR128_lo |
| 25898 | 103, // bsub -> FPR128_lo |
| 25899 | 103, // dsub -> FPR128_lo |
| 25900 | 0, // dsub0 |
| 25901 | 0, // dsub1 |
| 25902 | 0, // dsub2 |
| 25903 | 0, // dsub3 |
| 25904 | 103, // hsub -> FPR128_lo |
| 25905 | 0, // qhisub |
| 25906 | 0, // qsub |
| 25907 | 0, // qsub0 |
| 25908 | 0, // qsub1 |
| 25909 | 0, // qsub2 |
| 25910 | 0, // qsub3 |
| 25911 | 103, // ssub -> FPR128_lo |
| 25912 | 0, // sub_32 |
| 25913 | 0, // sube32 |
| 25914 | 0, // sube64 |
| 25915 | 0, // subo32 |
| 25916 | 0, // subo64 |
| 25917 | 0, // x8sub_0 |
| 25918 | 0, // x8sub_1 |
| 25919 | 0, // x8sub_2 |
| 25920 | 0, // x8sub_3 |
| 25921 | 0, // x8sub_4 |
| 25922 | 0, // x8sub_5 |
| 25923 | 0, // x8sub_6 |
| 25924 | 0, // x8sub_7 |
| 25925 | 0, // zsub |
| 25926 | 0, // zsub0 |
| 25927 | 0, // zsub1 |
| 25928 | 0, // zsub2 |
| 25929 | 0, // zsub3 |
| 25930 | 0, // zsub_hi |
| 25931 | 0, // dsub1_then_bsub |
| 25932 | 0, // dsub1_then_hsub |
| 25933 | 0, // dsub1_then_ssub |
| 25934 | 0, // dsub3_then_bsub |
| 25935 | 0, // dsub3_then_hsub |
| 25936 | 0, // dsub3_then_ssub |
| 25937 | 0, // dsub2_then_bsub |
| 25938 | 0, // dsub2_then_hsub |
| 25939 | 0, // dsub2_then_ssub |
| 25940 | 0, // qsub1_then_bsub |
| 25941 | 0, // qsub1_then_dsub |
| 25942 | 0, // qsub1_then_hsub |
| 25943 | 0, // qsub1_then_ssub |
| 25944 | 0, // qsub3_then_bsub |
| 25945 | 0, // qsub3_then_dsub |
| 25946 | 0, // qsub3_then_hsub |
| 25947 | 0, // qsub3_then_ssub |
| 25948 | 0, // qsub2_then_bsub |
| 25949 | 0, // qsub2_then_dsub |
| 25950 | 0, // qsub2_then_hsub |
| 25951 | 0, // qsub2_then_ssub |
| 25952 | 0, // x8sub_7_then_sub_32 |
| 25953 | 0, // x8sub_6_then_sub_32 |
| 25954 | 0, // x8sub_5_then_sub_32 |
| 25955 | 0, // x8sub_4_then_sub_32 |
| 25956 | 0, // x8sub_3_then_sub_32 |
| 25957 | 0, // x8sub_2_then_sub_32 |
| 25958 | 0, // x8sub_1_then_sub_32 |
| 25959 | 0, // subo64_then_sub_32 |
| 25960 | 0, // zsub1_then_bsub |
| 25961 | 0, // zsub1_then_dsub |
| 25962 | 0, // zsub1_then_hsub |
| 25963 | 0, // zsub1_then_ssub |
| 25964 | 0, // zsub1_then_zsub |
| 25965 | 0, // zsub1_then_zsub_hi |
| 25966 | 0, // zsub3_then_bsub |
| 25967 | 0, // zsub3_then_dsub |
| 25968 | 0, // zsub3_then_hsub |
| 25969 | 0, // zsub3_then_ssub |
| 25970 | 0, // zsub3_then_zsub |
| 25971 | 0, // zsub3_then_zsub_hi |
| 25972 | 0, // zsub2_then_bsub |
| 25973 | 0, // zsub2_then_dsub |
| 25974 | 0, // zsub2_then_hsub |
| 25975 | 0, // zsub2_then_ssub |
| 25976 | 0, // zsub2_then_zsub |
| 25977 | 0, // zsub2_then_zsub_hi |
| 25978 | 0, // dsub0_dsub1 |
| 25979 | 0, // dsub0_dsub1_dsub2 |
| 25980 | 0, // dsub1_dsub2 |
| 25981 | 0, // dsub1_dsub2_dsub3 |
| 25982 | 0, // dsub2_dsub3 |
| 25983 | 0, // dsub_qsub1_then_dsub |
| 25984 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25985 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 25986 | 0, // qsub0_qsub1 |
| 25987 | 0, // qsub0_qsub1_qsub2 |
| 25988 | 0, // qsub1_qsub2 |
| 25989 | 0, // qsub1_qsub2_qsub3 |
| 25990 | 0, // qsub2_qsub3 |
| 25991 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 25992 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 25993 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 25994 | 0, // sub_32_x8sub_1_then_sub_32 |
| 25995 | 0, // x8sub_0_x8sub_1 |
| 25996 | 0, // x8sub_2_x8sub_3 |
| 25997 | 0, // x8sub_4_x8sub_5 |
| 25998 | 0, // x8sub_6_x8sub_7 |
| 25999 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26000 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26001 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26002 | 0, // sub_32_subo64_then_sub_32 |
| 26003 | 0, // dsub_zsub1_then_dsub |
| 26004 | 0, // zsub_zsub1_then_zsub |
| 26005 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26006 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26007 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26008 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26009 | 0, // zsub0_zsub1 |
| 26010 | 0, // zsub0_zsub1_zsub2 |
| 26011 | 0, // zsub1_zsub2 |
| 26012 | 0, // zsub1_zsub2_zsub3 |
| 26013 | 0, // zsub2_zsub3 |
| 26014 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26015 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26016 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26017 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26018 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26019 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26020 | }, |
| 26021 | { // ZPR_4b |
| 26022 | 104, // bsub -> ZPR_4b |
| 26023 | 104, // dsub -> ZPR_4b |
| 26024 | 0, // dsub0 |
| 26025 | 0, // dsub1 |
| 26026 | 0, // dsub2 |
| 26027 | 0, // dsub3 |
| 26028 | 104, // hsub -> ZPR_4b |
| 26029 | 0, // qhisub |
| 26030 | 0, // qsub |
| 26031 | 0, // qsub0 |
| 26032 | 0, // qsub1 |
| 26033 | 0, // qsub2 |
| 26034 | 0, // qsub3 |
| 26035 | 104, // ssub -> ZPR_4b |
| 26036 | 0, // sub_32 |
| 26037 | 0, // sube32 |
| 26038 | 0, // sube64 |
| 26039 | 0, // subo32 |
| 26040 | 0, // subo64 |
| 26041 | 0, // x8sub_0 |
| 26042 | 0, // x8sub_1 |
| 26043 | 0, // x8sub_2 |
| 26044 | 0, // x8sub_3 |
| 26045 | 0, // x8sub_4 |
| 26046 | 0, // x8sub_5 |
| 26047 | 0, // x8sub_6 |
| 26048 | 0, // x8sub_7 |
| 26049 | 104, // zsub -> ZPR_4b |
| 26050 | 0, // zsub0 |
| 26051 | 0, // zsub1 |
| 26052 | 0, // zsub2 |
| 26053 | 0, // zsub3 |
| 26054 | 104, // zsub_hi -> ZPR_4b |
| 26055 | 0, // dsub1_then_bsub |
| 26056 | 0, // dsub1_then_hsub |
| 26057 | 0, // dsub1_then_ssub |
| 26058 | 0, // dsub3_then_bsub |
| 26059 | 0, // dsub3_then_hsub |
| 26060 | 0, // dsub3_then_ssub |
| 26061 | 0, // dsub2_then_bsub |
| 26062 | 0, // dsub2_then_hsub |
| 26063 | 0, // dsub2_then_ssub |
| 26064 | 0, // qsub1_then_bsub |
| 26065 | 0, // qsub1_then_dsub |
| 26066 | 0, // qsub1_then_hsub |
| 26067 | 0, // qsub1_then_ssub |
| 26068 | 0, // qsub3_then_bsub |
| 26069 | 0, // qsub3_then_dsub |
| 26070 | 0, // qsub3_then_hsub |
| 26071 | 0, // qsub3_then_ssub |
| 26072 | 0, // qsub2_then_bsub |
| 26073 | 0, // qsub2_then_dsub |
| 26074 | 0, // qsub2_then_hsub |
| 26075 | 0, // qsub2_then_ssub |
| 26076 | 0, // x8sub_7_then_sub_32 |
| 26077 | 0, // x8sub_6_then_sub_32 |
| 26078 | 0, // x8sub_5_then_sub_32 |
| 26079 | 0, // x8sub_4_then_sub_32 |
| 26080 | 0, // x8sub_3_then_sub_32 |
| 26081 | 0, // x8sub_2_then_sub_32 |
| 26082 | 0, // x8sub_1_then_sub_32 |
| 26083 | 0, // subo64_then_sub_32 |
| 26084 | 0, // zsub1_then_bsub |
| 26085 | 0, // zsub1_then_dsub |
| 26086 | 0, // zsub1_then_hsub |
| 26087 | 0, // zsub1_then_ssub |
| 26088 | 0, // zsub1_then_zsub |
| 26089 | 0, // zsub1_then_zsub_hi |
| 26090 | 0, // zsub3_then_bsub |
| 26091 | 0, // zsub3_then_dsub |
| 26092 | 0, // zsub3_then_hsub |
| 26093 | 0, // zsub3_then_ssub |
| 26094 | 0, // zsub3_then_zsub |
| 26095 | 0, // zsub3_then_zsub_hi |
| 26096 | 0, // zsub2_then_bsub |
| 26097 | 0, // zsub2_then_dsub |
| 26098 | 0, // zsub2_then_hsub |
| 26099 | 0, // zsub2_then_ssub |
| 26100 | 0, // zsub2_then_zsub |
| 26101 | 0, // zsub2_then_zsub_hi |
| 26102 | 0, // dsub0_dsub1 |
| 26103 | 0, // dsub0_dsub1_dsub2 |
| 26104 | 0, // dsub1_dsub2 |
| 26105 | 0, // dsub1_dsub2_dsub3 |
| 26106 | 0, // dsub2_dsub3 |
| 26107 | 0, // dsub_qsub1_then_dsub |
| 26108 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26109 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26110 | 0, // qsub0_qsub1 |
| 26111 | 0, // qsub0_qsub1_qsub2 |
| 26112 | 0, // qsub1_qsub2 |
| 26113 | 0, // qsub1_qsub2_qsub3 |
| 26114 | 0, // qsub2_qsub3 |
| 26115 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26116 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26117 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26118 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26119 | 0, // x8sub_0_x8sub_1 |
| 26120 | 0, // x8sub_2_x8sub_3 |
| 26121 | 0, // x8sub_4_x8sub_5 |
| 26122 | 0, // x8sub_6_x8sub_7 |
| 26123 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26124 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26125 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26126 | 0, // sub_32_subo64_then_sub_32 |
| 26127 | 0, // dsub_zsub1_then_dsub |
| 26128 | 0, // zsub_zsub1_then_zsub |
| 26129 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26130 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26131 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26132 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26133 | 0, // zsub0_zsub1 |
| 26134 | 0, // zsub0_zsub1_zsub2 |
| 26135 | 0, // zsub1_zsub2 |
| 26136 | 0, // zsub1_zsub2_zsub3 |
| 26137 | 0, // zsub2_zsub3 |
| 26138 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26139 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26140 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26141 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26142 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26143 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26144 | }, |
| 26145 | { // ZPR_3b |
| 26146 | 105, // bsub -> ZPR_3b |
| 26147 | 105, // dsub -> ZPR_3b |
| 26148 | 0, // dsub0 |
| 26149 | 0, // dsub1 |
| 26150 | 0, // dsub2 |
| 26151 | 0, // dsub3 |
| 26152 | 105, // hsub -> ZPR_3b |
| 26153 | 0, // qhisub |
| 26154 | 0, // qsub |
| 26155 | 0, // qsub0 |
| 26156 | 0, // qsub1 |
| 26157 | 0, // qsub2 |
| 26158 | 0, // qsub3 |
| 26159 | 105, // ssub -> ZPR_3b |
| 26160 | 0, // sub_32 |
| 26161 | 0, // sube32 |
| 26162 | 0, // sube64 |
| 26163 | 0, // subo32 |
| 26164 | 0, // subo64 |
| 26165 | 0, // x8sub_0 |
| 26166 | 0, // x8sub_1 |
| 26167 | 0, // x8sub_2 |
| 26168 | 0, // x8sub_3 |
| 26169 | 0, // x8sub_4 |
| 26170 | 0, // x8sub_5 |
| 26171 | 0, // x8sub_6 |
| 26172 | 0, // x8sub_7 |
| 26173 | 105, // zsub -> ZPR_3b |
| 26174 | 0, // zsub0 |
| 26175 | 0, // zsub1 |
| 26176 | 0, // zsub2 |
| 26177 | 0, // zsub3 |
| 26178 | 105, // zsub_hi -> ZPR_3b |
| 26179 | 0, // dsub1_then_bsub |
| 26180 | 0, // dsub1_then_hsub |
| 26181 | 0, // dsub1_then_ssub |
| 26182 | 0, // dsub3_then_bsub |
| 26183 | 0, // dsub3_then_hsub |
| 26184 | 0, // dsub3_then_ssub |
| 26185 | 0, // dsub2_then_bsub |
| 26186 | 0, // dsub2_then_hsub |
| 26187 | 0, // dsub2_then_ssub |
| 26188 | 0, // qsub1_then_bsub |
| 26189 | 0, // qsub1_then_dsub |
| 26190 | 0, // qsub1_then_hsub |
| 26191 | 0, // qsub1_then_ssub |
| 26192 | 0, // qsub3_then_bsub |
| 26193 | 0, // qsub3_then_dsub |
| 26194 | 0, // qsub3_then_hsub |
| 26195 | 0, // qsub3_then_ssub |
| 26196 | 0, // qsub2_then_bsub |
| 26197 | 0, // qsub2_then_dsub |
| 26198 | 0, // qsub2_then_hsub |
| 26199 | 0, // qsub2_then_ssub |
| 26200 | 0, // x8sub_7_then_sub_32 |
| 26201 | 0, // x8sub_6_then_sub_32 |
| 26202 | 0, // x8sub_5_then_sub_32 |
| 26203 | 0, // x8sub_4_then_sub_32 |
| 26204 | 0, // x8sub_3_then_sub_32 |
| 26205 | 0, // x8sub_2_then_sub_32 |
| 26206 | 0, // x8sub_1_then_sub_32 |
| 26207 | 0, // subo64_then_sub_32 |
| 26208 | 0, // zsub1_then_bsub |
| 26209 | 0, // zsub1_then_dsub |
| 26210 | 0, // zsub1_then_hsub |
| 26211 | 0, // zsub1_then_ssub |
| 26212 | 0, // zsub1_then_zsub |
| 26213 | 0, // zsub1_then_zsub_hi |
| 26214 | 0, // zsub3_then_bsub |
| 26215 | 0, // zsub3_then_dsub |
| 26216 | 0, // zsub3_then_hsub |
| 26217 | 0, // zsub3_then_ssub |
| 26218 | 0, // zsub3_then_zsub |
| 26219 | 0, // zsub3_then_zsub_hi |
| 26220 | 0, // zsub2_then_bsub |
| 26221 | 0, // zsub2_then_dsub |
| 26222 | 0, // zsub2_then_hsub |
| 26223 | 0, // zsub2_then_ssub |
| 26224 | 0, // zsub2_then_zsub |
| 26225 | 0, // zsub2_then_zsub_hi |
| 26226 | 0, // dsub0_dsub1 |
| 26227 | 0, // dsub0_dsub1_dsub2 |
| 26228 | 0, // dsub1_dsub2 |
| 26229 | 0, // dsub1_dsub2_dsub3 |
| 26230 | 0, // dsub2_dsub3 |
| 26231 | 0, // dsub_qsub1_then_dsub |
| 26232 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26233 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26234 | 0, // qsub0_qsub1 |
| 26235 | 0, // qsub0_qsub1_qsub2 |
| 26236 | 0, // qsub1_qsub2 |
| 26237 | 0, // qsub1_qsub2_qsub3 |
| 26238 | 0, // qsub2_qsub3 |
| 26239 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26240 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26241 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26242 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26243 | 0, // x8sub_0_x8sub_1 |
| 26244 | 0, // x8sub_2_x8sub_3 |
| 26245 | 0, // x8sub_4_x8sub_5 |
| 26246 | 0, // x8sub_6_x8sub_7 |
| 26247 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26248 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26249 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26250 | 0, // sub_32_subo64_then_sub_32 |
| 26251 | 0, // dsub_zsub1_then_dsub |
| 26252 | 0, // zsub_zsub1_then_zsub |
| 26253 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26254 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26255 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26256 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26257 | 0, // zsub0_zsub1 |
| 26258 | 0, // zsub0_zsub1_zsub2 |
| 26259 | 0, // zsub1_zsub2 |
| 26260 | 0, // zsub1_zsub2_zsub3 |
| 26261 | 0, // zsub2_zsub3 |
| 26262 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26263 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26264 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26265 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26266 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26267 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26268 | }, |
| 26269 | { // DDD |
| 26270 | 106, // bsub -> DDD |
| 26271 | 0, // dsub |
| 26272 | 106, // dsub0 -> DDD |
| 26273 | 106, // dsub1 -> DDD |
| 26274 | 106, // dsub2 -> DDD |
| 26275 | 0, // dsub3 |
| 26276 | 106, // hsub -> DDD |
| 26277 | 0, // qhisub |
| 26278 | 0, // qsub |
| 26279 | 0, // qsub0 |
| 26280 | 0, // qsub1 |
| 26281 | 0, // qsub2 |
| 26282 | 0, // qsub3 |
| 26283 | 106, // ssub -> DDD |
| 26284 | 0, // sub_32 |
| 26285 | 0, // sube32 |
| 26286 | 0, // sube64 |
| 26287 | 0, // subo32 |
| 26288 | 0, // subo64 |
| 26289 | 0, // x8sub_0 |
| 26290 | 0, // x8sub_1 |
| 26291 | 0, // x8sub_2 |
| 26292 | 0, // x8sub_3 |
| 26293 | 0, // x8sub_4 |
| 26294 | 0, // x8sub_5 |
| 26295 | 0, // x8sub_6 |
| 26296 | 0, // x8sub_7 |
| 26297 | 0, // zsub |
| 26298 | 0, // zsub0 |
| 26299 | 0, // zsub1 |
| 26300 | 0, // zsub2 |
| 26301 | 0, // zsub3 |
| 26302 | 0, // zsub_hi |
| 26303 | 106, // dsub1_then_bsub -> DDD |
| 26304 | 106, // dsub1_then_hsub -> DDD |
| 26305 | 106, // dsub1_then_ssub -> DDD |
| 26306 | 0, // dsub3_then_bsub |
| 26307 | 0, // dsub3_then_hsub |
| 26308 | 0, // dsub3_then_ssub |
| 26309 | 106, // dsub2_then_bsub -> DDD |
| 26310 | 106, // dsub2_then_hsub -> DDD |
| 26311 | 106, // dsub2_then_ssub -> DDD |
| 26312 | 0, // qsub1_then_bsub |
| 26313 | 0, // qsub1_then_dsub |
| 26314 | 0, // qsub1_then_hsub |
| 26315 | 0, // qsub1_then_ssub |
| 26316 | 0, // qsub3_then_bsub |
| 26317 | 0, // qsub3_then_dsub |
| 26318 | 0, // qsub3_then_hsub |
| 26319 | 0, // qsub3_then_ssub |
| 26320 | 0, // qsub2_then_bsub |
| 26321 | 0, // qsub2_then_dsub |
| 26322 | 0, // qsub2_then_hsub |
| 26323 | 0, // qsub2_then_ssub |
| 26324 | 0, // x8sub_7_then_sub_32 |
| 26325 | 0, // x8sub_6_then_sub_32 |
| 26326 | 0, // x8sub_5_then_sub_32 |
| 26327 | 0, // x8sub_4_then_sub_32 |
| 26328 | 0, // x8sub_3_then_sub_32 |
| 26329 | 0, // x8sub_2_then_sub_32 |
| 26330 | 0, // x8sub_1_then_sub_32 |
| 26331 | 0, // subo64_then_sub_32 |
| 26332 | 0, // zsub1_then_bsub |
| 26333 | 0, // zsub1_then_dsub |
| 26334 | 0, // zsub1_then_hsub |
| 26335 | 0, // zsub1_then_ssub |
| 26336 | 0, // zsub1_then_zsub |
| 26337 | 0, // zsub1_then_zsub_hi |
| 26338 | 0, // zsub3_then_bsub |
| 26339 | 0, // zsub3_then_dsub |
| 26340 | 0, // zsub3_then_hsub |
| 26341 | 0, // zsub3_then_ssub |
| 26342 | 0, // zsub3_then_zsub |
| 26343 | 0, // zsub3_then_zsub_hi |
| 26344 | 0, // zsub2_then_bsub |
| 26345 | 0, // zsub2_then_dsub |
| 26346 | 0, // zsub2_then_hsub |
| 26347 | 0, // zsub2_then_ssub |
| 26348 | 0, // zsub2_then_zsub |
| 26349 | 0, // zsub2_then_zsub_hi |
| 26350 | 106, // dsub0_dsub1 -> DDD |
| 26351 | 0, // dsub0_dsub1_dsub2 |
| 26352 | 106, // dsub1_dsub2 -> DDD |
| 26353 | 0, // dsub1_dsub2_dsub3 |
| 26354 | 0, // dsub2_dsub3 |
| 26355 | 0, // dsub_qsub1_then_dsub |
| 26356 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26357 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26358 | 0, // qsub0_qsub1 |
| 26359 | 0, // qsub0_qsub1_qsub2 |
| 26360 | 0, // qsub1_qsub2 |
| 26361 | 0, // qsub1_qsub2_qsub3 |
| 26362 | 0, // qsub2_qsub3 |
| 26363 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26364 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26365 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26366 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26367 | 0, // x8sub_0_x8sub_1 |
| 26368 | 0, // x8sub_2_x8sub_3 |
| 26369 | 0, // x8sub_4_x8sub_5 |
| 26370 | 0, // x8sub_6_x8sub_7 |
| 26371 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26372 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26373 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26374 | 0, // sub_32_subo64_then_sub_32 |
| 26375 | 0, // dsub_zsub1_then_dsub |
| 26376 | 0, // zsub_zsub1_then_zsub |
| 26377 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26378 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26379 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26380 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26381 | 0, // zsub0_zsub1 |
| 26382 | 0, // zsub0_zsub1_zsub2 |
| 26383 | 0, // zsub1_zsub2 |
| 26384 | 0, // zsub1_zsub2_zsub3 |
| 26385 | 0, // zsub2_zsub3 |
| 26386 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26387 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26388 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26389 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26390 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26391 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26392 | }, |
| 26393 | { // DDD_with_dsub0_in_FPR64_lo |
| 26394 | 107, // bsub -> DDD_with_dsub0_in_FPR64_lo |
| 26395 | 0, // dsub |
| 26396 | 107, // dsub0 -> DDD_with_dsub0_in_FPR64_lo |
| 26397 | 107, // dsub1 -> DDD_with_dsub0_in_FPR64_lo |
| 26398 | 107, // dsub2 -> DDD_with_dsub0_in_FPR64_lo |
| 26399 | 0, // dsub3 |
| 26400 | 107, // hsub -> DDD_with_dsub0_in_FPR64_lo |
| 26401 | 0, // qhisub |
| 26402 | 0, // qsub |
| 26403 | 0, // qsub0 |
| 26404 | 0, // qsub1 |
| 26405 | 0, // qsub2 |
| 26406 | 0, // qsub3 |
| 26407 | 107, // ssub -> DDD_with_dsub0_in_FPR64_lo |
| 26408 | 0, // sub_32 |
| 26409 | 0, // sube32 |
| 26410 | 0, // sube64 |
| 26411 | 0, // subo32 |
| 26412 | 0, // subo64 |
| 26413 | 0, // x8sub_0 |
| 26414 | 0, // x8sub_1 |
| 26415 | 0, // x8sub_2 |
| 26416 | 0, // x8sub_3 |
| 26417 | 0, // x8sub_4 |
| 26418 | 0, // x8sub_5 |
| 26419 | 0, // x8sub_6 |
| 26420 | 0, // x8sub_7 |
| 26421 | 0, // zsub |
| 26422 | 0, // zsub0 |
| 26423 | 0, // zsub1 |
| 26424 | 0, // zsub2 |
| 26425 | 0, // zsub3 |
| 26426 | 0, // zsub_hi |
| 26427 | 107, // dsub1_then_bsub -> DDD_with_dsub0_in_FPR64_lo |
| 26428 | 107, // dsub1_then_hsub -> DDD_with_dsub0_in_FPR64_lo |
| 26429 | 107, // dsub1_then_ssub -> DDD_with_dsub0_in_FPR64_lo |
| 26430 | 0, // dsub3_then_bsub |
| 26431 | 0, // dsub3_then_hsub |
| 26432 | 0, // dsub3_then_ssub |
| 26433 | 107, // dsub2_then_bsub -> DDD_with_dsub0_in_FPR64_lo |
| 26434 | 107, // dsub2_then_hsub -> DDD_with_dsub0_in_FPR64_lo |
| 26435 | 107, // dsub2_then_ssub -> DDD_with_dsub0_in_FPR64_lo |
| 26436 | 0, // qsub1_then_bsub |
| 26437 | 0, // qsub1_then_dsub |
| 26438 | 0, // qsub1_then_hsub |
| 26439 | 0, // qsub1_then_ssub |
| 26440 | 0, // qsub3_then_bsub |
| 26441 | 0, // qsub3_then_dsub |
| 26442 | 0, // qsub3_then_hsub |
| 26443 | 0, // qsub3_then_ssub |
| 26444 | 0, // qsub2_then_bsub |
| 26445 | 0, // qsub2_then_dsub |
| 26446 | 0, // qsub2_then_hsub |
| 26447 | 0, // qsub2_then_ssub |
| 26448 | 0, // x8sub_7_then_sub_32 |
| 26449 | 0, // x8sub_6_then_sub_32 |
| 26450 | 0, // x8sub_5_then_sub_32 |
| 26451 | 0, // x8sub_4_then_sub_32 |
| 26452 | 0, // x8sub_3_then_sub_32 |
| 26453 | 0, // x8sub_2_then_sub_32 |
| 26454 | 0, // x8sub_1_then_sub_32 |
| 26455 | 0, // subo64_then_sub_32 |
| 26456 | 0, // zsub1_then_bsub |
| 26457 | 0, // zsub1_then_dsub |
| 26458 | 0, // zsub1_then_hsub |
| 26459 | 0, // zsub1_then_ssub |
| 26460 | 0, // zsub1_then_zsub |
| 26461 | 0, // zsub1_then_zsub_hi |
| 26462 | 0, // zsub3_then_bsub |
| 26463 | 0, // zsub3_then_dsub |
| 26464 | 0, // zsub3_then_hsub |
| 26465 | 0, // zsub3_then_ssub |
| 26466 | 0, // zsub3_then_zsub |
| 26467 | 0, // zsub3_then_zsub_hi |
| 26468 | 0, // zsub2_then_bsub |
| 26469 | 0, // zsub2_then_dsub |
| 26470 | 0, // zsub2_then_hsub |
| 26471 | 0, // zsub2_then_ssub |
| 26472 | 0, // zsub2_then_zsub |
| 26473 | 0, // zsub2_then_zsub_hi |
| 26474 | 107, // dsub0_dsub1 -> DDD_with_dsub0_in_FPR64_lo |
| 26475 | 0, // dsub0_dsub1_dsub2 |
| 26476 | 107, // dsub1_dsub2 -> DDD_with_dsub0_in_FPR64_lo |
| 26477 | 0, // dsub1_dsub2_dsub3 |
| 26478 | 0, // dsub2_dsub3 |
| 26479 | 0, // dsub_qsub1_then_dsub |
| 26480 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26481 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26482 | 0, // qsub0_qsub1 |
| 26483 | 0, // qsub0_qsub1_qsub2 |
| 26484 | 0, // qsub1_qsub2 |
| 26485 | 0, // qsub1_qsub2_qsub3 |
| 26486 | 0, // qsub2_qsub3 |
| 26487 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26488 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26489 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26490 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26491 | 0, // x8sub_0_x8sub_1 |
| 26492 | 0, // x8sub_2_x8sub_3 |
| 26493 | 0, // x8sub_4_x8sub_5 |
| 26494 | 0, // x8sub_6_x8sub_7 |
| 26495 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26496 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26497 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26498 | 0, // sub_32_subo64_then_sub_32 |
| 26499 | 0, // dsub_zsub1_then_dsub |
| 26500 | 0, // zsub_zsub1_then_zsub |
| 26501 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26502 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26503 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26504 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26505 | 0, // zsub0_zsub1 |
| 26506 | 0, // zsub0_zsub1_zsub2 |
| 26507 | 0, // zsub1_zsub2 |
| 26508 | 0, // zsub1_zsub2_zsub3 |
| 26509 | 0, // zsub2_zsub3 |
| 26510 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26511 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26512 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26513 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26514 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26515 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26516 | }, |
| 26517 | { // DDD_with_dsub1_in_FPR64_lo |
| 26518 | 108, // bsub -> DDD_with_dsub1_in_FPR64_lo |
| 26519 | 0, // dsub |
| 26520 | 108, // dsub0 -> DDD_with_dsub1_in_FPR64_lo |
| 26521 | 108, // dsub1 -> DDD_with_dsub1_in_FPR64_lo |
| 26522 | 108, // dsub2 -> DDD_with_dsub1_in_FPR64_lo |
| 26523 | 0, // dsub3 |
| 26524 | 108, // hsub -> DDD_with_dsub1_in_FPR64_lo |
| 26525 | 0, // qhisub |
| 26526 | 0, // qsub |
| 26527 | 0, // qsub0 |
| 26528 | 0, // qsub1 |
| 26529 | 0, // qsub2 |
| 26530 | 0, // qsub3 |
| 26531 | 108, // ssub -> DDD_with_dsub1_in_FPR64_lo |
| 26532 | 0, // sub_32 |
| 26533 | 0, // sube32 |
| 26534 | 0, // sube64 |
| 26535 | 0, // subo32 |
| 26536 | 0, // subo64 |
| 26537 | 0, // x8sub_0 |
| 26538 | 0, // x8sub_1 |
| 26539 | 0, // x8sub_2 |
| 26540 | 0, // x8sub_3 |
| 26541 | 0, // x8sub_4 |
| 26542 | 0, // x8sub_5 |
| 26543 | 0, // x8sub_6 |
| 26544 | 0, // x8sub_7 |
| 26545 | 0, // zsub |
| 26546 | 0, // zsub0 |
| 26547 | 0, // zsub1 |
| 26548 | 0, // zsub2 |
| 26549 | 0, // zsub3 |
| 26550 | 0, // zsub_hi |
| 26551 | 108, // dsub1_then_bsub -> DDD_with_dsub1_in_FPR64_lo |
| 26552 | 108, // dsub1_then_hsub -> DDD_with_dsub1_in_FPR64_lo |
| 26553 | 108, // dsub1_then_ssub -> DDD_with_dsub1_in_FPR64_lo |
| 26554 | 0, // dsub3_then_bsub |
| 26555 | 0, // dsub3_then_hsub |
| 26556 | 0, // dsub3_then_ssub |
| 26557 | 108, // dsub2_then_bsub -> DDD_with_dsub1_in_FPR64_lo |
| 26558 | 108, // dsub2_then_hsub -> DDD_with_dsub1_in_FPR64_lo |
| 26559 | 108, // dsub2_then_ssub -> DDD_with_dsub1_in_FPR64_lo |
| 26560 | 0, // qsub1_then_bsub |
| 26561 | 0, // qsub1_then_dsub |
| 26562 | 0, // qsub1_then_hsub |
| 26563 | 0, // qsub1_then_ssub |
| 26564 | 0, // qsub3_then_bsub |
| 26565 | 0, // qsub3_then_dsub |
| 26566 | 0, // qsub3_then_hsub |
| 26567 | 0, // qsub3_then_ssub |
| 26568 | 0, // qsub2_then_bsub |
| 26569 | 0, // qsub2_then_dsub |
| 26570 | 0, // qsub2_then_hsub |
| 26571 | 0, // qsub2_then_ssub |
| 26572 | 0, // x8sub_7_then_sub_32 |
| 26573 | 0, // x8sub_6_then_sub_32 |
| 26574 | 0, // x8sub_5_then_sub_32 |
| 26575 | 0, // x8sub_4_then_sub_32 |
| 26576 | 0, // x8sub_3_then_sub_32 |
| 26577 | 0, // x8sub_2_then_sub_32 |
| 26578 | 0, // x8sub_1_then_sub_32 |
| 26579 | 0, // subo64_then_sub_32 |
| 26580 | 0, // zsub1_then_bsub |
| 26581 | 0, // zsub1_then_dsub |
| 26582 | 0, // zsub1_then_hsub |
| 26583 | 0, // zsub1_then_ssub |
| 26584 | 0, // zsub1_then_zsub |
| 26585 | 0, // zsub1_then_zsub_hi |
| 26586 | 0, // zsub3_then_bsub |
| 26587 | 0, // zsub3_then_dsub |
| 26588 | 0, // zsub3_then_hsub |
| 26589 | 0, // zsub3_then_ssub |
| 26590 | 0, // zsub3_then_zsub |
| 26591 | 0, // zsub3_then_zsub_hi |
| 26592 | 0, // zsub2_then_bsub |
| 26593 | 0, // zsub2_then_dsub |
| 26594 | 0, // zsub2_then_hsub |
| 26595 | 0, // zsub2_then_ssub |
| 26596 | 0, // zsub2_then_zsub |
| 26597 | 0, // zsub2_then_zsub_hi |
| 26598 | 108, // dsub0_dsub1 -> DDD_with_dsub1_in_FPR64_lo |
| 26599 | 0, // dsub0_dsub1_dsub2 |
| 26600 | 108, // dsub1_dsub2 -> DDD_with_dsub1_in_FPR64_lo |
| 26601 | 0, // dsub1_dsub2_dsub3 |
| 26602 | 0, // dsub2_dsub3 |
| 26603 | 0, // dsub_qsub1_then_dsub |
| 26604 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26605 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26606 | 0, // qsub0_qsub1 |
| 26607 | 0, // qsub0_qsub1_qsub2 |
| 26608 | 0, // qsub1_qsub2 |
| 26609 | 0, // qsub1_qsub2_qsub3 |
| 26610 | 0, // qsub2_qsub3 |
| 26611 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26612 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26613 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26614 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26615 | 0, // x8sub_0_x8sub_1 |
| 26616 | 0, // x8sub_2_x8sub_3 |
| 26617 | 0, // x8sub_4_x8sub_5 |
| 26618 | 0, // x8sub_6_x8sub_7 |
| 26619 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26620 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26621 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26622 | 0, // sub_32_subo64_then_sub_32 |
| 26623 | 0, // dsub_zsub1_then_dsub |
| 26624 | 0, // zsub_zsub1_then_zsub |
| 26625 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26626 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26627 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26628 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26629 | 0, // zsub0_zsub1 |
| 26630 | 0, // zsub0_zsub1_zsub2 |
| 26631 | 0, // zsub1_zsub2 |
| 26632 | 0, // zsub1_zsub2_zsub3 |
| 26633 | 0, // zsub2_zsub3 |
| 26634 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26635 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26636 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26637 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26638 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26639 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26640 | }, |
| 26641 | { // DDD_with_dsub2_in_FPR64_lo |
| 26642 | 109, // bsub -> DDD_with_dsub2_in_FPR64_lo |
| 26643 | 0, // dsub |
| 26644 | 109, // dsub0 -> DDD_with_dsub2_in_FPR64_lo |
| 26645 | 109, // dsub1 -> DDD_with_dsub2_in_FPR64_lo |
| 26646 | 109, // dsub2 -> DDD_with_dsub2_in_FPR64_lo |
| 26647 | 0, // dsub3 |
| 26648 | 109, // hsub -> DDD_with_dsub2_in_FPR64_lo |
| 26649 | 0, // qhisub |
| 26650 | 0, // qsub |
| 26651 | 0, // qsub0 |
| 26652 | 0, // qsub1 |
| 26653 | 0, // qsub2 |
| 26654 | 0, // qsub3 |
| 26655 | 109, // ssub -> DDD_with_dsub2_in_FPR64_lo |
| 26656 | 0, // sub_32 |
| 26657 | 0, // sube32 |
| 26658 | 0, // sube64 |
| 26659 | 0, // subo32 |
| 26660 | 0, // subo64 |
| 26661 | 0, // x8sub_0 |
| 26662 | 0, // x8sub_1 |
| 26663 | 0, // x8sub_2 |
| 26664 | 0, // x8sub_3 |
| 26665 | 0, // x8sub_4 |
| 26666 | 0, // x8sub_5 |
| 26667 | 0, // x8sub_6 |
| 26668 | 0, // x8sub_7 |
| 26669 | 0, // zsub |
| 26670 | 0, // zsub0 |
| 26671 | 0, // zsub1 |
| 26672 | 0, // zsub2 |
| 26673 | 0, // zsub3 |
| 26674 | 0, // zsub_hi |
| 26675 | 109, // dsub1_then_bsub -> DDD_with_dsub2_in_FPR64_lo |
| 26676 | 109, // dsub1_then_hsub -> DDD_with_dsub2_in_FPR64_lo |
| 26677 | 109, // dsub1_then_ssub -> DDD_with_dsub2_in_FPR64_lo |
| 26678 | 0, // dsub3_then_bsub |
| 26679 | 0, // dsub3_then_hsub |
| 26680 | 0, // dsub3_then_ssub |
| 26681 | 109, // dsub2_then_bsub -> DDD_with_dsub2_in_FPR64_lo |
| 26682 | 109, // dsub2_then_hsub -> DDD_with_dsub2_in_FPR64_lo |
| 26683 | 109, // dsub2_then_ssub -> DDD_with_dsub2_in_FPR64_lo |
| 26684 | 0, // qsub1_then_bsub |
| 26685 | 0, // qsub1_then_dsub |
| 26686 | 0, // qsub1_then_hsub |
| 26687 | 0, // qsub1_then_ssub |
| 26688 | 0, // qsub3_then_bsub |
| 26689 | 0, // qsub3_then_dsub |
| 26690 | 0, // qsub3_then_hsub |
| 26691 | 0, // qsub3_then_ssub |
| 26692 | 0, // qsub2_then_bsub |
| 26693 | 0, // qsub2_then_dsub |
| 26694 | 0, // qsub2_then_hsub |
| 26695 | 0, // qsub2_then_ssub |
| 26696 | 0, // x8sub_7_then_sub_32 |
| 26697 | 0, // x8sub_6_then_sub_32 |
| 26698 | 0, // x8sub_5_then_sub_32 |
| 26699 | 0, // x8sub_4_then_sub_32 |
| 26700 | 0, // x8sub_3_then_sub_32 |
| 26701 | 0, // x8sub_2_then_sub_32 |
| 26702 | 0, // x8sub_1_then_sub_32 |
| 26703 | 0, // subo64_then_sub_32 |
| 26704 | 0, // zsub1_then_bsub |
| 26705 | 0, // zsub1_then_dsub |
| 26706 | 0, // zsub1_then_hsub |
| 26707 | 0, // zsub1_then_ssub |
| 26708 | 0, // zsub1_then_zsub |
| 26709 | 0, // zsub1_then_zsub_hi |
| 26710 | 0, // zsub3_then_bsub |
| 26711 | 0, // zsub3_then_dsub |
| 26712 | 0, // zsub3_then_hsub |
| 26713 | 0, // zsub3_then_ssub |
| 26714 | 0, // zsub3_then_zsub |
| 26715 | 0, // zsub3_then_zsub_hi |
| 26716 | 0, // zsub2_then_bsub |
| 26717 | 0, // zsub2_then_dsub |
| 26718 | 0, // zsub2_then_hsub |
| 26719 | 0, // zsub2_then_ssub |
| 26720 | 0, // zsub2_then_zsub |
| 26721 | 0, // zsub2_then_zsub_hi |
| 26722 | 109, // dsub0_dsub1 -> DDD_with_dsub2_in_FPR64_lo |
| 26723 | 0, // dsub0_dsub1_dsub2 |
| 26724 | 109, // dsub1_dsub2 -> DDD_with_dsub2_in_FPR64_lo |
| 26725 | 0, // dsub1_dsub2_dsub3 |
| 26726 | 0, // dsub2_dsub3 |
| 26727 | 0, // dsub_qsub1_then_dsub |
| 26728 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26729 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26730 | 0, // qsub0_qsub1 |
| 26731 | 0, // qsub0_qsub1_qsub2 |
| 26732 | 0, // qsub1_qsub2 |
| 26733 | 0, // qsub1_qsub2_qsub3 |
| 26734 | 0, // qsub2_qsub3 |
| 26735 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26736 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26737 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26738 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26739 | 0, // x8sub_0_x8sub_1 |
| 26740 | 0, // x8sub_2_x8sub_3 |
| 26741 | 0, // x8sub_4_x8sub_5 |
| 26742 | 0, // x8sub_6_x8sub_7 |
| 26743 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26744 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26745 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26746 | 0, // sub_32_subo64_then_sub_32 |
| 26747 | 0, // dsub_zsub1_then_dsub |
| 26748 | 0, // zsub_zsub1_then_zsub |
| 26749 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26750 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26751 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26752 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26753 | 0, // zsub0_zsub1 |
| 26754 | 0, // zsub0_zsub1_zsub2 |
| 26755 | 0, // zsub1_zsub2 |
| 26756 | 0, // zsub1_zsub2_zsub3 |
| 26757 | 0, // zsub2_zsub3 |
| 26758 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26759 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26760 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26761 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26762 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26763 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26764 | }, |
| 26765 | { // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26766 | 110, // bsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26767 | 0, // dsub |
| 26768 | 110, // dsub0 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26769 | 110, // dsub1 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26770 | 110, // dsub2 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26771 | 0, // dsub3 |
| 26772 | 110, // hsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26773 | 0, // qhisub |
| 26774 | 0, // qsub |
| 26775 | 0, // qsub0 |
| 26776 | 0, // qsub1 |
| 26777 | 0, // qsub2 |
| 26778 | 0, // qsub3 |
| 26779 | 110, // ssub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26780 | 0, // sub_32 |
| 26781 | 0, // sube32 |
| 26782 | 0, // sube64 |
| 26783 | 0, // subo32 |
| 26784 | 0, // subo64 |
| 26785 | 0, // x8sub_0 |
| 26786 | 0, // x8sub_1 |
| 26787 | 0, // x8sub_2 |
| 26788 | 0, // x8sub_3 |
| 26789 | 0, // x8sub_4 |
| 26790 | 0, // x8sub_5 |
| 26791 | 0, // x8sub_6 |
| 26792 | 0, // x8sub_7 |
| 26793 | 0, // zsub |
| 26794 | 0, // zsub0 |
| 26795 | 0, // zsub1 |
| 26796 | 0, // zsub2 |
| 26797 | 0, // zsub3 |
| 26798 | 0, // zsub_hi |
| 26799 | 110, // dsub1_then_bsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26800 | 110, // dsub1_then_hsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26801 | 110, // dsub1_then_ssub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26802 | 0, // dsub3_then_bsub |
| 26803 | 0, // dsub3_then_hsub |
| 26804 | 0, // dsub3_then_ssub |
| 26805 | 110, // dsub2_then_bsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26806 | 110, // dsub2_then_hsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26807 | 110, // dsub2_then_ssub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26808 | 0, // qsub1_then_bsub |
| 26809 | 0, // qsub1_then_dsub |
| 26810 | 0, // qsub1_then_hsub |
| 26811 | 0, // qsub1_then_ssub |
| 26812 | 0, // qsub3_then_bsub |
| 26813 | 0, // qsub3_then_dsub |
| 26814 | 0, // qsub3_then_hsub |
| 26815 | 0, // qsub3_then_ssub |
| 26816 | 0, // qsub2_then_bsub |
| 26817 | 0, // qsub2_then_dsub |
| 26818 | 0, // qsub2_then_hsub |
| 26819 | 0, // qsub2_then_ssub |
| 26820 | 0, // x8sub_7_then_sub_32 |
| 26821 | 0, // x8sub_6_then_sub_32 |
| 26822 | 0, // x8sub_5_then_sub_32 |
| 26823 | 0, // x8sub_4_then_sub_32 |
| 26824 | 0, // x8sub_3_then_sub_32 |
| 26825 | 0, // x8sub_2_then_sub_32 |
| 26826 | 0, // x8sub_1_then_sub_32 |
| 26827 | 0, // subo64_then_sub_32 |
| 26828 | 0, // zsub1_then_bsub |
| 26829 | 0, // zsub1_then_dsub |
| 26830 | 0, // zsub1_then_hsub |
| 26831 | 0, // zsub1_then_ssub |
| 26832 | 0, // zsub1_then_zsub |
| 26833 | 0, // zsub1_then_zsub_hi |
| 26834 | 0, // zsub3_then_bsub |
| 26835 | 0, // zsub3_then_dsub |
| 26836 | 0, // zsub3_then_hsub |
| 26837 | 0, // zsub3_then_ssub |
| 26838 | 0, // zsub3_then_zsub |
| 26839 | 0, // zsub3_then_zsub_hi |
| 26840 | 0, // zsub2_then_bsub |
| 26841 | 0, // zsub2_then_dsub |
| 26842 | 0, // zsub2_then_hsub |
| 26843 | 0, // zsub2_then_ssub |
| 26844 | 0, // zsub2_then_zsub |
| 26845 | 0, // zsub2_then_zsub_hi |
| 26846 | 110, // dsub0_dsub1 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26847 | 0, // dsub0_dsub1_dsub2 |
| 26848 | 110, // dsub1_dsub2 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 26849 | 0, // dsub1_dsub2_dsub3 |
| 26850 | 0, // dsub2_dsub3 |
| 26851 | 0, // dsub_qsub1_then_dsub |
| 26852 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26853 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26854 | 0, // qsub0_qsub1 |
| 26855 | 0, // qsub0_qsub1_qsub2 |
| 26856 | 0, // qsub1_qsub2 |
| 26857 | 0, // qsub1_qsub2_qsub3 |
| 26858 | 0, // qsub2_qsub3 |
| 26859 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26860 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26861 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26862 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26863 | 0, // x8sub_0_x8sub_1 |
| 26864 | 0, // x8sub_2_x8sub_3 |
| 26865 | 0, // x8sub_4_x8sub_5 |
| 26866 | 0, // x8sub_6_x8sub_7 |
| 26867 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26868 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26869 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26870 | 0, // sub_32_subo64_then_sub_32 |
| 26871 | 0, // dsub_zsub1_then_dsub |
| 26872 | 0, // zsub_zsub1_then_zsub |
| 26873 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26874 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26875 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26876 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 26877 | 0, // zsub0_zsub1 |
| 26878 | 0, // zsub0_zsub1_zsub2 |
| 26879 | 0, // zsub1_zsub2 |
| 26880 | 0, // zsub1_zsub2_zsub3 |
| 26881 | 0, // zsub2_zsub3 |
| 26882 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 26883 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26884 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 26885 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 26886 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 26887 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 26888 | }, |
| 26889 | { // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26890 | 111, // bsub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26891 | 0, // dsub |
| 26892 | 111, // dsub0 -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26893 | 111, // dsub1 -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26894 | 111, // dsub2 -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26895 | 0, // dsub3 |
| 26896 | 111, // hsub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26897 | 0, // qhisub |
| 26898 | 0, // qsub |
| 26899 | 0, // qsub0 |
| 26900 | 0, // qsub1 |
| 26901 | 0, // qsub2 |
| 26902 | 0, // qsub3 |
| 26903 | 111, // ssub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26904 | 0, // sub_32 |
| 26905 | 0, // sube32 |
| 26906 | 0, // sube64 |
| 26907 | 0, // subo32 |
| 26908 | 0, // subo64 |
| 26909 | 0, // x8sub_0 |
| 26910 | 0, // x8sub_1 |
| 26911 | 0, // x8sub_2 |
| 26912 | 0, // x8sub_3 |
| 26913 | 0, // x8sub_4 |
| 26914 | 0, // x8sub_5 |
| 26915 | 0, // x8sub_6 |
| 26916 | 0, // x8sub_7 |
| 26917 | 0, // zsub |
| 26918 | 0, // zsub0 |
| 26919 | 0, // zsub1 |
| 26920 | 0, // zsub2 |
| 26921 | 0, // zsub3 |
| 26922 | 0, // zsub_hi |
| 26923 | 111, // dsub1_then_bsub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26924 | 111, // dsub1_then_hsub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26925 | 111, // dsub1_then_ssub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26926 | 0, // dsub3_then_bsub |
| 26927 | 0, // dsub3_then_hsub |
| 26928 | 0, // dsub3_then_ssub |
| 26929 | 111, // dsub2_then_bsub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26930 | 111, // dsub2_then_hsub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26931 | 111, // dsub2_then_ssub -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26932 | 0, // qsub1_then_bsub |
| 26933 | 0, // qsub1_then_dsub |
| 26934 | 0, // qsub1_then_hsub |
| 26935 | 0, // qsub1_then_ssub |
| 26936 | 0, // qsub3_then_bsub |
| 26937 | 0, // qsub3_then_dsub |
| 26938 | 0, // qsub3_then_hsub |
| 26939 | 0, // qsub3_then_ssub |
| 26940 | 0, // qsub2_then_bsub |
| 26941 | 0, // qsub2_then_dsub |
| 26942 | 0, // qsub2_then_hsub |
| 26943 | 0, // qsub2_then_ssub |
| 26944 | 0, // x8sub_7_then_sub_32 |
| 26945 | 0, // x8sub_6_then_sub_32 |
| 26946 | 0, // x8sub_5_then_sub_32 |
| 26947 | 0, // x8sub_4_then_sub_32 |
| 26948 | 0, // x8sub_3_then_sub_32 |
| 26949 | 0, // x8sub_2_then_sub_32 |
| 26950 | 0, // x8sub_1_then_sub_32 |
| 26951 | 0, // subo64_then_sub_32 |
| 26952 | 0, // zsub1_then_bsub |
| 26953 | 0, // zsub1_then_dsub |
| 26954 | 0, // zsub1_then_hsub |
| 26955 | 0, // zsub1_then_ssub |
| 26956 | 0, // zsub1_then_zsub |
| 26957 | 0, // zsub1_then_zsub_hi |
| 26958 | 0, // zsub3_then_bsub |
| 26959 | 0, // zsub3_then_dsub |
| 26960 | 0, // zsub3_then_hsub |
| 26961 | 0, // zsub3_then_ssub |
| 26962 | 0, // zsub3_then_zsub |
| 26963 | 0, // zsub3_then_zsub_hi |
| 26964 | 0, // zsub2_then_bsub |
| 26965 | 0, // zsub2_then_dsub |
| 26966 | 0, // zsub2_then_hsub |
| 26967 | 0, // zsub2_then_ssub |
| 26968 | 0, // zsub2_then_zsub |
| 26969 | 0, // zsub2_then_zsub_hi |
| 26970 | 111, // dsub0_dsub1 -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26971 | 0, // dsub0_dsub1_dsub2 |
| 26972 | 111, // dsub1_dsub2 -> DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 26973 | 0, // dsub1_dsub2_dsub3 |
| 26974 | 0, // dsub2_dsub3 |
| 26975 | 0, // dsub_qsub1_then_dsub |
| 26976 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26977 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 26978 | 0, // qsub0_qsub1 |
| 26979 | 0, // qsub0_qsub1_qsub2 |
| 26980 | 0, // qsub1_qsub2 |
| 26981 | 0, // qsub1_qsub2_qsub3 |
| 26982 | 0, // qsub2_qsub3 |
| 26983 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 26984 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 26985 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 26986 | 0, // sub_32_x8sub_1_then_sub_32 |
| 26987 | 0, // x8sub_0_x8sub_1 |
| 26988 | 0, // x8sub_2_x8sub_3 |
| 26989 | 0, // x8sub_4_x8sub_5 |
| 26990 | 0, // x8sub_6_x8sub_7 |
| 26991 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 26992 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 26993 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 26994 | 0, // sub_32_subo64_then_sub_32 |
| 26995 | 0, // dsub_zsub1_then_dsub |
| 26996 | 0, // zsub_zsub1_then_zsub |
| 26997 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 26998 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 26999 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27000 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27001 | 0, // zsub0_zsub1 |
| 27002 | 0, // zsub0_zsub1_zsub2 |
| 27003 | 0, // zsub1_zsub2 |
| 27004 | 0, // zsub1_zsub2_zsub3 |
| 27005 | 0, // zsub2_zsub3 |
| 27006 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27007 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27008 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27009 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27010 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27011 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27012 | }, |
| 27013 | { // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27014 | 112, // bsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27015 | 0, // dsub |
| 27016 | 112, // dsub0 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27017 | 112, // dsub1 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27018 | 112, // dsub2 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27019 | 0, // dsub3 |
| 27020 | 112, // hsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27021 | 0, // qhisub |
| 27022 | 0, // qsub |
| 27023 | 0, // qsub0 |
| 27024 | 0, // qsub1 |
| 27025 | 0, // qsub2 |
| 27026 | 0, // qsub3 |
| 27027 | 112, // ssub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27028 | 0, // sub_32 |
| 27029 | 0, // sube32 |
| 27030 | 0, // sube64 |
| 27031 | 0, // subo32 |
| 27032 | 0, // subo64 |
| 27033 | 0, // x8sub_0 |
| 27034 | 0, // x8sub_1 |
| 27035 | 0, // x8sub_2 |
| 27036 | 0, // x8sub_3 |
| 27037 | 0, // x8sub_4 |
| 27038 | 0, // x8sub_5 |
| 27039 | 0, // x8sub_6 |
| 27040 | 0, // x8sub_7 |
| 27041 | 0, // zsub |
| 27042 | 0, // zsub0 |
| 27043 | 0, // zsub1 |
| 27044 | 0, // zsub2 |
| 27045 | 0, // zsub3 |
| 27046 | 0, // zsub_hi |
| 27047 | 112, // dsub1_then_bsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27048 | 112, // dsub1_then_hsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27049 | 112, // dsub1_then_ssub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27050 | 0, // dsub3_then_bsub |
| 27051 | 0, // dsub3_then_hsub |
| 27052 | 0, // dsub3_then_ssub |
| 27053 | 112, // dsub2_then_bsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27054 | 112, // dsub2_then_hsub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27055 | 112, // dsub2_then_ssub -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27056 | 0, // qsub1_then_bsub |
| 27057 | 0, // qsub1_then_dsub |
| 27058 | 0, // qsub1_then_hsub |
| 27059 | 0, // qsub1_then_ssub |
| 27060 | 0, // qsub3_then_bsub |
| 27061 | 0, // qsub3_then_dsub |
| 27062 | 0, // qsub3_then_hsub |
| 27063 | 0, // qsub3_then_ssub |
| 27064 | 0, // qsub2_then_bsub |
| 27065 | 0, // qsub2_then_dsub |
| 27066 | 0, // qsub2_then_hsub |
| 27067 | 0, // qsub2_then_ssub |
| 27068 | 0, // x8sub_7_then_sub_32 |
| 27069 | 0, // x8sub_6_then_sub_32 |
| 27070 | 0, // x8sub_5_then_sub_32 |
| 27071 | 0, // x8sub_4_then_sub_32 |
| 27072 | 0, // x8sub_3_then_sub_32 |
| 27073 | 0, // x8sub_2_then_sub_32 |
| 27074 | 0, // x8sub_1_then_sub_32 |
| 27075 | 0, // subo64_then_sub_32 |
| 27076 | 0, // zsub1_then_bsub |
| 27077 | 0, // zsub1_then_dsub |
| 27078 | 0, // zsub1_then_hsub |
| 27079 | 0, // zsub1_then_ssub |
| 27080 | 0, // zsub1_then_zsub |
| 27081 | 0, // zsub1_then_zsub_hi |
| 27082 | 0, // zsub3_then_bsub |
| 27083 | 0, // zsub3_then_dsub |
| 27084 | 0, // zsub3_then_hsub |
| 27085 | 0, // zsub3_then_ssub |
| 27086 | 0, // zsub3_then_zsub |
| 27087 | 0, // zsub3_then_zsub_hi |
| 27088 | 0, // zsub2_then_bsub |
| 27089 | 0, // zsub2_then_dsub |
| 27090 | 0, // zsub2_then_hsub |
| 27091 | 0, // zsub2_then_ssub |
| 27092 | 0, // zsub2_then_zsub |
| 27093 | 0, // zsub2_then_zsub_hi |
| 27094 | 112, // dsub0_dsub1 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27095 | 0, // dsub0_dsub1_dsub2 |
| 27096 | 112, // dsub1_dsub2 -> DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 27097 | 0, // dsub1_dsub2_dsub3 |
| 27098 | 0, // dsub2_dsub3 |
| 27099 | 0, // dsub_qsub1_then_dsub |
| 27100 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27101 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27102 | 0, // qsub0_qsub1 |
| 27103 | 0, // qsub0_qsub1_qsub2 |
| 27104 | 0, // qsub1_qsub2 |
| 27105 | 0, // qsub1_qsub2_qsub3 |
| 27106 | 0, // qsub2_qsub3 |
| 27107 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27108 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27109 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27110 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27111 | 0, // x8sub_0_x8sub_1 |
| 27112 | 0, // x8sub_2_x8sub_3 |
| 27113 | 0, // x8sub_4_x8sub_5 |
| 27114 | 0, // x8sub_6_x8sub_7 |
| 27115 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27116 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27117 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27118 | 0, // sub_32_subo64_then_sub_32 |
| 27119 | 0, // dsub_zsub1_then_dsub |
| 27120 | 0, // zsub_zsub1_then_zsub |
| 27121 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27122 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27123 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27124 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27125 | 0, // zsub0_zsub1 |
| 27126 | 0, // zsub0_zsub1_zsub2 |
| 27127 | 0, // zsub1_zsub2 |
| 27128 | 0, // zsub1_zsub2_zsub3 |
| 27129 | 0, // zsub2_zsub3 |
| 27130 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27131 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27132 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27133 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27134 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27135 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27136 | }, |
| 27137 | { // DDDD |
| 27138 | 113, // bsub -> DDDD |
| 27139 | 0, // dsub |
| 27140 | 113, // dsub0 -> DDDD |
| 27141 | 113, // dsub1 -> DDDD |
| 27142 | 113, // dsub2 -> DDDD |
| 27143 | 113, // dsub3 -> DDDD |
| 27144 | 113, // hsub -> DDDD |
| 27145 | 0, // qhisub |
| 27146 | 0, // qsub |
| 27147 | 0, // qsub0 |
| 27148 | 0, // qsub1 |
| 27149 | 0, // qsub2 |
| 27150 | 0, // qsub3 |
| 27151 | 113, // ssub -> DDDD |
| 27152 | 0, // sub_32 |
| 27153 | 0, // sube32 |
| 27154 | 0, // sube64 |
| 27155 | 0, // subo32 |
| 27156 | 0, // subo64 |
| 27157 | 0, // x8sub_0 |
| 27158 | 0, // x8sub_1 |
| 27159 | 0, // x8sub_2 |
| 27160 | 0, // x8sub_3 |
| 27161 | 0, // x8sub_4 |
| 27162 | 0, // x8sub_5 |
| 27163 | 0, // x8sub_6 |
| 27164 | 0, // x8sub_7 |
| 27165 | 0, // zsub |
| 27166 | 0, // zsub0 |
| 27167 | 0, // zsub1 |
| 27168 | 0, // zsub2 |
| 27169 | 0, // zsub3 |
| 27170 | 0, // zsub_hi |
| 27171 | 113, // dsub1_then_bsub -> DDDD |
| 27172 | 113, // dsub1_then_hsub -> DDDD |
| 27173 | 113, // dsub1_then_ssub -> DDDD |
| 27174 | 113, // dsub3_then_bsub -> DDDD |
| 27175 | 113, // dsub3_then_hsub -> DDDD |
| 27176 | 113, // dsub3_then_ssub -> DDDD |
| 27177 | 113, // dsub2_then_bsub -> DDDD |
| 27178 | 113, // dsub2_then_hsub -> DDDD |
| 27179 | 113, // dsub2_then_ssub -> DDDD |
| 27180 | 0, // qsub1_then_bsub |
| 27181 | 0, // qsub1_then_dsub |
| 27182 | 0, // qsub1_then_hsub |
| 27183 | 0, // qsub1_then_ssub |
| 27184 | 0, // qsub3_then_bsub |
| 27185 | 0, // qsub3_then_dsub |
| 27186 | 0, // qsub3_then_hsub |
| 27187 | 0, // qsub3_then_ssub |
| 27188 | 0, // qsub2_then_bsub |
| 27189 | 0, // qsub2_then_dsub |
| 27190 | 0, // qsub2_then_hsub |
| 27191 | 0, // qsub2_then_ssub |
| 27192 | 0, // x8sub_7_then_sub_32 |
| 27193 | 0, // x8sub_6_then_sub_32 |
| 27194 | 0, // x8sub_5_then_sub_32 |
| 27195 | 0, // x8sub_4_then_sub_32 |
| 27196 | 0, // x8sub_3_then_sub_32 |
| 27197 | 0, // x8sub_2_then_sub_32 |
| 27198 | 0, // x8sub_1_then_sub_32 |
| 27199 | 0, // subo64_then_sub_32 |
| 27200 | 0, // zsub1_then_bsub |
| 27201 | 0, // zsub1_then_dsub |
| 27202 | 0, // zsub1_then_hsub |
| 27203 | 0, // zsub1_then_ssub |
| 27204 | 0, // zsub1_then_zsub |
| 27205 | 0, // zsub1_then_zsub_hi |
| 27206 | 0, // zsub3_then_bsub |
| 27207 | 0, // zsub3_then_dsub |
| 27208 | 0, // zsub3_then_hsub |
| 27209 | 0, // zsub3_then_ssub |
| 27210 | 0, // zsub3_then_zsub |
| 27211 | 0, // zsub3_then_zsub_hi |
| 27212 | 0, // zsub2_then_bsub |
| 27213 | 0, // zsub2_then_dsub |
| 27214 | 0, // zsub2_then_hsub |
| 27215 | 0, // zsub2_then_ssub |
| 27216 | 0, // zsub2_then_zsub |
| 27217 | 0, // zsub2_then_zsub_hi |
| 27218 | 113, // dsub0_dsub1 -> DDDD |
| 27219 | 113, // dsub0_dsub1_dsub2 -> DDDD |
| 27220 | 113, // dsub1_dsub2 -> DDDD |
| 27221 | 113, // dsub1_dsub2_dsub3 -> DDDD |
| 27222 | 113, // dsub2_dsub3 -> DDDD |
| 27223 | 0, // dsub_qsub1_then_dsub |
| 27224 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27225 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27226 | 0, // qsub0_qsub1 |
| 27227 | 0, // qsub0_qsub1_qsub2 |
| 27228 | 0, // qsub1_qsub2 |
| 27229 | 0, // qsub1_qsub2_qsub3 |
| 27230 | 0, // qsub2_qsub3 |
| 27231 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27232 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27233 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27234 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27235 | 0, // x8sub_0_x8sub_1 |
| 27236 | 0, // x8sub_2_x8sub_3 |
| 27237 | 0, // x8sub_4_x8sub_5 |
| 27238 | 0, // x8sub_6_x8sub_7 |
| 27239 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27240 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27241 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27242 | 0, // sub_32_subo64_then_sub_32 |
| 27243 | 0, // dsub_zsub1_then_dsub |
| 27244 | 0, // zsub_zsub1_then_zsub |
| 27245 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27246 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27247 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27248 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27249 | 0, // zsub0_zsub1 |
| 27250 | 0, // zsub0_zsub1_zsub2 |
| 27251 | 0, // zsub1_zsub2 |
| 27252 | 0, // zsub1_zsub2_zsub3 |
| 27253 | 0, // zsub2_zsub3 |
| 27254 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27255 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27256 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27257 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27258 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27259 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27260 | }, |
| 27261 | { // DDDD_with_dsub0_in_FPR64_lo |
| 27262 | 114, // bsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27263 | 0, // dsub |
| 27264 | 114, // dsub0 -> DDDD_with_dsub0_in_FPR64_lo |
| 27265 | 114, // dsub1 -> DDDD_with_dsub0_in_FPR64_lo |
| 27266 | 114, // dsub2 -> DDDD_with_dsub0_in_FPR64_lo |
| 27267 | 114, // dsub3 -> DDDD_with_dsub0_in_FPR64_lo |
| 27268 | 114, // hsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27269 | 0, // qhisub |
| 27270 | 0, // qsub |
| 27271 | 0, // qsub0 |
| 27272 | 0, // qsub1 |
| 27273 | 0, // qsub2 |
| 27274 | 0, // qsub3 |
| 27275 | 114, // ssub -> DDDD_with_dsub0_in_FPR64_lo |
| 27276 | 0, // sub_32 |
| 27277 | 0, // sube32 |
| 27278 | 0, // sube64 |
| 27279 | 0, // subo32 |
| 27280 | 0, // subo64 |
| 27281 | 0, // x8sub_0 |
| 27282 | 0, // x8sub_1 |
| 27283 | 0, // x8sub_2 |
| 27284 | 0, // x8sub_3 |
| 27285 | 0, // x8sub_4 |
| 27286 | 0, // x8sub_5 |
| 27287 | 0, // x8sub_6 |
| 27288 | 0, // x8sub_7 |
| 27289 | 0, // zsub |
| 27290 | 0, // zsub0 |
| 27291 | 0, // zsub1 |
| 27292 | 0, // zsub2 |
| 27293 | 0, // zsub3 |
| 27294 | 0, // zsub_hi |
| 27295 | 114, // dsub1_then_bsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27296 | 114, // dsub1_then_hsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27297 | 114, // dsub1_then_ssub -> DDDD_with_dsub0_in_FPR64_lo |
| 27298 | 114, // dsub3_then_bsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27299 | 114, // dsub3_then_hsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27300 | 114, // dsub3_then_ssub -> DDDD_with_dsub0_in_FPR64_lo |
| 27301 | 114, // dsub2_then_bsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27302 | 114, // dsub2_then_hsub -> DDDD_with_dsub0_in_FPR64_lo |
| 27303 | 114, // dsub2_then_ssub -> DDDD_with_dsub0_in_FPR64_lo |
| 27304 | 0, // qsub1_then_bsub |
| 27305 | 0, // qsub1_then_dsub |
| 27306 | 0, // qsub1_then_hsub |
| 27307 | 0, // qsub1_then_ssub |
| 27308 | 0, // qsub3_then_bsub |
| 27309 | 0, // qsub3_then_dsub |
| 27310 | 0, // qsub3_then_hsub |
| 27311 | 0, // qsub3_then_ssub |
| 27312 | 0, // qsub2_then_bsub |
| 27313 | 0, // qsub2_then_dsub |
| 27314 | 0, // qsub2_then_hsub |
| 27315 | 0, // qsub2_then_ssub |
| 27316 | 0, // x8sub_7_then_sub_32 |
| 27317 | 0, // x8sub_6_then_sub_32 |
| 27318 | 0, // x8sub_5_then_sub_32 |
| 27319 | 0, // x8sub_4_then_sub_32 |
| 27320 | 0, // x8sub_3_then_sub_32 |
| 27321 | 0, // x8sub_2_then_sub_32 |
| 27322 | 0, // x8sub_1_then_sub_32 |
| 27323 | 0, // subo64_then_sub_32 |
| 27324 | 0, // zsub1_then_bsub |
| 27325 | 0, // zsub1_then_dsub |
| 27326 | 0, // zsub1_then_hsub |
| 27327 | 0, // zsub1_then_ssub |
| 27328 | 0, // zsub1_then_zsub |
| 27329 | 0, // zsub1_then_zsub_hi |
| 27330 | 0, // zsub3_then_bsub |
| 27331 | 0, // zsub3_then_dsub |
| 27332 | 0, // zsub3_then_hsub |
| 27333 | 0, // zsub3_then_ssub |
| 27334 | 0, // zsub3_then_zsub |
| 27335 | 0, // zsub3_then_zsub_hi |
| 27336 | 0, // zsub2_then_bsub |
| 27337 | 0, // zsub2_then_dsub |
| 27338 | 0, // zsub2_then_hsub |
| 27339 | 0, // zsub2_then_ssub |
| 27340 | 0, // zsub2_then_zsub |
| 27341 | 0, // zsub2_then_zsub_hi |
| 27342 | 114, // dsub0_dsub1 -> DDDD_with_dsub0_in_FPR64_lo |
| 27343 | 114, // dsub0_dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo |
| 27344 | 114, // dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo |
| 27345 | 114, // dsub1_dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo |
| 27346 | 114, // dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo |
| 27347 | 0, // dsub_qsub1_then_dsub |
| 27348 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27349 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27350 | 0, // qsub0_qsub1 |
| 27351 | 0, // qsub0_qsub1_qsub2 |
| 27352 | 0, // qsub1_qsub2 |
| 27353 | 0, // qsub1_qsub2_qsub3 |
| 27354 | 0, // qsub2_qsub3 |
| 27355 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27356 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27357 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27358 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27359 | 0, // x8sub_0_x8sub_1 |
| 27360 | 0, // x8sub_2_x8sub_3 |
| 27361 | 0, // x8sub_4_x8sub_5 |
| 27362 | 0, // x8sub_6_x8sub_7 |
| 27363 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27364 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27365 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27366 | 0, // sub_32_subo64_then_sub_32 |
| 27367 | 0, // dsub_zsub1_then_dsub |
| 27368 | 0, // zsub_zsub1_then_zsub |
| 27369 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27370 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27371 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27372 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27373 | 0, // zsub0_zsub1 |
| 27374 | 0, // zsub0_zsub1_zsub2 |
| 27375 | 0, // zsub1_zsub2 |
| 27376 | 0, // zsub1_zsub2_zsub3 |
| 27377 | 0, // zsub2_zsub3 |
| 27378 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27379 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27380 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27381 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27382 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27383 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27384 | }, |
| 27385 | { // DDDD_with_dsub1_in_FPR64_lo |
| 27386 | 115, // bsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27387 | 0, // dsub |
| 27388 | 115, // dsub0 -> DDDD_with_dsub1_in_FPR64_lo |
| 27389 | 115, // dsub1 -> DDDD_with_dsub1_in_FPR64_lo |
| 27390 | 115, // dsub2 -> DDDD_with_dsub1_in_FPR64_lo |
| 27391 | 115, // dsub3 -> DDDD_with_dsub1_in_FPR64_lo |
| 27392 | 115, // hsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27393 | 0, // qhisub |
| 27394 | 0, // qsub |
| 27395 | 0, // qsub0 |
| 27396 | 0, // qsub1 |
| 27397 | 0, // qsub2 |
| 27398 | 0, // qsub3 |
| 27399 | 115, // ssub -> DDDD_with_dsub1_in_FPR64_lo |
| 27400 | 0, // sub_32 |
| 27401 | 0, // sube32 |
| 27402 | 0, // sube64 |
| 27403 | 0, // subo32 |
| 27404 | 0, // subo64 |
| 27405 | 0, // x8sub_0 |
| 27406 | 0, // x8sub_1 |
| 27407 | 0, // x8sub_2 |
| 27408 | 0, // x8sub_3 |
| 27409 | 0, // x8sub_4 |
| 27410 | 0, // x8sub_5 |
| 27411 | 0, // x8sub_6 |
| 27412 | 0, // x8sub_7 |
| 27413 | 0, // zsub |
| 27414 | 0, // zsub0 |
| 27415 | 0, // zsub1 |
| 27416 | 0, // zsub2 |
| 27417 | 0, // zsub3 |
| 27418 | 0, // zsub_hi |
| 27419 | 115, // dsub1_then_bsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27420 | 115, // dsub1_then_hsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27421 | 115, // dsub1_then_ssub -> DDDD_with_dsub1_in_FPR64_lo |
| 27422 | 115, // dsub3_then_bsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27423 | 115, // dsub3_then_hsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27424 | 115, // dsub3_then_ssub -> DDDD_with_dsub1_in_FPR64_lo |
| 27425 | 115, // dsub2_then_bsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27426 | 115, // dsub2_then_hsub -> DDDD_with_dsub1_in_FPR64_lo |
| 27427 | 115, // dsub2_then_ssub -> DDDD_with_dsub1_in_FPR64_lo |
| 27428 | 0, // qsub1_then_bsub |
| 27429 | 0, // qsub1_then_dsub |
| 27430 | 0, // qsub1_then_hsub |
| 27431 | 0, // qsub1_then_ssub |
| 27432 | 0, // qsub3_then_bsub |
| 27433 | 0, // qsub3_then_dsub |
| 27434 | 0, // qsub3_then_hsub |
| 27435 | 0, // qsub3_then_ssub |
| 27436 | 0, // qsub2_then_bsub |
| 27437 | 0, // qsub2_then_dsub |
| 27438 | 0, // qsub2_then_hsub |
| 27439 | 0, // qsub2_then_ssub |
| 27440 | 0, // x8sub_7_then_sub_32 |
| 27441 | 0, // x8sub_6_then_sub_32 |
| 27442 | 0, // x8sub_5_then_sub_32 |
| 27443 | 0, // x8sub_4_then_sub_32 |
| 27444 | 0, // x8sub_3_then_sub_32 |
| 27445 | 0, // x8sub_2_then_sub_32 |
| 27446 | 0, // x8sub_1_then_sub_32 |
| 27447 | 0, // subo64_then_sub_32 |
| 27448 | 0, // zsub1_then_bsub |
| 27449 | 0, // zsub1_then_dsub |
| 27450 | 0, // zsub1_then_hsub |
| 27451 | 0, // zsub1_then_ssub |
| 27452 | 0, // zsub1_then_zsub |
| 27453 | 0, // zsub1_then_zsub_hi |
| 27454 | 0, // zsub3_then_bsub |
| 27455 | 0, // zsub3_then_dsub |
| 27456 | 0, // zsub3_then_hsub |
| 27457 | 0, // zsub3_then_ssub |
| 27458 | 0, // zsub3_then_zsub |
| 27459 | 0, // zsub3_then_zsub_hi |
| 27460 | 0, // zsub2_then_bsub |
| 27461 | 0, // zsub2_then_dsub |
| 27462 | 0, // zsub2_then_hsub |
| 27463 | 0, // zsub2_then_ssub |
| 27464 | 0, // zsub2_then_zsub |
| 27465 | 0, // zsub2_then_zsub_hi |
| 27466 | 115, // dsub0_dsub1 -> DDDD_with_dsub1_in_FPR64_lo |
| 27467 | 115, // dsub0_dsub1_dsub2 -> DDDD_with_dsub1_in_FPR64_lo |
| 27468 | 115, // dsub1_dsub2 -> DDDD_with_dsub1_in_FPR64_lo |
| 27469 | 115, // dsub1_dsub2_dsub3 -> DDDD_with_dsub1_in_FPR64_lo |
| 27470 | 115, // dsub2_dsub3 -> DDDD_with_dsub1_in_FPR64_lo |
| 27471 | 0, // dsub_qsub1_then_dsub |
| 27472 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27473 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27474 | 0, // qsub0_qsub1 |
| 27475 | 0, // qsub0_qsub1_qsub2 |
| 27476 | 0, // qsub1_qsub2 |
| 27477 | 0, // qsub1_qsub2_qsub3 |
| 27478 | 0, // qsub2_qsub3 |
| 27479 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27480 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27481 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27482 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27483 | 0, // x8sub_0_x8sub_1 |
| 27484 | 0, // x8sub_2_x8sub_3 |
| 27485 | 0, // x8sub_4_x8sub_5 |
| 27486 | 0, // x8sub_6_x8sub_7 |
| 27487 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27488 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27489 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27490 | 0, // sub_32_subo64_then_sub_32 |
| 27491 | 0, // dsub_zsub1_then_dsub |
| 27492 | 0, // zsub_zsub1_then_zsub |
| 27493 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27494 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27495 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27496 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27497 | 0, // zsub0_zsub1 |
| 27498 | 0, // zsub0_zsub1_zsub2 |
| 27499 | 0, // zsub1_zsub2 |
| 27500 | 0, // zsub1_zsub2_zsub3 |
| 27501 | 0, // zsub2_zsub3 |
| 27502 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27503 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27504 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27505 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27506 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27507 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27508 | }, |
| 27509 | { // DDDD_with_dsub2_in_FPR64_lo |
| 27510 | 116, // bsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27511 | 0, // dsub |
| 27512 | 116, // dsub0 -> DDDD_with_dsub2_in_FPR64_lo |
| 27513 | 116, // dsub1 -> DDDD_with_dsub2_in_FPR64_lo |
| 27514 | 116, // dsub2 -> DDDD_with_dsub2_in_FPR64_lo |
| 27515 | 116, // dsub3 -> DDDD_with_dsub2_in_FPR64_lo |
| 27516 | 116, // hsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27517 | 0, // qhisub |
| 27518 | 0, // qsub |
| 27519 | 0, // qsub0 |
| 27520 | 0, // qsub1 |
| 27521 | 0, // qsub2 |
| 27522 | 0, // qsub3 |
| 27523 | 116, // ssub -> DDDD_with_dsub2_in_FPR64_lo |
| 27524 | 0, // sub_32 |
| 27525 | 0, // sube32 |
| 27526 | 0, // sube64 |
| 27527 | 0, // subo32 |
| 27528 | 0, // subo64 |
| 27529 | 0, // x8sub_0 |
| 27530 | 0, // x8sub_1 |
| 27531 | 0, // x8sub_2 |
| 27532 | 0, // x8sub_3 |
| 27533 | 0, // x8sub_4 |
| 27534 | 0, // x8sub_5 |
| 27535 | 0, // x8sub_6 |
| 27536 | 0, // x8sub_7 |
| 27537 | 0, // zsub |
| 27538 | 0, // zsub0 |
| 27539 | 0, // zsub1 |
| 27540 | 0, // zsub2 |
| 27541 | 0, // zsub3 |
| 27542 | 0, // zsub_hi |
| 27543 | 116, // dsub1_then_bsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27544 | 116, // dsub1_then_hsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27545 | 116, // dsub1_then_ssub -> DDDD_with_dsub2_in_FPR64_lo |
| 27546 | 116, // dsub3_then_bsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27547 | 116, // dsub3_then_hsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27548 | 116, // dsub3_then_ssub -> DDDD_with_dsub2_in_FPR64_lo |
| 27549 | 116, // dsub2_then_bsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27550 | 116, // dsub2_then_hsub -> DDDD_with_dsub2_in_FPR64_lo |
| 27551 | 116, // dsub2_then_ssub -> DDDD_with_dsub2_in_FPR64_lo |
| 27552 | 0, // qsub1_then_bsub |
| 27553 | 0, // qsub1_then_dsub |
| 27554 | 0, // qsub1_then_hsub |
| 27555 | 0, // qsub1_then_ssub |
| 27556 | 0, // qsub3_then_bsub |
| 27557 | 0, // qsub3_then_dsub |
| 27558 | 0, // qsub3_then_hsub |
| 27559 | 0, // qsub3_then_ssub |
| 27560 | 0, // qsub2_then_bsub |
| 27561 | 0, // qsub2_then_dsub |
| 27562 | 0, // qsub2_then_hsub |
| 27563 | 0, // qsub2_then_ssub |
| 27564 | 0, // x8sub_7_then_sub_32 |
| 27565 | 0, // x8sub_6_then_sub_32 |
| 27566 | 0, // x8sub_5_then_sub_32 |
| 27567 | 0, // x8sub_4_then_sub_32 |
| 27568 | 0, // x8sub_3_then_sub_32 |
| 27569 | 0, // x8sub_2_then_sub_32 |
| 27570 | 0, // x8sub_1_then_sub_32 |
| 27571 | 0, // subo64_then_sub_32 |
| 27572 | 0, // zsub1_then_bsub |
| 27573 | 0, // zsub1_then_dsub |
| 27574 | 0, // zsub1_then_hsub |
| 27575 | 0, // zsub1_then_ssub |
| 27576 | 0, // zsub1_then_zsub |
| 27577 | 0, // zsub1_then_zsub_hi |
| 27578 | 0, // zsub3_then_bsub |
| 27579 | 0, // zsub3_then_dsub |
| 27580 | 0, // zsub3_then_hsub |
| 27581 | 0, // zsub3_then_ssub |
| 27582 | 0, // zsub3_then_zsub |
| 27583 | 0, // zsub3_then_zsub_hi |
| 27584 | 0, // zsub2_then_bsub |
| 27585 | 0, // zsub2_then_dsub |
| 27586 | 0, // zsub2_then_hsub |
| 27587 | 0, // zsub2_then_ssub |
| 27588 | 0, // zsub2_then_zsub |
| 27589 | 0, // zsub2_then_zsub_hi |
| 27590 | 116, // dsub0_dsub1 -> DDDD_with_dsub2_in_FPR64_lo |
| 27591 | 116, // dsub0_dsub1_dsub2 -> DDDD_with_dsub2_in_FPR64_lo |
| 27592 | 116, // dsub1_dsub2 -> DDDD_with_dsub2_in_FPR64_lo |
| 27593 | 116, // dsub1_dsub2_dsub3 -> DDDD_with_dsub2_in_FPR64_lo |
| 27594 | 116, // dsub2_dsub3 -> DDDD_with_dsub2_in_FPR64_lo |
| 27595 | 0, // dsub_qsub1_then_dsub |
| 27596 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27597 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27598 | 0, // qsub0_qsub1 |
| 27599 | 0, // qsub0_qsub1_qsub2 |
| 27600 | 0, // qsub1_qsub2 |
| 27601 | 0, // qsub1_qsub2_qsub3 |
| 27602 | 0, // qsub2_qsub3 |
| 27603 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27604 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27605 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27606 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27607 | 0, // x8sub_0_x8sub_1 |
| 27608 | 0, // x8sub_2_x8sub_3 |
| 27609 | 0, // x8sub_4_x8sub_5 |
| 27610 | 0, // x8sub_6_x8sub_7 |
| 27611 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27612 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27613 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27614 | 0, // sub_32_subo64_then_sub_32 |
| 27615 | 0, // dsub_zsub1_then_dsub |
| 27616 | 0, // zsub_zsub1_then_zsub |
| 27617 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27618 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27619 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27620 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27621 | 0, // zsub0_zsub1 |
| 27622 | 0, // zsub0_zsub1_zsub2 |
| 27623 | 0, // zsub1_zsub2 |
| 27624 | 0, // zsub1_zsub2_zsub3 |
| 27625 | 0, // zsub2_zsub3 |
| 27626 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27627 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27628 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27629 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27630 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27631 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27632 | }, |
| 27633 | { // DDDD_with_dsub3_in_FPR64_lo |
| 27634 | 117, // bsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27635 | 0, // dsub |
| 27636 | 117, // dsub0 -> DDDD_with_dsub3_in_FPR64_lo |
| 27637 | 117, // dsub1 -> DDDD_with_dsub3_in_FPR64_lo |
| 27638 | 117, // dsub2 -> DDDD_with_dsub3_in_FPR64_lo |
| 27639 | 117, // dsub3 -> DDDD_with_dsub3_in_FPR64_lo |
| 27640 | 117, // hsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27641 | 0, // qhisub |
| 27642 | 0, // qsub |
| 27643 | 0, // qsub0 |
| 27644 | 0, // qsub1 |
| 27645 | 0, // qsub2 |
| 27646 | 0, // qsub3 |
| 27647 | 117, // ssub -> DDDD_with_dsub3_in_FPR64_lo |
| 27648 | 0, // sub_32 |
| 27649 | 0, // sube32 |
| 27650 | 0, // sube64 |
| 27651 | 0, // subo32 |
| 27652 | 0, // subo64 |
| 27653 | 0, // x8sub_0 |
| 27654 | 0, // x8sub_1 |
| 27655 | 0, // x8sub_2 |
| 27656 | 0, // x8sub_3 |
| 27657 | 0, // x8sub_4 |
| 27658 | 0, // x8sub_5 |
| 27659 | 0, // x8sub_6 |
| 27660 | 0, // x8sub_7 |
| 27661 | 0, // zsub |
| 27662 | 0, // zsub0 |
| 27663 | 0, // zsub1 |
| 27664 | 0, // zsub2 |
| 27665 | 0, // zsub3 |
| 27666 | 0, // zsub_hi |
| 27667 | 117, // dsub1_then_bsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27668 | 117, // dsub1_then_hsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27669 | 117, // dsub1_then_ssub -> DDDD_with_dsub3_in_FPR64_lo |
| 27670 | 117, // dsub3_then_bsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27671 | 117, // dsub3_then_hsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27672 | 117, // dsub3_then_ssub -> DDDD_with_dsub3_in_FPR64_lo |
| 27673 | 117, // dsub2_then_bsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27674 | 117, // dsub2_then_hsub -> DDDD_with_dsub3_in_FPR64_lo |
| 27675 | 117, // dsub2_then_ssub -> DDDD_with_dsub3_in_FPR64_lo |
| 27676 | 0, // qsub1_then_bsub |
| 27677 | 0, // qsub1_then_dsub |
| 27678 | 0, // qsub1_then_hsub |
| 27679 | 0, // qsub1_then_ssub |
| 27680 | 0, // qsub3_then_bsub |
| 27681 | 0, // qsub3_then_dsub |
| 27682 | 0, // qsub3_then_hsub |
| 27683 | 0, // qsub3_then_ssub |
| 27684 | 0, // qsub2_then_bsub |
| 27685 | 0, // qsub2_then_dsub |
| 27686 | 0, // qsub2_then_hsub |
| 27687 | 0, // qsub2_then_ssub |
| 27688 | 0, // x8sub_7_then_sub_32 |
| 27689 | 0, // x8sub_6_then_sub_32 |
| 27690 | 0, // x8sub_5_then_sub_32 |
| 27691 | 0, // x8sub_4_then_sub_32 |
| 27692 | 0, // x8sub_3_then_sub_32 |
| 27693 | 0, // x8sub_2_then_sub_32 |
| 27694 | 0, // x8sub_1_then_sub_32 |
| 27695 | 0, // subo64_then_sub_32 |
| 27696 | 0, // zsub1_then_bsub |
| 27697 | 0, // zsub1_then_dsub |
| 27698 | 0, // zsub1_then_hsub |
| 27699 | 0, // zsub1_then_ssub |
| 27700 | 0, // zsub1_then_zsub |
| 27701 | 0, // zsub1_then_zsub_hi |
| 27702 | 0, // zsub3_then_bsub |
| 27703 | 0, // zsub3_then_dsub |
| 27704 | 0, // zsub3_then_hsub |
| 27705 | 0, // zsub3_then_ssub |
| 27706 | 0, // zsub3_then_zsub |
| 27707 | 0, // zsub3_then_zsub_hi |
| 27708 | 0, // zsub2_then_bsub |
| 27709 | 0, // zsub2_then_dsub |
| 27710 | 0, // zsub2_then_hsub |
| 27711 | 0, // zsub2_then_ssub |
| 27712 | 0, // zsub2_then_zsub |
| 27713 | 0, // zsub2_then_zsub_hi |
| 27714 | 117, // dsub0_dsub1 -> DDDD_with_dsub3_in_FPR64_lo |
| 27715 | 117, // dsub0_dsub1_dsub2 -> DDDD_with_dsub3_in_FPR64_lo |
| 27716 | 117, // dsub1_dsub2 -> DDDD_with_dsub3_in_FPR64_lo |
| 27717 | 117, // dsub1_dsub2_dsub3 -> DDDD_with_dsub3_in_FPR64_lo |
| 27718 | 117, // dsub2_dsub3 -> DDDD_with_dsub3_in_FPR64_lo |
| 27719 | 0, // dsub_qsub1_then_dsub |
| 27720 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27721 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27722 | 0, // qsub0_qsub1 |
| 27723 | 0, // qsub0_qsub1_qsub2 |
| 27724 | 0, // qsub1_qsub2 |
| 27725 | 0, // qsub1_qsub2_qsub3 |
| 27726 | 0, // qsub2_qsub3 |
| 27727 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27728 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27729 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27730 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27731 | 0, // x8sub_0_x8sub_1 |
| 27732 | 0, // x8sub_2_x8sub_3 |
| 27733 | 0, // x8sub_4_x8sub_5 |
| 27734 | 0, // x8sub_6_x8sub_7 |
| 27735 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27736 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27737 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27738 | 0, // sub_32_subo64_then_sub_32 |
| 27739 | 0, // dsub_zsub1_then_dsub |
| 27740 | 0, // zsub_zsub1_then_zsub |
| 27741 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27742 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27743 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27744 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27745 | 0, // zsub0_zsub1 |
| 27746 | 0, // zsub0_zsub1_zsub2 |
| 27747 | 0, // zsub1_zsub2 |
| 27748 | 0, // zsub1_zsub2_zsub3 |
| 27749 | 0, // zsub2_zsub3 |
| 27750 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27751 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27752 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27753 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27754 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27755 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27756 | }, |
| 27757 | { // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27758 | 118, // bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27759 | 0, // dsub |
| 27760 | 118, // dsub0 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27761 | 118, // dsub1 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27762 | 118, // dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27763 | 118, // dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27764 | 118, // hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27765 | 0, // qhisub |
| 27766 | 0, // qsub |
| 27767 | 0, // qsub0 |
| 27768 | 0, // qsub1 |
| 27769 | 0, // qsub2 |
| 27770 | 0, // qsub3 |
| 27771 | 118, // ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27772 | 0, // sub_32 |
| 27773 | 0, // sube32 |
| 27774 | 0, // sube64 |
| 27775 | 0, // subo32 |
| 27776 | 0, // subo64 |
| 27777 | 0, // x8sub_0 |
| 27778 | 0, // x8sub_1 |
| 27779 | 0, // x8sub_2 |
| 27780 | 0, // x8sub_3 |
| 27781 | 0, // x8sub_4 |
| 27782 | 0, // x8sub_5 |
| 27783 | 0, // x8sub_6 |
| 27784 | 0, // x8sub_7 |
| 27785 | 0, // zsub |
| 27786 | 0, // zsub0 |
| 27787 | 0, // zsub1 |
| 27788 | 0, // zsub2 |
| 27789 | 0, // zsub3 |
| 27790 | 0, // zsub_hi |
| 27791 | 118, // dsub1_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27792 | 118, // dsub1_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27793 | 118, // dsub1_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27794 | 118, // dsub3_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27795 | 118, // dsub3_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27796 | 118, // dsub3_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27797 | 118, // dsub2_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27798 | 118, // dsub2_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27799 | 118, // dsub2_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27800 | 0, // qsub1_then_bsub |
| 27801 | 0, // qsub1_then_dsub |
| 27802 | 0, // qsub1_then_hsub |
| 27803 | 0, // qsub1_then_ssub |
| 27804 | 0, // qsub3_then_bsub |
| 27805 | 0, // qsub3_then_dsub |
| 27806 | 0, // qsub3_then_hsub |
| 27807 | 0, // qsub3_then_ssub |
| 27808 | 0, // qsub2_then_bsub |
| 27809 | 0, // qsub2_then_dsub |
| 27810 | 0, // qsub2_then_hsub |
| 27811 | 0, // qsub2_then_ssub |
| 27812 | 0, // x8sub_7_then_sub_32 |
| 27813 | 0, // x8sub_6_then_sub_32 |
| 27814 | 0, // x8sub_5_then_sub_32 |
| 27815 | 0, // x8sub_4_then_sub_32 |
| 27816 | 0, // x8sub_3_then_sub_32 |
| 27817 | 0, // x8sub_2_then_sub_32 |
| 27818 | 0, // x8sub_1_then_sub_32 |
| 27819 | 0, // subo64_then_sub_32 |
| 27820 | 0, // zsub1_then_bsub |
| 27821 | 0, // zsub1_then_dsub |
| 27822 | 0, // zsub1_then_hsub |
| 27823 | 0, // zsub1_then_ssub |
| 27824 | 0, // zsub1_then_zsub |
| 27825 | 0, // zsub1_then_zsub_hi |
| 27826 | 0, // zsub3_then_bsub |
| 27827 | 0, // zsub3_then_dsub |
| 27828 | 0, // zsub3_then_hsub |
| 27829 | 0, // zsub3_then_ssub |
| 27830 | 0, // zsub3_then_zsub |
| 27831 | 0, // zsub3_then_zsub_hi |
| 27832 | 0, // zsub2_then_bsub |
| 27833 | 0, // zsub2_then_dsub |
| 27834 | 0, // zsub2_then_hsub |
| 27835 | 0, // zsub2_then_ssub |
| 27836 | 0, // zsub2_then_zsub |
| 27837 | 0, // zsub2_then_zsub_hi |
| 27838 | 118, // dsub0_dsub1 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27839 | 118, // dsub0_dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27840 | 118, // dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27841 | 118, // dsub1_dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27842 | 118, // dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 27843 | 0, // dsub_qsub1_then_dsub |
| 27844 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27845 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27846 | 0, // qsub0_qsub1 |
| 27847 | 0, // qsub0_qsub1_qsub2 |
| 27848 | 0, // qsub1_qsub2 |
| 27849 | 0, // qsub1_qsub2_qsub3 |
| 27850 | 0, // qsub2_qsub3 |
| 27851 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27852 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27853 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27854 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27855 | 0, // x8sub_0_x8sub_1 |
| 27856 | 0, // x8sub_2_x8sub_3 |
| 27857 | 0, // x8sub_4_x8sub_5 |
| 27858 | 0, // x8sub_6_x8sub_7 |
| 27859 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27860 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27861 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27862 | 0, // sub_32_subo64_then_sub_32 |
| 27863 | 0, // dsub_zsub1_then_dsub |
| 27864 | 0, // zsub_zsub1_then_zsub |
| 27865 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27866 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27867 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27868 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27869 | 0, // zsub0_zsub1 |
| 27870 | 0, // zsub0_zsub1_zsub2 |
| 27871 | 0, // zsub1_zsub2 |
| 27872 | 0, // zsub1_zsub2_zsub3 |
| 27873 | 0, // zsub2_zsub3 |
| 27874 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27875 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27876 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 27877 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27878 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 27879 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 27880 | }, |
| 27881 | { // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27882 | 119, // bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27883 | 0, // dsub |
| 27884 | 119, // dsub0 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27885 | 119, // dsub1 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27886 | 119, // dsub2 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27887 | 119, // dsub3 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27888 | 119, // hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27889 | 0, // qhisub |
| 27890 | 0, // qsub |
| 27891 | 0, // qsub0 |
| 27892 | 0, // qsub1 |
| 27893 | 0, // qsub2 |
| 27894 | 0, // qsub3 |
| 27895 | 119, // ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27896 | 0, // sub_32 |
| 27897 | 0, // sube32 |
| 27898 | 0, // sube64 |
| 27899 | 0, // subo32 |
| 27900 | 0, // subo64 |
| 27901 | 0, // x8sub_0 |
| 27902 | 0, // x8sub_1 |
| 27903 | 0, // x8sub_2 |
| 27904 | 0, // x8sub_3 |
| 27905 | 0, // x8sub_4 |
| 27906 | 0, // x8sub_5 |
| 27907 | 0, // x8sub_6 |
| 27908 | 0, // x8sub_7 |
| 27909 | 0, // zsub |
| 27910 | 0, // zsub0 |
| 27911 | 0, // zsub1 |
| 27912 | 0, // zsub2 |
| 27913 | 0, // zsub3 |
| 27914 | 0, // zsub_hi |
| 27915 | 119, // dsub1_then_bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27916 | 119, // dsub1_then_hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27917 | 119, // dsub1_then_ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27918 | 119, // dsub3_then_bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27919 | 119, // dsub3_then_hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27920 | 119, // dsub3_then_ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27921 | 119, // dsub2_then_bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27922 | 119, // dsub2_then_hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27923 | 119, // dsub2_then_ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27924 | 0, // qsub1_then_bsub |
| 27925 | 0, // qsub1_then_dsub |
| 27926 | 0, // qsub1_then_hsub |
| 27927 | 0, // qsub1_then_ssub |
| 27928 | 0, // qsub3_then_bsub |
| 27929 | 0, // qsub3_then_dsub |
| 27930 | 0, // qsub3_then_hsub |
| 27931 | 0, // qsub3_then_ssub |
| 27932 | 0, // qsub2_then_bsub |
| 27933 | 0, // qsub2_then_dsub |
| 27934 | 0, // qsub2_then_hsub |
| 27935 | 0, // qsub2_then_ssub |
| 27936 | 0, // x8sub_7_then_sub_32 |
| 27937 | 0, // x8sub_6_then_sub_32 |
| 27938 | 0, // x8sub_5_then_sub_32 |
| 27939 | 0, // x8sub_4_then_sub_32 |
| 27940 | 0, // x8sub_3_then_sub_32 |
| 27941 | 0, // x8sub_2_then_sub_32 |
| 27942 | 0, // x8sub_1_then_sub_32 |
| 27943 | 0, // subo64_then_sub_32 |
| 27944 | 0, // zsub1_then_bsub |
| 27945 | 0, // zsub1_then_dsub |
| 27946 | 0, // zsub1_then_hsub |
| 27947 | 0, // zsub1_then_ssub |
| 27948 | 0, // zsub1_then_zsub |
| 27949 | 0, // zsub1_then_zsub_hi |
| 27950 | 0, // zsub3_then_bsub |
| 27951 | 0, // zsub3_then_dsub |
| 27952 | 0, // zsub3_then_hsub |
| 27953 | 0, // zsub3_then_ssub |
| 27954 | 0, // zsub3_then_zsub |
| 27955 | 0, // zsub3_then_zsub_hi |
| 27956 | 0, // zsub2_then_bsub |
| 27957 | 0, // zsub2_then_dsub |
| 27958 | 0, // zsub2_then_hsub |
| 27959 | 0, // zsub2_then_ssub |
| 27960 | 0, // zsub2_then_zsub |
| 27961 | 0, // zsub2_then_zsub_hi |
| 27962 | 119, // dsub0_dsub1 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27963 | 119, // dsub0_dsub1_dsub2 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27964 | 119, // dsub1_dsub2 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27965 | 119, // dsub1_dsub2_dsub3 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27966 | 119, // dsub2_dsub3 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 27967 | 0, // dsub_qsub1_then_dsub |
| 27968 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27969 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 27970 | 0, // qsub0_qsub1 |
| 27971 | 0, // qsub0_qsub1_qsub2 |
| 27972 | 0, // qsub1_qsub2 |
| 27973 | 0, // qsub1_qsub2_qsub3 |
| 27974 | 0, // qsub2_qsub3 |
| 27975 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 27976 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 27977 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 27978 | 0, // sub_32_x8sub_1_then_sub_32 |
| 27979 | 0, // x8sub_0_x8sub_1 |
| 27980 | 0, // x8sub_2_x8sub_3 |
| 27981 | 0, // x8sub_4_x8sub_5 |
| 27982 | 0, // x8sub_6_x8sub_7 |
| 27983 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 27984 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 27985 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 27986 | 0, // sub_32_subo64_then_sub_32 |
| 27987 | 0, // dsub_zsub1_then_dsub |
| 27988 | 0, // zsub_zsub1_then_zsub |
| 27989 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 27990 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 27991 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 27992 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 27993 | 0, // zsub0_zsub1 |
| 27994 | 0, // zsub0_zsub1_zsub2 |
| 27995 | 0, // zsub1_zsub2 |
| 27996 | 0, // zsub1_zsub2_zsub3 |
| 27997 | 0, // zsub2_zsub3 |
| 27998 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 27999 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28000 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28001 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28002 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28003 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28004 | }, |
| 28005 | { // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28006 | 120, // bsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28007 | 0, // dsub |
| 28008 | 120, // dsub0 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28009 | 120, // dsub1 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28010 | 120, // dsub2 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28011 | 120, // dsub3 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28012 | 120, // hsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28013 | 0, // qhisub |
| 28014 | 0, // qsub |
| 28015 | 0, // qsub0 |
| 28016 | 0, // qsub1 |
| 28017 | 0, // qsub2 |
| 28018 | 0, // qsub3 |
| 28019 | 120, // ssub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28020 | 0, // sub_32 |
| 28021 | 0, // sube32 |
| 28022 | 0, // sube64 |
| 28023 | 0, // subo32 |
| 28024 | 0, // subo64 |
| 28025 | 0, // x8sub_0 |
| 28026 | 0, // x8sub_1 |
| 28027 | 0, // x8sub_2 |
| 28028 | 0, // x8sub_3 |
| 28029 | 0, // x8sub_4 |
| 28030 | 0, // x8sub_5 |
| 28031 | 0, // x8sub_6 |
| 28032 | 0, // x8sub_7 |
| 28033 | 0, // zsub |
| 28034 | 0, // zsub0 |
| 28035 | 0, // zsub1 |
| 28036 | 0, // zsub2 |
| 28037 | 0, // zsub3 |
| 28038 | 0, // zsub_hi |
| 28039 | 120, // dsub1_then_bsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28040 | 120, // dsub1_then_hsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28041 | 120, // dsub1_then_ssub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28042 | 120, // dsub3_then_bsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28043 | 120, // dsub3_then_hsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28044 | 120, // dsub3_then_ssub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28045 | 120, // dsub2_then_bsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28046 | 120, // dsub2_then_hsub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28047 | 120, // dsub2_then_ssub -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28048 | 0, // qsub1_then_bsub |
| 28049 | 0, // qsub1_then_dsub |
| 28050 | 0, // qsub1_then_hsub |
| 28051 | 0, // qsub1_then_ssub |
| 28052 | 0, // qsub3_then_bsub |
| 28053 | 0, // qsub3_then_dsub |
| 28054 | 0, // qsub3_then_hsub |
| 28055 | 0, // qsub3_then_ssub |
| 28056 | 0, // qsub2_then_bsub |
| 28057 | 0, // qsub2_then_dsub |
| 28058 | 0, // qsub2_then_hsub |
| 28059 | 0, // qsub2_then_ssub |
| 28060 | 0, // x8sub_7_then_sub_32 |
| 28061 | 0, // x8sub_6_then_sub_32 |
| 28062 | 0, // x8sub_5_then_sub_32 |
| 28063 | 0, // x8sub_4_then_sub_32 |
| 28064 | 0, // x8sub_3_then_sub_32 |
| 28065 | 0, // x8sub_2_then_sub_32 |
| 28066 | 0, // x8sub_1_then_sub_32 |
| 28067 | 0, // subo64_then_sub_32 |
| 28068 | 0, // zsub1_then_bsub |
| 28069 | 0, // zsub1_then_dsub |
| 28070 | 0, // zsub1_then_hsub |
| 28071 | 0, // zsub1_then_ssub |
| 28072 | 0, // zsub1_then_zsub |
| 28073 | 0, // zsub1_then_zsub_hi |
| 28074 | 0, // zsub3_then_bsub |
| 28075 | 0, // zsub3_then_dsub |
| 28076 | 0, // zsub3_then_hsub |
| 28077 | 0, // zsub3_then_ssub |
| 28078 | 0, // zsub3_then_zsub |
| 28079 | 0, // zsub3_then_zsub_hi |
| 28080 | 0, // zsub2_then_bsub |
| 28081 | 0, // zsub2_then_dsub |
| 28082 | 0, // zsub2_then_hsub |
| 28083 | 0, // zsub2_then_ssub |
| 28084 | 0, // zsub2_then_zsub |
| 28085 | 0, // zsub2_then_zsub_hi |
| 28086 | 120, // dsub0_dsub1 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28087 | 120, // dsub0_dsub1_dsub2 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28088 | 120, // dsub1_dsub2 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28089 | 120, // dsub1_dsub2_dsub3 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28090 | 120, // dsub2_dsub3 -> DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28091 | 0, // dsub_qsub1_then_dsub |
| 28092 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28093 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28094 | 0, // qsub0_qsub1 |
| 28095 | 0, // qsub0_qsub1_qsub2 |
| 28096 | 0, // qsub1_qsub2 |
| 28097 | 0, // qsub1_qsub2_qsub3 |
| 28098 | 0, // qsub2_qsub3 |
| 28099 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28100 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28101 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28102 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28103 | 0, // x8sub_0_x8sub_1 |
| 28104 | 0, // x8sub_2_x8sub_3 |
| 28105 | 0, // x8sub_4_x8sub_5 |
| 28106 | 0, // x8sub_6_x8sub_7 |
| 28107 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28108 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28109 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28110 | 0, // sub_32_subo64_then_sub_32 |
| 28111 | 0, // dsub_zsub1_then_dsub |
| 28112 | 0, // zsub_zsub1_then_zsub |
| 28113 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28114 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28115 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28116 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28117 | 0, // zsub0_zsub1 |
| 28118 | 0, // zsub0_zsub1_zsub2 |
| 28119 | 0, // zsub1_zsub2 |
| 28120 | 0, // zsub1_zsub2_zsub3 |
| 28121 | 0, // zsub2_zsub3 |
| 28122 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28123 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28124 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28125 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28126 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28127 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28128 | }, |
| 28129 | { // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28130 | 121, // bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28131 | 0, // dsub |
| 28132 | 121, // dsub0 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28133 | 121, // dsub1 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28134 | 121, // dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28135 | 121, // dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28136 | 121, // hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28137 | 0, // qhisub |
| 28138 | 0, // qsub |
| 28139 | 0, // qsub0 |
| 28140 | 0, // qsub1 |
| 28141 | 0, // qsub2 |
| 28142 | 0, // qsub3 |
| 28143 | 121, // ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28144 | 0, // sub_32 |
| 28145 | 0, // sube32 |
| 28146 | 0, // sube64 |
| 28147 | 0, // subo32 |
| 28148 | 0, // subo64 |
| 28149 | 0, // x8sub_0 |
| 28150 | 0, // x8sub_1 |
| 28151 | 0, // x8sub_2 |
| 28152 | 0, // x8sub_3 |
| 28153 | 0, // x8sub_4 |
| 28154 | 0, // x8sub_5 |
| 28155 | 0, // x8sub_6 |
| 28156 | 0, // x8sub_7 |
| 28157 | 0, // zsub |
| 28158 | 0, // zsub0 |
| 28159 | 0, // zsub1 |
| 28160 | 0, // zsub2 |
| 28161 | 0, // zsub3 |
| 28162 | 0, // zsub_hi |
| 28163 | 121, // dsub1_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28164 | 121, // dsub1_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28165 | 121, // dsub1_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28166 | 121, // dsub3_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28167 | 121, // dsub3_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28168 | 121, // dsub3_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28169 | 121, // dsub2_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28170 | 121, // dsub2_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28171 | 121, // dsub2_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28172 | 0, // qsub1_then_bsub |
| 28173 | 0, // qsub1_then_dsub |
| 28174 | 0, // qsub1_then_hsub |
| 28175 | 0, // qsub1_then_ssub |
| 28176 | 0, // qsub3_then_bsub |
| 28177 | 0, // qsub3_then_dsub |
| 28178 | 0, // qsub3_then_hsub |
| 28179 | 0, // qsub3_then_ssub |
| 28180 | 0, // qsub2_then_bsub |
| 28181 | 0, // qsub2_then_dsub |
| 28182 | 0, // qsub2_then_hsub |
| 28183 | 0, // qsub2_then_ssub |
| 28184 | 0, // x8sub_7_then_sub_32 |
| 28185 | 0, // x8sub_6_then_sub_32 |
| 28186 | 0, // x8sub_5_then_sub_32 |
| 28187 | 0, // x8sub_4_then_sub_32 |
| 28188 | 0, // x8sub_3_then_sub_32 |
| 28189 | 0, // x8sub_2_then_sub_32 |
| 28190 | 0, // x8sub_1_then_sub_32 |
| 28191 | 0, // subo64_then_sub_32 |
| 28192 | 0, // zsub1_then_bsub |
| 28193 | 0, // zsub1_then_dsub |
| 28194 | 0, // zsub1_then_hsub |
| 28195 | 0, // zsub1_then_ssub |
| 28196 | 0, // zsub1_then_zsub |
| 28197 | 0, // zsub1_then_zsub_hi |
| 28198 | 0, // zsub3_then_bsub |
| 28199 | 0, // zsub3_then_dsub |
| 28200 | 0, // zsub3_then_hsub |
| 28201 | 0, // zsub3_then_ssub |
| 28202 | 0, // zsub3_then_zsub |
| 28203 | 0, // zsub3_then_zsub_hi |
| 28204 | 0, // zsub2_then_bsub |
| 28205 | 0, // zsub2_then_dsub |
| 28206 | 0, // zsub2_then_hsub |
| 28207 | 0, // zsub2_then_ssub |
| 28208 | 0, // zsub2_then_zsub |
| 28209 | 0, // zsub2_then_zsub_hi |
| 28210 | 121, // dsub0_dsub1 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28211 | 121, // dsub0_dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28212 | 121, // dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28213 | 121, // dsub1_dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28214 | 121, // dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 28215 | 0, // dsub_qsub1_then_dsub |
| 28216 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28217 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28218 | 0, // qsub0_qsub1 |
| 28219 | 0, // qsub0_qsub1_qsub2 |
| 28220 | 0, // qsub1_qsub2 |
| 28221 | 0, // qsub1_qsub2_qsub3 |
| 28222 | 0, // qsub2_qsub3 |
| 28223 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28224 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28225 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28226 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28227 | 0, // x8sub_0_x8sub_1 |
| 28228 | 0, // x8sub_2_x8sub_3 |
| 28229 | 0, // x8sub_4_x8sub_5 |
| 28230 | 0, // x8sub_6_x8sub_7 |
| 28231 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28232 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28233 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28234 | 0, // sub_32_subo64_then_sub_32 |
| 28235 | 0, // dsub_zsub1_then_dsub |
| 28236 | 0, // zsub_zsub1_then_zsub |
| 28237 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28238 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28239 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28240 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28241 | 0, // zsub0_zsub1 |
| 28242 | 0, // zsub0_zsub1_zsub2 |
| 28243 | 0, // zsub1_zsub2 |
| 28244 | 0, // zsub1_zsub2_zsub3 |
| 28245 | 0, // zsub2_zsub3 |
| 28246 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28247 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28248 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28249 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28250 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28251 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28252 | }, |
| 28253 | { // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28254 | 122, // bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28255 | 0, // dsub |
| 28256 | 122, // dsub0 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28257 | 122, // dsub1 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28258 | 122, // dsub2 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28259 | 122, // dsub3 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28260 | 122, // hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28261 | 0, // qhisub |
| 28262 | 0, // qsub |
| 28263 | 0, // qsub0 |
| 28264 | 0, // qsub1 |
| 28265 | 0, // qsub2 |
| 28266 | 0, // qsub3 |
| 28267 | 122, // ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28268 | 0, // sub_32 |
| 28269 | 0, // sube32 |
| 28270 | 0, // sube64 |
| 28271 | 0, // subo32 |
| 28272 | 0, // subo64 |
| 28273 | 0, // x8sub_0 |
| 28274 | 0, // x8sub_1 |
| 28275 | 0, // x8sub_2 |
| 28276 | 0, // x8sub_3 |
| 28277 | 0, // x8sub_4 |
| 28278 | 0, // x8sub_5 |
| 28279 | 0, // x8sub_6 |
| 28280 | 0, // x8sub_7 |
| 28281 | 0, // zsub |
| 28282 | 0, // zsub0 |
| 28283 | 0, // zsub1 |
| 28284 | 0, // zsub2 |
| 28285 | 0, // zsub3 |
| 28286 | 0, // zsub_hi |
| 28287 | 122, // dsub1_then_bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28288 | 122, // dsub1_then_hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28289 | 122, // dsub1_then_ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28290 | 122, // dsub3_then_bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28291 | 122, // dsub3_then_hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28292 | 122, // dsub3_then_ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28293 | 122, // dsub2_then_bsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28294 | 122, // dsub2_then_hsub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28295 | 122, // dsub2_then_ssub -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28296 | 0, // qsub1_then_bsub |
| 28297 | 0, // qsub1_then_dsub |
| 28298 | 0, // qsub1_then_hsub |
| 28299 | 0, // qsub1_then_ssub |
| 28300 | 0, // qsub3_then_bsub |
| 28301 | 0, // qsub3_then_dsub |
| 28302 | 0, // qsub3_then_hsub |
| 28303 | 0, // qsub3_then_ssub |
| 28304 | 0, // qsub2_then_bsub |
| 28305 | 0, // qsub2_then_dsub |
| 28306 | 0, // qsub2_then_hsub |
| 28307 | 0, // qsub2_then_ssub |
| 28308 | 0, // x8sub_7_then_sub_32 |
| 28309 | 0, // x8sub_6_then_sub_32 |
| 28310 | 0, // x8sub_5_then_sub_32 |
| 28311 | 0, // x8sub_4_then_sub_32 |
| 28312 | 0, // x8sub_3_then_sub_32 |
| 28313 | 0, // x8sub_2_then_sub_32 |
| 28314 | 0, // x8sub_1_then_sub_32 |
| 28315 | 0, // subo64_then_sub_32 |
| 28316 | 0, // zsub1_then_bsub |
| 28317 | 0, // zsub1_then_dsub |
| 28318 | 0, // zsub1_then_hsub |
| 28319 | 0, // zsub1_then_ssub |
| 28320 | 0, // zsub1_then_zsub |
| 28321 | 0, // zsub1_then_zsub_hi |
| 28322 | 0, // zsub3_then_bsub |
| 28323 | 0, // zsub3_then_dsub |
| 28324 | 0, // zsub3_then_hsub |
| 28325 | 0, // zsub3_then_ssub |
| 28326 | 0, // zsub3_then_zsub |
| 28327 | 0, // zsub3_then_zsub_hi |
| 28328 | 0, // zsub2_then_bsub |
| 28329 | 0, // zsub2_then_dsub |
| 28330 | 0, // zsub2_then_hsub |
| 28331 | 0, // zsub2_then_ssub |
| 28332 | 0, // zsub2_then_zsub |
| 28333 | 0, // zsub2_then_zsub_hi |
| 28334 | 122, // dsub0_dsub1 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28335 | 122, // dsub0_dsub1_dsub2 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28336 | 122, // dsub1_dsub2 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28337 | 122, // dsub1_dsub2_dsub3 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28338 | 122, // dsub2_dsub3 -> DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28339 | 0, // dsub_qsub1_then_dsub |
| 28340 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28341 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28342 | 0, // qsub0_qsub1 |
| 28343 | 0, // qsub0_qsub1_qsub2 |
| 28344 | 0, // qsub1_qsub2 |
| 28345 | 0, // qsub1_qsub2_qsub3 |
| 28346 | 0, // qsub2_qsub3 |
| 28347 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28348 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28349 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28350 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28351 | 0, // x8sub_0_x8sub_1 |
| 28352 | 0, // x8sub_2_x8sub_3 |
| 28353 | 0, // x8sub_4_x8sub_5 |
| 28354 | 0, // x8sub_6_x8sub_7 |
| 28355 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28356 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28357 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28358 | 0, // sub_32_subo64_then_sub_32 |
| 28359 | 0, // dsub_zsub1_then_dsub |
| 28360 | 0, // zsub_zsub1_then_zsub |
| 28361 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28362 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28363 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28364 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28365 | 0, // zsub0_zsub1 |
| 28366 | 0, // zsub0_zsub1_zsub2 |
| 28367 | 0, // zsub1_zsub2 |
| 28368 | 0, // zsub1_zsub2_zsub3 |
| 28369 | 0, // zsub2_zsub3 |
| 28370 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28371 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28372 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28373 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28374 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28375 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28376 | }, |
| 28377 | { // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28378 | 123, // bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28379 | 0, // dsub |
| 28380 | 123, // dsub0 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28381 | 123, // dsub1 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28382 | 123, // dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28383 | 123, // dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28384 | 123, // hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28385 | 0, // qhisub |
| 28386 | 0, // qsub |
| 28387 | 0, // qsub0 |
| 28388 | 0, // qsub1 |
| 28389 | 0, // qsub2 |
| 28390 | 0, // qsub3 |
| 28391 | 123, // ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28392 | 0, // sub_32 |
| 28393 | 0, // sube32 |
| 28394 | 0, // sube64 |
| 28395 | 0, // subo32 |
| 28396 | 0, // subo64 |
| 28397 | 0, // x8sub_0 |
| 28398 | 0, // x8sub_1 |
| 28399 | 0, // x8sub_2 |
| 28400 | 0, // x8sub_3 |
| 28401 | 0, // x8sub_4 |
| 28402 | 0, // x8sub_5 |
| 28403 | 0, // x8sub_6 |
| 28404 | 0, // x8sub_7 |
| 28405 | 0, // zsub |
| 28406 | 0, // zsub0 |
| 28407 | 0, // zsub1 |
| 28408 | 0, // zsub2 |
| 28409 | 0, // zsub3 |
| 28410 | 0, // zsub_hi |
| 28411 | 123, // dsub1_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28412 | 123, // dsub1_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28413 | 123, // dsub1_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28414 | 123, // dsub3_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28415 | 123, // dsub3_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28416 | 123, // dsub3_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28417 | 123, // dsub2_then_bsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28418 | 123, // dsub2_then_hsub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28419 | 123, // dsub2_then_ssub -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28420 | 0, // qsub1_then_bsub |
| 28421 | 0, // qsub1_then_dsub |
| 28422 | 0, // qsub1_then_hsub |
| 28423 | 0, // qsub1_then_ssub |
| 28424 | 0, // qsub3_then_bsub |
| 28425 | 0, // qsub3_then_dsub |
| 28426 | 0, // qsub3_then_hsub |
| 28427 | 0, // qsub3_then_ssub |
| 28428 | 0, // qsub2_then_bsub |
| 28429 | 0, // qsub2_then_dsub |
| 28430 | 0, // qsub2_then_hsub |
| 28431 | 0, // qsub2_then_ssub |
| 28432 | 0, // x8sub_7_then_sub_32 |
| 28433 | 0, // x8sub_6_then_sub_32 |
| 28434 | 0, // x8sub_5_then_sub_32 |
| 28435 | 0, // x8sub_4_then_sub_32 |
| 28436 | 0, // x8sub_3_then_sub_32 |
| 28437 | 0, // x8sub_2_then_sub_32 |
| 28438 | 0, // x8sub_1_then_sub_32 |
| 28439 | 0, // subo64_then_sub_32 |
| 28440 | 0, // zsub1_then_bsub |
| 28441 | 0, // zsub1_then_dsub |
| 28442 | 0, // zsub1_then_hsub |
| 28443 | 0, // zsub1_then_ssub |
| 28444 | 0, // zsub1_then_zsub |
| 28445 | 0, // zsub1_then_zsub_hi |
| 28446 | 0, // zsub3_then_bsub |
| 28447 | 0, // zsub3_then_dsub |
| 28448 | 0, // zsub3_then_hsub |
| 28449 | 0, // zsub3_then_ssub |
| 28450 | 0, // zsub3_then_zsub |
| 28451 | 0, // zsub3_then_zsub_hi |
| 28452 | 0, // zsub2_then_bsub |
| 28453 | 0, // zsub2_then_dsub |
| 28454 | 0, // zsub2_then_hsub |
| 28455 | 0, // zsub2_then_ssub |
| 28456 | 0, // zsub2_then_zsub |
| 28457 | 0, // zsub2_then_zsub_hi |
| 28458 | 123, // dsub0_dsub1 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28459 | 123, // dsub0_dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28460 | 123, // dsub1_dsub2 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28461 | 123, // dsub1_dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28462 | 123, // dsub2_dsub3 -> DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 28463 | 0, // dsub_qsub1_then_dsub |
| 28464 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28465 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28466 | 0, // qsub0_qsub1 |
| 28467 | 0, // qsub0_qsub1_qsub2 |
| 28468 | 0, // qsub1_qsub2 |
| 28469 | 0, // qsub1_qsub2_qsub3 |
| 28470 | 0, // qsub2_qsub3 |
| 28471 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28472 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28473 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28474 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28475 | 0, // x8sub_0_x8sub_1 |
| 28476 | 0, // x8sub_2_x8sub_3 |
| 28477 | 0, // x8sub_4_x8sub_5 |
| 28478 | 0, // x8sub_6_x8sub_7 |
| 28479 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28480 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28481 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28482 | 0, // sub_32_subo64_then_sub_32 |
| 28483 | 0, // dsub_zsub1_then_dsub |
| 28484 | 0, // zsub_zsub1_then_zsub |
| 28485 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28486 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28487 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28488 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28489 | 0, // zsub0_zsub1 |
| 28490 | 0, // zsub0_zsub1_zsub2 |
| 28491 | 0, // zsub1_zsub2 |
| 28492 | 0, // zsub1_zsub2_zsub3 |
| 28493 | 0, // zsub2_zsub3 |
| 28494 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28495 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28496 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28497 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28498 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28499 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28500 | }, |
| 28501 | { // QQ |
| 28502 | 124, // bsub -> QQ |
| 28503 | 124, // dsub -> QQ |
| 28504 | 0, // dsub0 |
| 28505 | 0, // dsub1 |
| 28506 | 0, // dsub2 |
| 28507 | 0, // dsub3 |
| 28508 | 124, // hsub -> QQ |
| 28509 | 0, // qhisub |
| 28510 | 0, // qsub |
| 28511 | 124, // qsub0 -> QQ |
| 28512 | 124, // qsub1 -> QQ |
| 28513 | 0, // qsub2 |
| 28514 | 0, // qsub3 |
| 28515 | 124, // ssub -> QQ |
| 28516 | 0, // sub_32 |
| 28517 | 0, // sube32 |
| 28518 | 0, // sube64 |
| 28519 | 0, // subo32 |
| 28520 | 0, // subo64 |
| 28521 | 0, // x8sub_0 |
| 28522 | 0, // x8sub_1 |
| 28523 | 0, // x8sub_2 |
| 28524 | 0, // x8sub_3 |
| 28525 | 0, // x8sub_4 |
| 28526 | 0, // x8sub_5 |
| 28527 | 0, // x8sub_6 |
| 28528 | 0, // x8sub_7 |
| 28529 | 0, // zsub |
| 28530 | 0, // zsub0 |
| 28531 | 0, // zsub1 |
| 28532 | 0, // zsub2 |
| 28533 | 0, // zsub3 |
| 28534 | 0, // zsub_hi |
| 28535 | 0, // dsub1_then_bsub |
| 28536 | 0, // dsub1_then_hsub |
| 28537 | 0, // dsub1_then_ssub |
| 28538 | 0, // dsub3_then_bsub |
| 28539 | 0, // dsub3_then_hsub |
| 28540 | 0, // dsub3_then_ssub |
| 28541 | 0, // dsub2_then_bsub |
| 28542 | 0, // dsub2_then_hsub |
| 28543 | 0, // dsub2_then_ssub |
| 28544 | 124, // qsub1_then_bsub -> QQ |
| 28545 | 124, // qsub1_then_dsub -> QQ |
| 28546 | 124, // qsub1_then_hsub -> QQ |
| 28547 | 124, // qsub1_then_ssub -> QQ |
| 28548 | 0, // qsub3_then_bsub |
| 28549 | 0, // qsub3_then_dsub |
| 28550 | 0, // qsub3_then_hsub |
| 28551 | 0, // qsub3_then_ssub |
| 28552 | 0, // qsub2_then_bsub |
| 28553 | 0, // qsub2_then_dsub |
| 28554 | 0, // qsub2_then_hsub |
| 28555 | 0, // qsub2_then_ssub |
| 28556 | 0, // x8sub_7_then_sub_32 |
| 28557 | 0, // x8sub_6_then_sub_32 |
| 28558 | 0, // x8sub_5_then_sub_32 |
| 28559 | 0, // x8sub_4_then_sub_32 |
| 28560 | 0, // x8sub_3_then_sub_32 |
| 28561 | 0, // x8sub_2_then_sub_32 |
| 28562 | 0, // x8sub_1_then_sub_32 |
| 28563 | 0, // subo64_then_sub_32 |
| 28564 | 0, // zsub1_then_bsub |
| 28565 | 0, // zsub1_then_dsub |
| 28566 | 0, // zsub1_then_hsub |
| 28567 | 0, // zsub1_then_ssub |
| 28568 | 0, // zsub1_then_zsub |
| 28569 | 0, // zsub1_then_zsub_hi |
| 28570 | 0, // zsub3_then_bsub |
| 28571 | 0, // zsub3_then_dsub |
| 28572 | 0, // zsub3_then_hsub |
| 28573 | 0, // zsub3_then_ssub |
| 28574 | 0, // zsub3_then_zsub |
| 28575 | 0, // zsub3_then_zsub_hi |
| 28576 | 0, // zsub2_then_bsub |
| 28577 | 0, // zsub2_then_dsub |
| 28578 | 0, // zsub2_then_hsub |
| 28579 | 0, // zsub2_then_ssub |
| 28580 | 0, // zsub2_then_zsub |
| 28581 | 0, // zsub2_then_zsub_hi |
| 28582 | 0, // dsub0_dsub1 |
| 28583 | 0, // dsub0_dsub1_dsub2 |
| 28584 | 0, // dsub1_dsub2 |
| 28585 | 0, // dsub1_dsub2_dsub3 |
| 28586 | 0, // dsub2_dsub3 |
| 28587 | 124, // dsub_qsub1_then_dsub -> QQ |
| 28588 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28589 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28590 | 0, // qsub0_qsub1 |
| 28591 | 0, // qsub0_qsub1_qsub2 |
| 28592 | 0, // qsub1_qsub2 |
| 28593 | 0, // qsub1_qsub2_qsub3 |
| 28594 | 0, // qsub2_qsub3 |
| 28595 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28596 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28597 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28598 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28599 | 0, // x8sub_0_x8sub_1 |
| 28600 | 0, // x8sub_2_x8sub_3 |
| 28601 | 0, // x8sub_4_x8sub_5 |
| 28602 | 0, // x8sub_6_x8sub_7 |
| 28603 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28604 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28605 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28606 | 0, // sub_32_subo64_then_sub_32 |
| 28607 | 0, // dsub_zsub1_then_dsub |
| 28608 | 0, // zsub_zsub1_then_zsub |
| 28609 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28610 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28611 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28612 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28613 | 0, // zsub0_zsub1 |
| 28614 | 0, // zsub0_zsub1_zsub2 |
| 28615 | 0, // zsub1_zsub2 |
| 28616 | 0, // zsub1_zsub2_zsub3 |
| 28617 | 0, // zsub2_zsub3 |
| 28618 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28619 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28620 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28621 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28622 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28623 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28624 | }, |
| 28625 | { // ZPR2 |
| 28626 | 125, // bsub -> ZPR2 |
| 28627 | 125, // dsub -> ZPR2 |
| 28628 | 0, // dsub0 |
| 28629 | 0, // dsub1 |
| 28630 | 0, // dsub2 |
| 28631 | 0, // dsub3 |
| 28632 | 125, // hsub -> ZPR2 |
| 28633 | 0, // qhisub |
| 28634 | 0, // qsub |
| 28635 | 0, // qsub0 |
| 28636 | 0, // qsub1 |
| 28637 | 0, // qsub2 |
| 28638 | 0, // qsub3 |
| 28639 | 125, // ssub -> ZPR2 |
| 28640 | 0, // sub_32 |
| 28641 | 0, // sube32 |
| 28642 | 0, // sube64 |
| 28643 | 0, // subo32 |
| 28644 | 0, // subo64 |
| 28645 | 0, // x8sub_0 |
| 28646 | 0, // x8sub_1 |
| 28647 | 0, // x8sub_2 |
| 28648 | 0, // x8sub_3 |
| 28649 | 0, // x8sub_4 |
| 28650 | 0, // x8sub_5 |
| 28651 | 0, // x8sub_6 |
| 28652 | 0, // x8sub_7 |
| 28653 | 125, // zsub -> ZPR2 |
| 28654 | 125, // zsub0 -> ZPR2 |
| 28655 | 125, // zsub1 -> ZPR2 |
| 28656 | 0, // zsub2 |
| 28657 | 0, // zsub3 |
| 28658 | 125, // zsub_hi -> ZPR2 |
| 28659 | 0, // dsub1_then_bsub |
| 28660 | 0, // dsub1_then_hsub |
| 28661 | 0, // dsub1_then_ssub |
| 28662 | 0, // dsub3_then_bsub |
| 28663 | 0, // dsub3_then_hsub |
| 28664 | 0, // dsub3_then_ssub |
| 28665 | 0, // dsub2_then_bsub |
| 28666 | 0, // dsub2_then_hsub |
| 28667 | 0, // dsub2_then_ssub |
| 28668 | 0, // qsub1_then_bsub |
| 28669 | 0, // qsub1_then_dsub |
| 28670 | 0, // qsub1_then_hsub |
| 28671 | 0, // qsub1_then_ssub |
| 28672 | 0, // qsub3_then_bsub |
| 28673 | 0, // qsub3_then_dsub |
| 28674 | 0, // qsub3_then_hsub |
| 28675 | 0, // qsub3_then_ssub |
| 28676 | 0, // qsub2_then_bsub |
| 28677 | 0, // qsub2_then_dsub |
| 28678 | 0, // qsub2_then_hsub |
| 28679 | 0, // qsub2_then_ssub |
| 28680 | 0, // x8sub_7_then_sub_32 |
| 28681 | 0, // x8sub_6_then_sub_32 |
| 28682 | 0, // x8sub_5_then_sub_32 |
| 28683 | 0, // x8sub_4_then_sub_32 |
| 28684 | 0, // x8sub_3_then_sub_32 |
| 28685 | 0, // x8sub_2_then_sub_32 |
| 28686 | 0, // x8sub_1_then_sub_32 |
| 28687 | 0, // subo64_then_sub_32 |
| 28688 | 125, // zsub1_then_bsub -> ZPR2 |
| 28689 | 125, // zsub1_then_dsub -> ZPR2 |
| 28690 | 125, // zsub1_then_hsub -> ZPR2 |
| 28691 | 125, // zsub1_then_ssub -> ZPR2 |
| 28692 | 125, // zsub1_then_zsub -> ZPR2 |
| 28693 | 125, // zsub1_then_zsub_hi -> ZPR2 |
| 28694 | 0, // zsub3_then_bsub |
| 28695 | 0, // zsub3_then_dsub |
| 28696 | 0, // zsub3_then_hsub |
| 28697 | 0, // zsub3_then_ssub |
| 28698 | 0, // zsub3_then_zsub |
| 28699 | 0, // zsub3_then_zsub_hi |
| 28700 | 0, // zsub2_then_bsub |
| 28701 | 0, // zsub2_then_dsub |
| 28702 | 0, // zsub2_then_hsub |
| 28703 | 0, // zsub2_then_ssub |
| 28704 | 0, // zsub2_then_zsub |
| 28705 | 0, // zsub2_then_zsub_hi |
| 28706 | 0, // dsub0_dsub1 |
| 28707 | 0, // dsub0_dsub1_dsub2 |
| 28708 | 0, // dsub1_dsub2 |
| 28709 | 0, // dsub1_dsub2_dsub3 |
| 28710 | 0, // dsub2_dsub3 |
| 28711 | 0, // dsub_qsub1_then_dsub |
| 28712 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28713 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28714 | 0, // qsub0_qsub1 |
| 28715 | 0, // qsub0_qsub1_qsub2 |
| 28716 | 0, // qsub1_qsub2 |
| 28717 | 0, // qsub1_qsub2_qsub3 |
| 28718 | 0, // qsub2_qsub3 |
| 28719 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28720 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28721 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28722 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28723 | 0, // x8sub_0_x8sub_1 |
| 28724 | 0, // x8sub_2_x8sub_3 |
| 28725 | 0, // x8sub_4_x8sub_5 |
| 28726 | 0, // x8sub_6_x8sub_7 |
| 28727 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28728 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28729 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28730 | 0, // sub_32_subo64_then_sub_32 |
| 28731 | 125, // dsub_zsub1_then_dsub -> ZPR2 |
| 28732 | 125, // zsub_zsub1_then_zsub -> ZPR2 |
| 28733 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28734 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28735 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28736 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28737 | 0, // zsub0_zsub1 |
| 28738 | 0, // zsub0_zsub1_zsub2 |
| 28739 | 0, // zsub1_zsub2 |
| 28740 | 0, // zsub1_zsub2_zsub3 |
| 28741 | 0, // zsub2_zsub3 |
| 28742 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28743 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28744 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28745 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28746 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28747 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28748 | }, |
| 28749 | { // QQ_with_dsub_in_FPR64_lo |
| 28750 | 126, // bsub -> QQ_with_dsub_in_FPR64_lo |
| 28751 | 126, // dsub -> QQ_with_dsub_in_FPR64_lo |
| 28752 | 0, // dsub0 |
| 28753 | 0, // dsub1 |
| 28754 | 0, // dsub2 |
| 28755 | 0, // dsub3 |
| 28756 | 126, // hsub -> QQ_with_dsub_in_FPR64_lo |
| 28757 | 0, // qhisub |
| 28758 | 0, // qsub |
| 28759 | 126, // qsub0 -> QQ_with_dsub_in_FPR64_lo |
| 28760 | 126, // qsub1 -> QQ_with_dsub_in_FPR64_lo |
| 28761 | 0, // qsub2 |
| 28762 | 0, // qsub3 |
| 28763 | 126, // ssub -> QQ_with_dsub_in_FPR64_lo |
| 28764 | 0, // sub_32 |
| 28765 | 0, // sube32 |
| 28766 | 0, // sube64 |
| 28767 | 0, // subo32 |
| 28768 | 0, // subo64 |
| 28769 | 0, // x8sub_0 |
| 28770 | 0, // x8sub_1 |
| 28771 | 0, // x8sub_2 |
| 28772 | 0, // x8sub_3 |
| 28773 | 0, // x8sub_4 |
| 28774 | 0, // x8sub_5 |
| 28775 | 0, // x8sub_6 |
| 28776 | 0, // x8sub_7 |
| 28777 | 0, // zsub |
| 28778 | 0, // zsub0 |
| 28779 | 0, // zsub1 |
| 28780 | 0, // zsub2 |
| 28781 | 0, // zsub3 |
| 28782 | 0, // zsub_hi |
| 28783 | 0, // dsub1_then_bsub |
| 28784 | 0, // dsub1_then_hsub |
| 28785 | 0, // dsub1_then_ssub |
| 28786 | 0, // dsub3_then_bsub |
| 28787 | 0, // dsub3_then_hsub |
| 28788 | 0, // dsub3_then_ssub |
| 28789 | 0, // dsub2_then_bsub |
| 28790 | 0, // dsub2_then_hsub |
| 28791 | 0, // dsub2_then_ssub |
| 28792 | 126, // qsub1_then_bsub -> QQ_with_dsub_in_FPR64_lo |
| 28793 | 126, // qsub1_then_dsub -> QQ_with_dsub_in_FPR64_lo |
| 28794 | 126, // qsub1_then_hsub -> QQ_with_dsub_in_FPR64_lo |
| 28795 | 126, // qsub1_then_ssub -> QQ_with_dsub_in_FPR64_lo |
| 28796 | 0, // qsub3_then_bsub |
| 28797 | 0, // qsub3_then_dsub |
| 28798 | 0, // qsub3_then_hsub |
| 28799 | 0, // qsub3_then_ssub |
| 28800 | 0, // qsub2_then_bsub |
| 28801 | 0, // qsub2_then_dsub |
| 28802 | 0, // qsub2_then_hsub |
| 28803 | 0, // qsub2_then_ssub |
| 28804 | 0, // x8sub_7_then_sub_32 |
| 28805 | 0, // x8sub_6_then_sub_32 |
| 28806 | 0, // x8sub_5_then_sub_32 |
| 28807 | 0, // x8sub_4_then_sub_32 |
| 28808 | 0, // x8sub_3_then_sub_32 |
| 28809 | 0, // x8sub_2_then_sub_32 |
| 28810 | 0, // x8sub_1_then_sub_32 |
| 28811 | 0, // subo64_then_sub_32 |
| 28812 | 0, // zsub1_then_bsub |
| 28813 | 0, // zsub1_then_dsub |
| 28814 | 0, // zsub1_then_hsub |
| 28815 | 0, // zsub1_then_ssub |
| 28816 | 0, // zsub1_then_zsub |
| 28817 | 0, // zsub1_then_zsub_hi |
| 28818 | 0, // zsub3_then_bsub |
| 28819 | 0, // zsub3_then_dsub |
| 28820 | 0, // zsub3_then_hsub |
| 28821 | 0, // zsub3_then_ssub |
| 28822 | 0, // zsub3_then_zsub |
| 28823 | 0, // zsub3_then_zsub_hi |
| 28824 | 0, // zsub2_then_bsub |
| 28825 | 0, // zsub2_then_dsub |
| 28826 | 0, // zsub2_then_hsub |
| 28827 | 0, // zsub2_then_ssub |
| 28828 | 0, // zsub2_then_zsub |
| 28829 | 0, // zsub2_then_zsub_hi |
| 28830 | 0, // dsub0_dsub1 |
| 28831 | 0, // dsub0_dsub1_dsub2 |
| 28832 | 0, // dsub1_dsub2 |
| 28833 | 0, // dsub1_dsub2_dsub3 |
| 28834 | 0, // dsub2_dsub3 |
| 28835 | 126, // dsub_qsub1_then_dsub -> QQ_with_dsub_in_FPR64_lo |
| 28836 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28837 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28838 | 0, // qsub0_qsub1 |
| 28839 | 0, // qsub0_qsub1_qsub2 |
| 28840 | 0, // qsub1_qsub2 |
| 28841 | 0, // qsub1_qsub2_qsub3 |
| 28842 | 0, // qsub2_qsub3 |
| 28843 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28844 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28845 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28846 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28847 | 0, // x8sub_0_x8sub_1 |
| 28848 | 0, // x8sub_2_x8sub_3 |
| 28849 | 0, // x8sub_4_x8sub_5 |
| 28850 | 0, // x8sub_6_x8sub_7 |
| 28851 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28852 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28853 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28854 | 0, // sub_32_subo64_then_sub_32 |
| 28855 | 0, // dsub_zsub1_then_dsub |
| 28856 | 0, // zsub_zsub1_then_zsub |
| 28857 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28858 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28859 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28860 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28861 | 0, // zsub0_zsub1 |
| 28862 | 0, // zsub0_zsub1_zsub2 |
| 28863 | 0, // zsub1_zsub2 |
| 28864 | 0, // zsub1_zsub2_zsub3 |
| 28865 | 0, // zsub2_zsub3 |
| 28866 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28867 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28868 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28869 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28870 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28871 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28872 | }, |
| 28873 | { // QQ_with_qsub1_in_FPR128_lo |
| 28874 | 127, // bsub -> QQ_with_qsub1_in_FPR128_lo |
| 28875 | 127, // dsub -> QQ_with_qsub1_in_FPR128_lo |
| 28876 | 0, // dsub0 |
| 28877 | 0, // dsub1 |
| 28878 | 0, // dsub2 |
| 28879 | 0, // dsub3 |
| 28880 | 127, // hsub -> QQ_with_qsub1_in_FPR128_lo |
| 28881 | 0, // qhisub |
| 28882 | 0, // qsub |
| 28883 | 127, // qsub0 -> QQ_with_qsub1_in_FPR128_lo |
| 28884 | 127, // qsub1 -> QQ_with_qsub1_in_FPR128_lo |
| 28885 | 0, // qsub2 |
| 28886 | 0, // qsub3 |
| 28887 | 127, // ssub -> QQ_with_qsub1_in_FPR128_lo |
| 28888 | 0, // sub_32 |
| 28889 | 0, // sube32 |
| 28890 | 0, // sube64 |
| 28891 | 0, // subo32 |
| 28892 | 0, // subo64 |
| 28893 | 0, // x8sub_0 |
| 28894 | 0, // x8sub_1 |
| 28895 | 0, // x8sub_2 |
| 28896 | 0, // x8sub_3 |
| 28897 | 0, // x8sub_4 |
| 28898 | 0, // x8sub_5 |
| 28899 | 0, // x8sub_6 |
| 28900 | 0, // x8sub_7 |
| 28901 | 0, // zsub |
| 28902 | 0, // zsub0 |
| 28903 | 0, // zsub1 |
| 28904 | 0, // zsub2 |
| 28905 | 0, // zsub3 |
| 28906 | 0, // zsub_hi |
| 28907 | 0, // dsub1_then_bsub |
| 28908 | 0, // dsub1_then_hsub |
| 28909 | 0, // dsub1_then_ssub |
| 28910 | 0, // dsub3_then_bsub |
| 28911 | 0, // dsub3_then_hsub |
| 28912 | 0, // dsub3_then_ssub |
| 28913 | 0, // dsub2_then_bsub |
| 28914 | 0, // dsub2_then_hsub |
| 28915 | 0, // dsub2_then_ssub |
| 28916 | 127, // qsub1_then_bsub -> QQ_with_qsub1_in_FPR128_lo |
| 28917 | 127, // qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo |
| 28918 | 127, // qsub1_then_hsub -> QQ_with_qsub1_in_FPR128_lo |
| 28919 | 127, // qsub1_then_ssub -> QQ_with_qsub1_in_FPR128_lo |
| 28920 | 0, // qsub3_then_bsub |
| 28921 | 0, // qsub3_then_dsub |
| 28922 | 0, // qsub3_then_hsub |
| 28923 | 0, // qsub3_then_ssub |
| 28924 | 0, // qsub2_then_bsub |
| 28925 | 0, // qsub2_then_dsub |
| 28926 | 0, // qsub2_then_hsub |
| 28927 | 0, // qsub2_then_ssub |
| 28928 | 0, // x8sub_7_then_sub_32 |
| 28929 | 0, // x8sub_6_then_sub_32 |
| 28930 | 0, // x8sub_5_then_sub_32 |
| 28931 | 0, // x8sub_4_then_sub_32 |
| 28932 | 0, // x8sub_3_then_sub_32 |
| 28933 | 0, // x8sub_2_then_sub_32 |
| 28934 | 0, // x8sub_1_then_sub_32 |
| 28935 | 0, // subo64_then_sub_32 |
| 28936 | 0, // zsub1_then_bsub |
| 28937 | 0, // zsub1_then_dsub |
| 28938 | 0, // zsub1_then_hsub |
| 28939 | 0, // zsub1_then_ssub |
| 28940 | 0, // zsub1_then_zsub |
| 28941 | 0, // zsub1_then_zsub_hi |
| 28942 | 0, // zsub3_then_bsub |
| 28943 | 0, // zsub3_then_dsub |
| 28944 | 0, // zsub3_then_hsub |
| 28945 | 0, // zsub3_then_ssub |
| 28946 | 0, // zsub3_then_zsub |
| 28947 | 0, // zsub3_then_zsub_hi |
| 28948 | 0, // zsub2_then_bsub |
| 28949 | 0, // zsub2_then_dsub |
| 28950 | 0, // zsub2_then_hsub |
| 28951 | 0, // zsub2_then_ssub |
| 28952 | 0, // zsub2_then_zsub |
| 28953 | 0, // zsub2_then_zsub_hi |
| 28954 | 0, // dsub0_dsub1 |
| 28955 | 0, // dsub0_dsub1_dsub2 |
| 28956 | 0, // dsub1_dsub2 |
| 28957 | 0, // dsub1_dsub2_dsub3 |
| 28958 | 0, // dsub2_dsub3 |
| 28959 | 127, // dsub_qsub1_then_dsub -> QQ_with_qsub1_in_FPR128_lo |
| 28960 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28961 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 28962 | 0, // qsub0_qsub1 |
| 28963 | 0, // qsub0_qsub1_qsub2 |
| 28964 | 0, // qsub1_qsub2 |
| 28965 | 0, // qsub1_qsub2_qsub3 |
| 28966 | 0, // qsub2_qsub3 |
| 28967 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 28968 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 28969 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 28970 | 0, // sub_32_x8sub_1_then_sub_32 |
| 28971 | 0, // x8sub_0_x8sub_1 |
| 28972 | 0, // x8sub_2_x8sub_3 |
| 28973 | 0, // x8sub_4_x8sub_5 |
| 28974 | 0, // x8sub_6_x8sub_7 |
| 28975 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 28976 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 28977 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 28978 | 0, // sub_32_subo64_then_sub_32 |
| 28979 | 0, // dsub_zsub1_then_dsub |
| 28980 | 0, // zsub_zsub1_then_zsub |
| 28981 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28982 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 28983 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28984 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 28985 | 0, // zsub0_zsub1 |
| 28986 | 0, // zsub0_zsub1_zsub2 |
| 28987 | 0, // zsub1_zsub2 |
| 28988 | 0, // zsub1_zsub2_zsub3 |
| 28989 | 0, // zsub2_zsub3 |
| 28990 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 28991 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 28992 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 28993 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 28994 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 28995 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 28996 | }, |
| 28997 | { // ZPR2_with_dsub_in_FPR64_lo |
| 28998 | 128, // bsub -> ZPR2_with_dsub_in_FPR64_lo |
| 28999 | 128, // dsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29000 | 0, // dsub0 |
| 29001 | 0, // dsub1 |
| 29002 | 0, // dsub2 |
| 29003 | 0, // dsub3 |
| 29004 | 128, // hsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29005 | 0, // qhisub |
| 29006 | 0, // qsub |
| 29007 | 0, // qsub0 |
| 29008 | 0, // qsub1 |
| 29009 | 0, // qsub2 |
| 29010 | 0, // qsub3 |
| 29011 | 128, // ssub -> ZPR2_with_dsub_in_FPR64_lo |
| 29012 | 0, // sub_32 |
| 29013 | 0, // sube32 |
| 29014 | 0, // sube64 |
| 29015 | 0, // subo32 |
| 29016 | 0, // subo64 |
| 29017 | 0, // x8sub_0 |
| 29018 | 0, // x8sub_1 |
| 29019 | 0, // x8sub_2 |
| 29020 | 0, // x8sub_3 |
| 29021 | 0, // x8sub_4 |
| 29022 | 0, // x8sub_5 |
| 29023 | 0, // x8sub_6 |
| 29024 | 0, // x8sub_7 |
| 29025 | 128, // zsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29026 | 128, // zsub0 -> ZPR2_with_dsub_in_FPR64_lo |
| 29027 | 128, // zsub1 -> ZPR2_with_dsub_in_FPR64_lo |
| 29028 | 0, // zsub2 |
| 29029 | 0, // zsub3 |
| 29030 | 128, // zsub_hi -> ZPR2_with_dsub_in_FPR64_lo |
| 29031 | 0, // dsub1_then_bsub |
| 29032 | 0, // dsub1_then_hsub |
| 29033 | 0, // dsub1_then_ssub |
| 29034 | 0, // dsub3_then_bsub |
| 29035 | 0, // dsub3_then_hsub |
| 29036 | 0, // dsub3_then_ssub |
| 29037 | 0, // dsub2_then_bsub |
| 29038 | 0, // dsub2_then_hsub |
| 29039 | 0, // dsub2_then_ssub |
| 29040 | 0, // qsub1_then_bsub |
| 29041 | 0, // qsub1_then_dsub |
| 29042 | 0, // qsub1_then_hsub |
| 29043 | 0, // qsub1_then_ssub |
| 29044 | 0, // qsub3_then_bsub |
| 29045 | 0, // qsub3_then_dsub |
| 29046 | 0, // qsub3_then_hsub |
| 29047 | 0, // qsub3_then_ssub |
| 29048 | 0, // qsub2_then_bsub |
| 29049 | 0, // qsub2_then_dsub |
| 29050 | 0, // qsub2_then_hsub |
| 29051 | 0, // qsub2_then_ssub |
| 29052 | 0, // x8sub_7_then_sub_32 |
| 29053 | 0, // x8sub_6_then_sub_32 |
| 29054 | 0, // x8sub_5_then_sub_32 |
| 29055 | 0, // x8sub_4_then_sub_32 |
| 29056 | 0, // x8sub_3_then_sub_32 |
| 29057 | 0, // x8sub_2_then_sub_32 |
| 29058 | 0, // x8sub_1_then_sub_32 |
| 29059 | 0, // subo64_then_sub_32 |
| 29060 | 128, // zsub1_then_bsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29061 | 128, // zsub1_then_dsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29062 | 128, // zsub1_then_hsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29063 | 128, // zsub1_then_ssub -> ZPR2_with_dsub_in_FPR64_lo |
| 29064 | 128, // zsub1_then_zsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29065 | 128, // zsub1_then_zsub_hi -> ZPR2_with_dsub_in_FPR64_lo |
| 29066 | 0, // zsub3_then_bsub |
| 29067 | 0, // zsub3_then_dsub |
| 29068 | 0, // zsub3_then_hsub |
| 29069 | 0, // zsub3_then_ssub |
| 29070 | 0, // zsub3_then_zsub |
| 29071 | 0, // zsub3_then_zsub_hi |
| 29072 | 0, // zsub2_then_bsub |
| 29073 | 0, // zsub2_then_dsub |
| 29074 | 0, // zsub2_then_hsub |
| 29075 | 0, // zsub2_then_ssub |
| 29076 | 0, // zsub2_then_zsub |
| 29077 | 0, // zsub2_then_zsub_hi |
| 29078 | 0, // dsub0_dsub1 |
| 29079 | 0, // dsub0_dsub1_dsub2 |
| 29080 | 0, // dsub1_dsub2 |
| 29081 | 0, // dsub1_dsub2_dsub3 |
| 29082 | 0, // dsub2_dsub3 |
| 29083 | 0, // dsub_qsub1_then_dsub |
| 29084 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29085 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29086 | 0, // qsub0_qsub1 |
| 29087 | 0, // qsub0_qsub1_qsub2 |
| 29088 | 0, // qsub1_qsub2 |
| 29089 | 0, // qsub1_qsub2_qsub3 |
| 29090 | 0, // qsub2_qsub3 |
| 29091 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29092 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29093 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29094 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29095 | 0, // x8sub_0_x8sub_1 |
| 29096 | 0, // x8sub_2_x8sub_3 |
| 29097 | 0, // x8sub_4_x8sub_5 |
| 29098 | 0, // x8sub_6_x8sub_7 |
| 29099 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29100 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29101 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29102 | 0, // sub_32_subo64_then_sub_32 |
| 29103 | 128, // dsub_zsub1_then_dsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29104 | 128, // zsub_zsub1_then_zsub -> ZPR2_with_dsub_in_FPR64_lo |
| 29105 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29106 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29107 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29108 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29109 | 0, // zsub0_zsub1 |
| 29110 | 0, // zsub0_zsub1_zsub2 |
| 29111 | 0, // zsub1_zsub2 |
| 29112 | 0, // zsub1_zsub2_zsub3 |
| 29113 | 0, // zsub2_zsub3 |
| 29114 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29115 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29116 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29117 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29118 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29119 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29120 | }, |
| 29121 | { // ZPR2_with_zsub1_in_ZPR_4b |
| 29122 | 129, // bsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29123 | 129, // dsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29124 | 0, // dsub0 |
| 29125 | 0, // dsub1 |
| 29126 | 0, // dsub2 |
| 29127 | 0, // dsub3 |
| 29128 | 129, // hsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29129 | 0, // qhisub |
| 29130 | 0, // qsub |
| 29131 | 0, // qsub0 |
| 29132 | 0, // qsub1 |
| 29133 | 0, // qsub2 |
| 29134 | 0, // qsub3 |
| 29135 | 129, // ssub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29136 | 0, // sub_32 |
| 29137 | 0, // sube32 |
| 29138 | 0, // sube64 |
| 29139 | 0, // subo32 |
| 29140 | 0, // subo64 |
| 29141 | 0, // x8sub_0 |
| 29142 | 0, // x8sub_1 |
| 29143 | 0, // x8sub_2 |
| 29144 | 0, // x8sub_3 |
| 29145 | 0, // x8sub_4 |
| 29146 | 0, // x8sub_5 |
| 29147 | 0, // x8sub_6 |
| 29148 | 0, // x8sub_7 |
| 29149 | 129, // zsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29150 | 129, // zsub0 -> ZPR2_with_zsub1_in_ZPR_4b |
| 29151 | 129, // zsub1 -> ZPR2_with_zsub1_in_ZPR_4b |
| 29152 | 0, // zsub2 |
| 29153 | 0, // zsub3 |
| 29154 | 129, // zsub_hi -> ZPR2_with_zsub1_in_ZPR_4b |
| 29155 | 0, // dsub1_then_bsub |
| 29156 | 0, // dsub1_then_hsub |
| 29157 | 0, // dsub1_then_ssub |
| 29158 | 0, // dsub3_then_bsub |
| 29159 | 0, // dsub3_then_hsub |
| 29160 | 0, // dsub3_then_ssub |
| 29161 | 0, // dsub2_then_bsub |
| 29162 | 0, // dsub2_then_hsub |
| 29163 | 0, // dsub2_then_ssub |
| 29164 | 0, // qsub1_then_bsub |
| 29165 | 0, // qsub1_then_dsub |
| 29166 | 0, // qsub1_then_hsub |
| 29167 | 0, // qsub1_then_ssub |
| 29168 | 0, // qsub3_then_bsub |
| 29169 | 0, // qsub3_then_dsub |
| 29170 | 0, // qsub3_then_hsub |
| 29171 | 0, // qsub3_then_ssub |
| 29172 | 0, // qsub2_then_bsub |
| 29173 | 0, // qsub2_then_dsub |
| 29174 | 0, // qsub2_then_hsub |
| 29175 | 0, // qsub2_then_ssub |
| 29176 | 0, // x8sub_7_then_sub_32 |
| 29177 | 0, // x8sub_6_then_sub_32 |
| 29178 | 0, // x8sub_5_then_sub_32 |
| 29179 | 0, // x8sub_4_then_sub_32 |
| 29180 | 0, // x8sub_3_then_sub_32 |
| 29181 | 0, // x8sub_2_then_sub_32 |
| 29182 | 0, // x8sub_1_then_sub_32 |
| 29183 | 0, // subo64_then_sub_32 |
| 29184 | 129, // zsub1_then_bsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29185 | 129, // zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29186 | 129, // zsub1_then_hsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29187 | 129, // zsub1_then_ssub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29188 | 129, // zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29189 | 129, // zsub1_then_zsub_hi -> ZPR2_with_zsub1_in_ZPR_4b |
| 29190 | 0, // zsub3_then_bsub |
| 29191 | 0, // zsub3_then_dsub |
| 29192 | 0, // zsub3_then_hsub |
| 29193 | 0, // zsub3_then_ssub |
| 29194 | 0, // zsub3_then_zsub |
| 29195 | 0, // zsub3_then_zsub_hi |
| 29196 | 0, // zsub2_then_bsub |
| 29197 | 0, // zsub2_then_dsub |
| 29198 | 0, // zsub2_then_hsub |
| 29199 | 0, // zsub2_then_ssub |
| 29200 | 0, // zsub2_then_zsub |
| 29201 | 0, // zsub2_then_zsub_hi |
| 29202 | 0, // dsub0_dsub1 |
| 29203 | 0, // dsub0_dsub1_dsub2 |
| 29204 | 0, // dsub1_dsub2 |
| 29205 | 0, // dsub1_dsub2_dsub3 |
| 29206 | 0, // dsub2_dsub3 |
| 29207 | 0, // dsub_qsub1_then_dsub |
| 29208 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29209 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29210 | 0, // qsub0_qsub1 |
| 29211 | 0, // qsub0_qsub1_qsub2 |
| 29212 | 0, // qsub1_qsub2 |
| 29213 | 0, // qsub1_qsub2_qsub3 |
| 29214 | 0, // qsub2_qsub3 |
| 29215 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29216 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29217 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29218 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29219 | 0, // x8sub_0_x8sub_1 |
| 29220 | 0, // x8sub_2_x8sub_3 |
| 29221 | 0, // x8sub_4_x8sub_5 |
| 29222 | 0, // x8sub_6_x8sub_7 |
| 29223 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29224 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29225 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29226 | 0, // sub_32_subo64_then_sub_32 |
| 29227 | 129, // dsub_zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29228 | 129, // zsub_zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_4b |
| 29229 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29230 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29231 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29232 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29233 | 0, // zsub0_zsub1 |
| 29234 | 0, // zsub0_zsub1_zsub2 |
| 29235 | 0, // zsub1_zsub2 |
| 29236 | 0, // zsub1_zsub2_zsub3 |
| 29237 | 0, // zsub2_zsub3 |
| 29238 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29239 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29240 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29241 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29242 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29243 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29244 | }, |
| 29245 | { // QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29246 | 130, // bsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29247 | 130, // dsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29248 | 0, // dsub0 |
| 29249 | 0, // dsub1 |
| 29250 | 0, // dsub2 |
| 29251 | 0, // dsub3 |
| 29252 | 130, // hsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29253 | 0, // qhisub |
| 29254 | 0, // qsub |
| 29255 | 130, // qsub0 -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29256 | 130, // qsub1 -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29257 | 0, // qsub2 |
| 29258 | 0, // qsub3 |
| 29259 | 130, // ssub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29260 | 0, // sub_32 |
| 29261 | 0, // sube32 |
| 29262 | 0, // sube64 |
| 29263 | 0, // subo32 |
| 29264 | 0, // subo64 |
| 29265 | 0, // x8sub_0 |
| 29266 | 0, // x8sub_1 |
| 29267 | 0, // x8sub_2 |
| 29268 | 0, // x8sub_3 |
| 29269 | 0, // x8sub_4 |
| 29270 | 0, // x8sub_5 |
| 29271 | 0, // x8sub_6 |
| 29272 | 0, // x8sub_7 |
| 29273 | 0, // zsub |
| 29274 | 0, // zsub0 |
| 29275 | 0, // zsub1 |
| 29276 | 0, // zsub2 |
| 29277 | 0, // zsub3 |
| 29278 | 0, // zsub_hi |
| 29279 | 0, // dsub1_then_bsub |
| 29280 | 0, // dsub1_then_hsub |
| 29281 | 0, // dsub1_then_ssub |
| 29282 | 0, // dsub3_then_bsub |
| 29283 | 0, // dsub3_then_hsub |
| 29284 | 0, // dsub3_then_ssub |
| 29285 | 0, // dsub2_then_bsub |
| 29286 | 0, // dsub2_then_hsub |
| 29287 | 0, // dsub2_then_ssub |
| 29288 | 130, // qsub1_then_bsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29289 | 130, // qsub1_then_dsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29290 | 130, // qsub1_then_hsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29291 | 130, // qsub1_then_ssub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29292 | 0, // qsub3_then_bsub |
| 29293 | 0, // qsub3_then_dsub |
| 29294 | 0, // qsub3_then_hsub |
| 29295 | 0, // qsub3_then_ssub |
| 29296 | 0, // qsub2_then_bsub |
| 29297 | 0, // qsub2_then_dsub |
| 29298 | 0, // qsub2_then_hsub |
| 29299 | 0, // qsub2_then_ssub |
| 29300 | 0, // x8sub_7_then_sub_32 |
| 29301 | 0, // x8sub_6_then_sub_32 |
| 29302 | 0, // x8sub_5_then_sub_32 |
| 29303 | 0, // x8sub_4_then_sub_32 |
| 29304 | 0, // x8sub_3_then_sub_32 |
| 29305 | 0, // x8sub_2_then_sub_32 |
| 29306 | 0, // x8sub_1_then_sub_32 |
| 29307 | 0, // subo64_then_sub_32 |
| 29308 | 0, // zsub1_then_bsub |
| 29309 | 0, // zsub1_then_dsub |
| 29310 | 0, // zsub1_then_hsub |
| 29311 | 0, // zsub1_then_ssub |
| 29312 | 0, // zsub1_then_zsub |
| 29313 | 0, // zsub1_then_zsub_hi |
| 29314 | 0, // zsub3_then_bsub |
| 29315 | 0, // zsub3_then_dsub |
| 29316 | 0, // zsub3_then_hsub |
| 29317 | 0, // zsub3_then_ssub |
| 29318 | 0, // zsub3_then_zsub |
| 29319 | 0, // zsub3_then_zsub_hi |
| 29320 | 0, // zsub2_then_bsub |
| 29321 | 0, // zsub2_then_dsub |
| 29322 | 0, // zsub2_then_hsub |
| 29323 | 0, // zsub2_then_ssub |
| 29324 | 0, // zsub2_then_zsub |
| 29325 | 0, // zsub2_then_zsub_hi |
| 29326 | 0, // dsub0_dsub1 |
| 29327 | 0, // dsub0_dsub1_dsub2 |
| 29328 | 0, // dsub1_dsub2 |
| 29329 | 0, // dsub1_dsub2_dsub3 |
| 29330 | 0, // dsub2_dsub3 |
| 29331 | 130, // dsub_qsub1_then_dsub -> QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 29332 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29333 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29334 | 0, // qsub0_qsub1 |
| 29335 | 0, // qsub0_qsub1_qsub2 |
| 29336 | 0, // qsub1_qsub2 |
| 29337 | 0, // qsub1_qsub2_qsub3 |
| 29338 | 0, // qsub2_qsub3 |
| 29339 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29340 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29341 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29342 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29343 | 0, // x8sub_0_x8sub_1 |
| 29344 | 0, // x8sub_2_x8sub_3 |
| 29345 | 0, // x8sub_4_x8sub_5 |
| 29346 | 0, // x8sub_6_x8sub_7 |
| 29347 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29348 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29349 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29350 | 0, // sub_32_subo64_then_sub_32 |
| 29351 | 0, // dsub_zsub1_then_dsub |
| 29352 | 0, // zsub_zsub1_then_zsub |
| 29353 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29354 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29355 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29356 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29357 | 0, // zsub0_zsub1 |
| 29358 | 0, // zsub0_zsub1_zsub2 |
| 29359 | 0, // zsub1_zsub2 |
| 29360 | 0, // zsub1_zsub2_zsub3 |
| 29361 | 0, // zsub2_zsub3 |
| 29362 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29363 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29364 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29365 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29366 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29367 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29368 | }, |
| 29369 | { // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29370 | 131, // bsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29371 | 131, // dsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29372 | 0, // dsub0 |
| 29373 | 0, // dsub1 |
| 29374 | 0, // dsub2 |
| 29375 | 0, // dsub3 |
| 29376 | 131, // hsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29377 | 0, // qhisub |
| 29378 | 0, // qsub |
| 29379 | 0, // qsub0 |
| 29380 | 0, // qsub1 |
| 29381 | 0, // qsub2 |
| 29382 | 0, // qsub3 |
| 29383 | 131, // ssub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29384 | 0, // sub_32 |
| 29385 | 0, // sube32 |
| 29386 | 0, // sube64 |
| 29387 | 0, // subo32 |
| 29388 | 0, // subo64 |
| 29389 | 0, // x8sub_0 |
| 29390 | 0, // x8sub_1 |
| 29391 | 0, // x8sub_2 |
| 29392 | 0, // x8sub_3 |
| 29393 | 0, // x8sub_4 |
| 29394 | 0, // x8sub_5 |
| 29395 | 0, // x8sub_6 |
| 29396 | 0, // x8sub_7 |
| 29397 | 131, // zsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29398 | 131, // zsub0 -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29399 | 131, // zsub1 -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29400 | 0, // zsub2 |
| 29401 | 0, // zsub3 |
| 29402 | 131, // zsub_hi -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29403 | 0, // dsub1_then_bsub |
| 29404 | 0, // dsub1_then_hsub |
| 29405 | 0, // dsub1_then_ssub |
| 29406 | 0, // dsub3_then_bsub |
| 29407 | 0, // dsub3_then_hsub |
| 29408 | 0, // dsub3_then_ssub |
| 29409 | 0, // dsub2_then_bsub |
| 29410 | 0, // dsub2_then_hsub |
| 29411 | 0, // dsub2_then_ssub |
| 29412 | 0, // qsub1_then_bsub |
| 29413 | 0, // qsub1_then_dsub |
| 29414 | 0, // qsub1_then_hsub |
| 29415 | 0, // qsub1_then_ssub |
| 29416 | 0, // qsub3_then_bsub |
| 29417 | 0, // qsub3_then_dsub |
| 29418 | 0, // qsub3_then_hsub |
| 29419 | 0, // qsub3_then_ssub |
| 29420 | 0, // qsub2_then_bsub |
| 29421 | 0, // qsub2_then_dsub |
| 29422 | 0, // qsub2_then_hsub |
| 29423 | 0, // qsub2_then_ssub |
| 29424 | 0, // x8sub_7_then_sub_32 |
| 29425 | 0, // x8sub_6_then_sub_32 |
| 29426 | 0, // x8sub_5_then_sub_32 |
| 29427 | 0, // x8sub_4_then_sub_32 |
| 29428 | 0, // x8sub_3_then_sub_32 |
| 29429 | 0, // x8sub_2_then_sub_32 |
| 29430 | 0, // x8sub_1_then_sub_32 |
| 29431 | 0, // subo64_then_sub_32 |
| 29432 | 131, // zsub1_then_bsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29433 | 131, // zsub1_then_dsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29434 | 131, // zsub1_then_hsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29435 | 131, // zsub1_then_ssub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29436 | 131, // zsub1_then_zsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29437 | 131, // zsub1_then_zsub_hi -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29438 | 0, // zsub3_then_bsub |
| 29439 | 0, // zsub3_then_dsub |
| 29440 | 0, // zsub3_then_hsub |
| 29441 | 0, // zsub3_then_ssub |
| 29442 | 0, // zsub3_then_zsub |
| 29443 | 0, // zsub3_then_zsub_hi |
| 29444 | 0, // zsub2_then_bsub |
| 29445 | 0, // zsub2_then_dsub |
| 29446 | 0, // zsub2_then_hsub |
| 29447 | 0, // zsub2_then_ssub |
| 29448 | 0, // zsub2_then_zsub |
| 29449 | 0, // zsub2_then_zsub_hi |
| 29450 | 0, // dsub0_dsub1 |
| 29451 | 0, // dsub0_dsub1_dsub2 |
| 29452 | 0, // dsub1_dsub2 |
| 29453 | 0, // dsub1_dsub2_dsub3 |
| 29454 | 0, // dsub2_dsub3 |
| 29455 | 0, // dsub_qsub1_then_dsub |
| 29456 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29457 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29458 | 0, // qsub0_qsub1 |
| 29459 | 0, // qsub0_qsub1_qsub2 |
| 29460 | 0, // qsub1_qsub2 |
| 29461 | 0, // qsub1_qsub2_qsub3 |
| 29462 | 0, // qsub2_qsub3 |
| 29463 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29464 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29465 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29466 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29467 | 0, // x8sub_0_x8sub_1 |
| 29468 | 0, // x8sub_2_x8sub_3 |
| 29469 | 0, // x8sub_4_x8sub_5 |
| 29470 | 0, // x8sub_6_x8sub_7 |
| 29471 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29472 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29473 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29474 | 0, // sub_32_subo64_then_sub_32 |
| 29475 | 131, // dsub_zsub1_then_dsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29476 | 131, // zsub_zsub1_then_zsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 29477 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29478 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29479 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29480 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29481 | 0, // zsub0_zsub1 |
| 29482 | 0, // zsub0_zsub1_zsub2 |
| 29483 | 0, // zsub1_zsub2 |
| 29484 | 0, // zsub1_zsub2_zsub3 |
| 29485 | 0, // zsub2_zsub3 |
| 29486 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29487 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29488 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29489 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29490 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29491 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29492 | }, |
| 29493 | { // ZPR2_with_zsub0_in_ZPR_3b |
| 29494 | 132, // bsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29495 | 132, // dsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29496 | 0, // dsub0 |
| 29497 | 0, // dsub1 |
| 29498 | 0, // dsub2 |
| 29499 | 0, // dsub3 |
| 29500 | 132, // hsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29501 | 0, // qhisub |
| 29502 | 0, // qsub |
| 29503 | 0, // qsub0 |
| 29504 | 0, // qsub1 |
| 29505 | 0, // qsub2 |
| 29506 | 0, // qsub3 |
| 29507 | 132, // ssub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29508 | 0, // sub_32 |
| 29509 | 0, // sube32 |
| 29510 | 0, // sube64 |
| 29511 | 0, // subo32 |
| 29512 | 0, // subo64 |
| 29513 | 0, // x8sub_0 |
| 29514 | 0, // x8sub_1 |
| 29515 | 0, // x8sub_2 |
| 29516 | 0, // x8sub_3 |
| 29517 | 0, // x8sub_4 |
| 29518 | 0, // x8sub_5 |
| 29519 | 0, // x8sub_6 |
| 29520 | 0, // x8sub_7 |
| 29521 | 132, // zsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29522 | 132, // zsub0 -> ZPR2_with_zsub0_in_ZPR_3b |
| 29523 | 132, // zsub1 -> ZPR2_with_zsub0_in_ZPR_3b |
| 29524 | 0, // zsub2 |
| 29525 | 0, // zsub3 |
| 29526 | 132, // zsub_hi -> ZPR2_with_zsub0_in_ZPR_3b |
| 29527 | 0, // dsub1_then_bsub |
| 29528 | 0, // dsub1_then_hsub |
| 29529 | 0, // dsub1_then_ssub |
| 29530 | 0, // dsub3_then_bsub |
| 29531 | 0, // dsub3_then_hsub |
| 29532 | 0, // dsub3_then_ssub |
| 29533 | 0, // dsub2_then_bsub |
| 29534 | 0, // dsub2_then_hsub |
| 29535 | 0, // dsub2_then_ssub |
| 29536 | 0, // qsub1_then_bsub |
| 29537 | 0, // qsub1_then_dsub |
| 29538 | 0, // qsub1_then_hsub |
| 29539 | 0, // qsub1_then_ssub |
| 29540 | 0, // qsub3_then_bsub |
| 29541 | 0, // qsub3_then_dsub |
| 29542 | 0, // qsub3_then_hsub |
| 29543 | 0, // qsub3_then_ssub |
| 29544 | 0, // qsub2_then_bsub |
| 29545 | 0, // qsub2_then_dsub |
| 29546 | 0, // qsub2_then_hsub |
| 29547 | 0, // qsub2_then_ssub |
| 29548 | 0, // x8sub_7_then_sub_32 |
| 29549 | 0, // x8sub_6_then_sub_32 |
| 29550 | 0, // x8sub_5_then_sub_32 |
| 29551 | 0, // x8sub_4_then_sub_32 |
| 29552 | 0, // x8sub_3_then_sub_32 |
| 29553 | 0, // x8sub_2_then_sub_32 |
| 29554 | 0, // x8sub_1_then_sub_32 |
| 29555 | 0, // subo64_then_sub_32 |
| 29556 | 132, // zsub1_then_bsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29557 | 132, // zsub1_then_dsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29558 | 132, // zsub1_then_hsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29559 | 132, // zsub1_then_ssub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29560 | 132, // zsub1_then_zsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29561 | 132, // zsub1_then_zsub_hi -> ZPR2_with_zsub0_in_ZPR_3b |
| 29562 | 0, // zsub3_then_bsub |
| 29563 | 0, // zsub3_then_dsub |
| 29564 | 0, // zsub3_then_hsub |
| 29565 | 0, // zsub3_then_ssub |
| 29566 | 0, // zsub3_then_zsub |
| 29567 | 0, // zsub3_then_zsub_hi |
| 29568 | 0, // zsub2_then_bsub |
| 29569 | 0, // zsub2_then_dsub |
| 29570 | 0, // zsub2_then_hsub |
| 29571 | 0, // zsub2_then_ssub |
| 29572 | 0, // zsub2_then_zsub |
| 29573 | 0, // zsub2_then_zsub_hi |
| 29574 | 0, // dsub0_dsub1 |
| 29575 | 0, // dsub0_dsub1_dsub2 |
| 29576 | 0, // dsub1_dsub2 |
| 29577 | 0, // dsub1_dsub2_dsub3 |
| 29578 | 0, // dsub2_dsub3 |
| 29579 | 0, // dsub_qsub1_then_dsub |
| 29580 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29581 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29582 | 0, // qsub0_qsub1 |
| 29583 | 0, // qsub0_qsub1_qsub2 |
| 29584 | 0, // qsub1_qsub2 |
| 29585 | 0, // qsub1_qsub2_qsub3 |
| 29586 | 0, // qsub2_qsub3 |
| 29587 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29588 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29589 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29590 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29591 | 0, // x8sub_0_x8sub_1 |
| 29592 | 0, // x8sub_2_x8sub_3 |
| 29593 | 0, // x8sub_4_x8sub_5 |
| 29594 | 0, // x8sub_6_x8sub_7 |
| 29595 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29596 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29597 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29598 | 0, // sub_32_subo64_then_sub_32 |
| 29599 | 132, // dsub_zsub1_then_dsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29600 | 132, // zsub_zsub1_then_zsub -> ZPR2_with_zsub0_in_ZPR_3b |
| 29601 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29602 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29603 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29604 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29605 | 0, // zsub0_zsub1 |
| 29606 | 0, // zsub0_zsub1_zsub2 |
| 29607 | 0, // zsub1_zsub2 |
| 29608 | 0, // zsub1_zsub2_zsub3 |
| 29609 | 0, // zsub2_zsub3 |
| 29610 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29611 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29612 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29613 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29614 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29615 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29616 | }, |
| 29617 | { // ZPR2_with_zsub1_in_ZPR_3b |
| 29618 | 133, // bsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29619 | 133, // dsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29620 | 0, // dsub0 |
| 29621 | 0, // dsub1 |
| 29622 | 0, // dsub2 |
| 29623 | 0, // dsub3 |
| 29624 | 133, // hsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29625 | 0, // qhisub |
| 29626 | 0, // qsub |
| 29627 | 0, // qsub0 |
| 29628 | 0, // qsub1 |
| 29629 | 0, // qsub2 |
| 29630 | 0, // qsub3 |
| 29631 | 133, // ssub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29632 | 0, // sub_32 |
| 29633 | 0, // sube32 |
| 29634 | 0, // sube64 |
| 29635 | 0, // subo32 |
| 29636 | 0, // subo64 |
| 29637 | 0, // x8sub_0 |
| 29638 | 0, // x8sub_1 |
| 29639 | 0, // x8sub_2 |
| 29640 | 0, // x8sub_3 |
| 29641 | 0, // x8sub_4 |
| 29642 | 0, // x8sub_5 |
| 29643 | 0, // x8sub_6 |
| 29644 | 0, // x8sub_7 |
| 29645 | 133, // zsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29646 | 133, // zsub0 -> ZPR2_with_zsub1_in_ZPR_3b |
| 29647 | 133, // zsub1 -> ZPR2_with_zsub1_in_ZPR_3b |
| 29648 | 0, // zsub2 |
| 29649 | 0, // zsub3 |
| 29650 | 133, // zsub_hi -> ZPR2_with_zsub1_in_ZPR_3b |
| 29651 | 0, // dsub1_then_bsub |
| 29652 | 0, // dsub1_then_hsub |
| 29653 | 0, // dsub1_then_ssub |
| 29654 | 0, // dsub3_then_bsub |
| 29655 | 0, // dsub3_then_hsub |
| 29656 | 0, // dsub3_then_ssub |
| 29657 | 0, // dsub2_then_bsub |
| 29658 | 0, // dsub2_then_hsub |
| 29659 | 0, // dsub2_then_ssub |
| 29660 | 0, // qsub1_then_bsub |
| 29661 | 0, // qsub1_then_dsub |
| 29662 | 0, // qsub1_then_hsub |
| 29663 | 0, // qsub1_then_ssub |
| 29664 | 0, // qsub3_then_bsub |
| 29665 | 0, // qsub3_then_dsub |
| 29666 | 0, // qsub3_then_hsub |
| 29667 | 0, // qsub3_then_ssub |
| 29668 | 0, // qsub2_then_bsub |
| 29669 | 0, // qsub2_then_dsub |
| 29670 | 0, // qsub2_then_hsub |
| 29671 | 0, // qsub2_then_ssub |
| 29672 | 0, // x8sub_7_then_sub_32 |
| 29673 | 0, // x8sub_6_then_sub_32 |
| 29674 | 0, // x8sub_5_then_sub_32 |
| 29675 | 0, // x8sub_4_then_sub_32 |
| 29676 | 0, // x8sub_3_then_sub_32 |
| 29677 | 0, // x8sub_2_then_sub_32 |
| 29678 | 0, // x8sub_1_then_sub_32 |
| 29679 | 0, // subo64_then_sub_32 |
| 29680 | 133, // zsub1_then_bsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29681 | 133, // zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29682 | 133, // zsub1_then_hsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29683 | 133, // zsub1_then_ssub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29684 | 133, // zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29685 | 133, // zsub1_then_zsub_hi -> ZPR2_with_zsub1_in_ZPR_3b |
| 29686 | 0, // zsub3_then_bsub |
| 29687 | 0, // zsub3_then_dsub |
| 29688 | 0, // zsub3_then_hsub |
| 29689 | 0, // zsub3_then_ssub |
| 29690 | 0, // zsub3_then_zsub |
| 29691 | 0, // zsub3_then_zsub_hi |
| 29692 | 0, // zsub2_then_bsub |
| 29693 | 0, // zsub2_then_dsub |
| 29694 | 0, // zsub2_then_hsub |
| 29695 | 0, // zsub2_then_ssub |
| 29696 | 0, // zsub2_then_zsub |
| 29697 | 0, // zsub2_then_zsub_hi |
| 29698 | 0, // dsub0_dsub1 |
| 29699 | 0, // dsub0_dsub1_dsub2 |
| 29700 | 0, // dsub1_dsub2 |
| 29701 | 0, // dsub1_dsub2_dsub3 |
| 29702 | 0, // dsub2_dsub3 |
| 29703 | 0, // dsub_qsub1_then_dsub |
| 29704 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29705 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29706 | 0, // qsub0_qsub1 |
| 29707 | 0, // qsub0_qsub1_qsub2 |
| 29708 | 0, // qsub1_qsub2 |
| 29709 | 0, // qsub1_qsub2_qsub3 |
| 29710 | 0, // qsub2_qsub3 |
| 29711 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29712 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29713 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29714 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29715 | 0, // x8sub_0_x8sub_1 |
| 29716 | 0, // x8sub_2_x8sub_3 |
| 29717 | 0, // x8sub_4_x8sub_5 |
| 29718 | 0, // x8sub_6_x8sub_7 |
| 29719 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29720 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29721 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29722 | 0, // sub_32_subo64_then_sub_32 |
| 29723 | 133, // dsub_zsub1_then_dsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29724 | 133, // zsub_zsub1_then_zsub -> ZPR2_with_zsub1_in_ZPR_3b |
| 29725 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29726 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29727 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29728 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29729 | 0, // zsub0_zsub1 |
| 29730 | 0, // zsub0_zsub1_zsub2 |
| 29731 | 0, // zsub1_zsub2 |
| 29732 | 0, // zsub1_zsub2_zsub3 |
| 29733 | 0, // zsub2_zsub3 |
| 29734 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29735 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29736 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29737 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29738 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29739 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29740 | }, |
| 29741 | { // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29742 | 134, // bsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29743 | 134, // dsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29744 | 0, // dsub0 |
| 29745 | 0, // dsub1 |
| 29746 | 0, // dsub2 |
| 29747 | 0, // dsub3 |
| 29748 | 134, // hsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29749 | 0, // qhisub |
| 29750 | 0, // qsub |
| 29751 | 0, // qsub0 |
| 29752 | 0, // qsub1 |
| 29753 | 0, // qsub2 |
| 29754 | 0, // qsub3 |
| 29755 | 134, // ssub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29756 | 0, // sub_32 |
| 29757 | 0, // sube32 |
| 29758 | 0, // sube64 |
| 29759 | 0, // subo32 |
| 29760 | 0, // subo64 |
| 29761 | 0, // x8sub_0 |
| 29762 | 0, // x8sub_1 |
| 29763 | 0, // x8sub_2 |
| 29764 | 0, // x8sub_3 |
| 29765 | 0, // x8sub_4 |
| 29766 | 0, // x8sub_5 |
| 29767 | 0, // x8sub_6 |
| 29768 | 0, // x8sub_7 |
| 29769 | 134, // zsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29770 | 134, // zsub0 -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29771 | 134, // zsub1 -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29772 | 0, // zsub2 |
| 29773 | 0, // zsub3 |
| 29774 | 134, // zsub_hi -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29775 | 0, // dsub1_then_bsub |
| 29776 | 0, // dsub1_then_hsub |
| 29777 | 0, // dsub1_then_ssub |
| 29778 | 0, // dsub3_then_bsub |
| 29779 | 0, // dsub3_then_hsub |
| 29780 | 0, // dsub3_then_ssub |
| 29781 | 0, // dsub2_then_bsub |
| 29782 | 0, // dsub2_then_hsub |
| 29783 | 0, // dsub2_then_ssub |
| 29784 | 0, // qsub1_then_bsub |
| 29785 | 0, // qsub1_then_dsub |
| 29786 | 0, // qsub1_then_hsub |
| 29787 | 0, // qsub1_then_ssub |
| 29788 | 0, // qsub3_then_bsub |
| 29789 | 0, // qsub3_then_dsub |
| 29790 | 0, // qsub3_then_hsub |
| 29791 | 0, // qsub3_then_ssub |
| 29792 | 0, // qsub2_then_bsub |
| 29793 | 0, // qsub2_then_dsub |
| 29794 | 0, // qsub2_then_hsub |
| 29795 | 0, // qsub2_then_ssub |
| 29796 | 0, // x8sub_7_then_sub_32 |
| 29797 | 0, // x8sub_6_then_sub_32 |
| 29798 | 0, // x8sub_5_then_sub_32 |
| 29799 | 0, // x8sub_4_then_sub_32 |
| 29800 | 0, // x8sub_3_then_sub_32 |
| 29801 | 0, // x8sub_2_then_sub_32 |
| 29802 | 0, // x8sub_1_then_sub_32 |
| 29803 | 0, // subo64_then_sub_32 |
| 29804 | 134, // zsub1_then_bsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29805 | 134, // zsub1_then_dsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29806 | 134, // zsub1_then_hsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29807 | 134, // zsub1_then_ssub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29808 | 134, // zsub1_then_zsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29809 | 134, // zsub1_then_zsub_hi -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29810 | 0, // zsub3_then_bsub |
| 29811 | 0, // zsub3_then_dsub |
| 29812 | 0, // zsub3_then_hsub |
| 29813 | 0, // zsub3_then_ssub |
| 29814 | 0, // zsub3_then_zsub |
| 29815 | 0, // zsub3_then_zsub_hi |
| 29816 | 0, // zsub2_then_bsub |
| 29817 | 0, // zsub2_then_dsub |
| 29818 | 0, // zsub2_then_hsub |
| 29819 | 0, // zsub2_then_ssub |
| 29820 | 0, // zsub2_then_zsub |
| 29821 | 0, // zsub2_then_zsub_hi |
| 29822 | 0, // dsub0_dsub1 |
| 29823 | 0, // dsub0_dsub1_dsub2 |
| 29824 | 0, // dsub1_dsub2 |
| 29825 | 0, // dsub1_dsub2_dsub3 |
| 29826 | 0, // dsub2_dsub3 |
| 29827 | 0, // dsub_qsub1_then_dsub |
| 29828 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29829 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 29830 | 0, // qsub0_qsub1 |
| 29831 | 0, // qsub0_qsub1_qsub2 |
| 29832 | 0, // qsub1_qsub2 |
| 29833 | 0, // qsub1_qsub2_qsub3 |
| 29834 | 0, // qsub2_qsub3 |
| 29835 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 29836 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29837 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29838 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29839 | 0, // x8sub_0_x8sub_1 |
| 29840 | 0, // x8sub_2_x8sub_3 |
| 29841 | 0, // x8sub_4_x8sub_5 |
| 29842 | 0, // x8sub_6_x8sub_7 |
| 29843 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29844 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29845 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29846 | 0, // sub_32_subo64_then_sub_32 |
| 29847 | 134, // dsub_zsub1_then_dsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29848 | 134, // zsub_zsub1_then_zsub -> ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 29849 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29850 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29851 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29852 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29853 | 0, // zsub0_zsub1 |
| 29854 | 0, // zsub0_zsub1_zsub2 |
| 29855 | 0, // zsub1_zsub2 |
| 29856 | 0, // zsub1_zsub2_zsub3 |
| 29857 | 0, // zsub2_zsub3 |
| 29858 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29859 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29860 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29861 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29862 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29863 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29864 | }, |
| 29865 | { // QQQ |
| 29866 | 135, // bsub -> QQQ |
| 29867 | 135, // dsub -> QQQ |
| 29868 | 0, // dsub0 |
| 29869 | 0, // dsub1 |
| 29870 | 0, // dsub2 |
| 29871 | 0, // dsub3 |
| 29872 | 135, // hsub -> QQQ |
| 29873 | 0, // qhisub |
| 29874 | 0, // qsub |
| 29875 | 135, // qsub0 -> QQQ |
| 29876 | 135, // qsub1 -> QQQ |
| 29877 | 135, // qsub2 -> QQQ |
| 29878 | 0, // qsub3 |
| 29879 | 135, // ssub -> QQQ |
| 29880 | 0, // sub_32 |
| 29881 | 0, // sube32 |
| 29882 | 0, // sube64 |
| 29883 | 0, // subo32 |
| 29884 | 0, // subo64 |
| 29885 | 0, // x8sub_0 |
| 29886 | 0, // x8sub_1 |
| 29887 | 0, // x8sub_2 |
| 29888 | 0, // x8sub_3 |
| 29889 | 0, // x8sub_4 |
| 29890 | 0, // x8sub_5 |
| 29891 | 0, // x8sub_6 |
| 29892 | 0, // x8sub_7 |
| 29893 | 0, // zsub |
| 29894 | 0, // zsub0 |
| 29895 | 0, // zsub1 |
| 29896 | 0, // zsub2 |
| 29897 | 0, // zsub3 |
| 29898 | 0, // zsub_hi |
| 29899 | 0, // dsub1_then_bsub |
| 29900 | 0, // dsub1_then_hsub |
| 29901 | 0, // dsub1_then_ssub |
| 29902 | 0, // dsub3_then_bsub |
| 29903 | 0, // dsub3_then_hsub |
| 29904 | 0, // dsub3_then_ssub |
| 29905 | 0, // dsub2_then_bsub |
| 29906 | 0, // dsub2_then_hsub |
| 29907 | 0, // dsub2_then_ssub |
| 29908 | 135, // qsub1_then_bsub -> QQQ |
| 29909 | 135, // qsub1_then_dsub -> QQQ |
| 29910 | 135, // qsub1_then_hsub -> QQQ |
| 29911 | 135, // qsub1_then_ssub -> QQQ |
| 29912 | 0, // qsub3_then_bsub |
| 29913 | 0, // qsub3_then_dsub |
| 29914 | 0, // qsub3_then_hsub |
| 29915 | 0, // qsub3_then_ssub |
| 29916 | 135, // qsub2_then_bsub -> QQQ |
| 29917 | 135, // qsub2_then_dsub -> QQQ |
| 29918 | 135, // qsub2_then_hsub -> QQQ |
| 29919 | 135, // qsub2_then_ssub -> QQQ |
| 29920 | 0, // x8sub_7_then_sub_32 |
| 29921 | 0, // x8sub_6_then_sub_32 |
| 29922 | 0, // x8sub_5_then_sub_32 |
| 29923 | 0, // x8sub_4_then_sub_32 |
| 29924 | 0, // x8sub_3_then_sub_32 |
| 29925 | 0, // x8sub_2_then_sub_32 |
| 29926 | 0, // x8sub_1_then_sub_32 |
| 29927 | 0, // subo64_then_sub_32 |
| 29928 | 0, // zsub1_then_bsub |
| 29929 | 0, // zsub1_then_dsub |
| 29930 | 0, // zsub1_then_hsub |
| 29931 | 0, // zsub1_then_ssub |
| 29932 | 0, // zsub1_then_zsub |
| 29933 | 0, // zsub1_then_zsub_hi |
| 29934 | 0, // zsub3_then_bsub |
| 29935 | 0, // zsub3_then_dsub |
| 29936 | 0, // zsub3_then_hsub |
| 29937 | 0, // zsub3_then_ssub |
| 29938 | 0, // zsub3_then_zsub |
| 29939 | 0, // zsub3_then_zsub_hi |
| 29940 | 0, // zsub2_then_bsub |
| 29941 | 0, // zsub2_then_dsub |
| 29942 | 0, // zsub2_then_hsub |
| 29943 | 0, // zsub2_then_ssub |
| 29944 | 0, // zsub2_then_zsub |
| 29945 | 0, // zsub2_then_zsub_hi |
| 29946 | 0, // dsub0_dsub1 |
| 29947 | 0, // dsub0_dsub1_dsub2 |
| 29948 | 0, // dsub1_dsub2 |
| 29949 | 0, // dsub1_dsub2_dsub3 |
| 29950 | 0, // dsub2_dsub3 |
| 29951 | 135, // dsub_qsub1_then_dsub -> QQQ |
| 29952 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29953 | 135, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ |
| 29954 | 135, // qsub0_qsub1 -> QQQ |
| 29955 | 0, // qsub0_qsub1_qsub2 |
| 29956 | 135, // qsub1_qsub2 -> QQQ |
| 29957 | 0, // qsub1_qsub2_qsub3 |
| 29958 | 0, // qsub2_qsub3 |
| 29959 | 135, // qsub1_then_dsub_qsub2_then_dsub -> QQQ |
| 29960 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 29961 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 29962 | 0, // sub_32_x8sub_1_then_sub_32 |
| 29963 | 0, // x8sub_0_x8sub_1 |
| 29964 | 0, // x8sub_2_x8sub_3 |
| 29965 | 0, // x8sub_4_x8sub_5 |
| 29966 | 0, // x8sub_6_x8sub_7 |
| 29967 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 29968 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 29969 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 29970 | 0, // sub_32_subo64_then_sub_32 |
| 29971 | 0, // dsub_zsub1_then_dsub |
| 29972 | 0, // zsub_zsub1_then_zsub |
| 29973 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29974 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 29975 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29976 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 29977 | 0, // zsub0_zsub1 |
| 29978 | 0, // zsub0_zsub1_zsub2 |
| 29979 | 0, // zsub1_zsub2 |
| 29980 | 0, // zsub1_zsub2_zsub3 |
| 29981 | 0, // zsub2_zsub3 |
| 29982 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 29983 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 29984 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 29985 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 29986 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 29987 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 29988 | }, |
| 29989 | { // ZPR3 |
| 29990 | 136, // bsub -> ZPR3 |
| 29991 | 136, // dsub -> ZPR3 |
| 29992 | 0, // dsub0 |
| 29993 | 0, // dsub1 |
| 29994 | 0, // dsub2 |
| 29995 | 0, // dsub3 |
| 29996 | 136, // hsub -> ZPR3 |
| 29997 | 0, // qhisub |
| 29998 | 0, // qsub |
| 29999 | 0, // qsub0 |
| 30000 | 0, // qsub1 |
| 30001 | 0, // qsub2 |
| 30002 | 0, // qsub3 |
| 30003 | 136, // ssub -> ZPR3 |
| 30004 | 0, // sub_32 |
| 30005 | 0, // sube32 |
| 30006 | 0, // sube64 |
| 30007 | 0, // subo32 |
| 30008 | 0, // subo64 |
| 30009 | 0, // x8sub_0 |
| 30010 | 0, // x8sub_1 |
| 30011 | 0, // x8sub_2 |
| 30012 | 0, // x8sub_3 |
| 30013 | 0, // x8sub_4 |
| 30014 | 0, // x8sub_5 |
| 30015 | 0, // x8sub_6 |
| 30016 | 0, // x8sub_7 |
| 30017 | 136, // zsub -> ZPR3 |
| 30018 | 136, // zsub0 -> ZPR3 |
| 30019 | 136, // zsub1 -> ZPR3 |
| 30020 | 136, // zsub2 -> ZPR3 |
| 30021 | 0, // zsub3 |
| 30022 | 136, // zsub_hi -> ZPR3 |
| 30023 | 0, // dsub1_then_bsub |
| 30024 | 0, // dsub1_then_hsub |
| 30025 | 0, // dsub1_then_ssub |
| 30026 | 0, // dsub3_then_bsub |
| 30027 | 0, // dsub3_then_hsub |
| 30028 | 0, // dsub3_then_ssub |
| 30029 | 0, // dsub2_then_bsub |
| 30030 | 0, // dsub2_then_hsub |
| 30031 | 0, // dsub2_then_ssub |
| 30032 | 0, // qsub1_then_bsub |
| 30033 | 0, // qsub1_then_dsub |
| 30034 | 0, // qsub1_then_hsub |
| 30035 | 0, // qsub1_then_ssub |
| 30036 | 0, // qsub3_then_bsub |
| 30037 | 0, // qsub3_then_dsub |
| 30038 | 0, // qsub3_then_hsub |
| 30039 | 0, // qsub3_then_ssub |
| 30040 | 0, // qsub2_then_bsub |
| 30041 | 0, // qsub2_then_dsub |
| 30042 | 0, // qsub2_then_hsub |
| 30043 | 0, // qsub2_then_ssub |
| 30044 | 0, // x8sub_7_then_sub_32 |
| 30045 | 0, // x8sub_6_then_sub_32 |
| 30046 | 0, // x8sub_5_then_sub_32 |
| 30047 | 0, // x8sub_4_then_sub_32 |
| 30048 | 0, // x8sub_3_then_sub_32 |
| 30049 | 0, // x8sub_2_then_sub_32 |
| 30050 | 0, // x8sub_1_then_sub_32 |
| 30051 | 0, // subo64_then_sub_32 |
| 30052 | 136, // zsub1_then_bsub -> ZPR3 |
| 30053 | 136, // zsub1_then_dsub -> ZPR3 |
| 30054 | 136, // zsub1_then_hsub -> ZPR3 |
| 30055 | 136, // zsub1_then_ssub -> ZPR3 |
| 30056 | 136, // zsub1_then_zsub -> ZPR3 |
| 30057 | 136, // zsub1_then_zsub_hi -> ZPR3 |
| 30058 | 0, // zsub3_then_bsub |
| 30059 | 0, // zsub3_then_dsub |
| 30060 | 0, // zsub3_then_hsub |
| 30061 | 0, // zsub3_then_ssub |
| 30062 | 0, // zsub3_then_zsub |
| 30063 | 0, // zsub3_then_zsub_hi |
| 30064 | 136, // zsub2_then_bsub -> ZPR3 |
| 30065 | 136, // zsub2_then_dsub -> ZPR3 |
| 30066 | 136, // zsub2_then_hsub -> ZPR3 |
| 30067 | 136, // zsub2_then_ssub -> ZPR3 |
| 30068 | 136, // zsub2_then_zsub -> ZPR3 |
| 30069 | 136, // zsub2_then_zsub_hi -> ZPR3 |
| 30070 | 0, // dsub0_dsub1 |
| 30071 | 0, // dsub0_dsub1_dsub2 |
| 30072 | 0, // dsub1_dsub2 |
| 30073 | 0, // dsub1_dsub2_dsub3 |
| 30074 | 0, // dsub2_dsub3 |
| 30075 | 0, // dsub_qsub1_then_dsub |
| 30076 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30077 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 30078 | 0, // qsub0_qsub1 |
| 30079 | 0, // qsub0_qsub1_qsub2 |
| 30080 | 0, // qsub1_qsub2 |
| 30081 | 0, // qsub1_qsub2_qsub3 |
| 30082 | 0, // qsub2_qsub3 |
| 30083 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 30084 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30085 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30086 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30087 | 0, // x8sub_0_x8sub_1 |
| 30088 | 0, // x8sub_2_x8sub_3 |
| 30089 | 0, // x8sub_4_x8sub_5 |
| 30090 | 0, // x8sub_6_x8sub_7 |
| 30091 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30092 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30093 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30094 | 0, // sub_32_subo64_then_sub_32 |
| 30095 | 136, // dsub_zsub1_then_dsub -> ZPR3 |
| 30096 | 136, // zsub_zsub1_then_zsub -> ZPR3 |
| 30097 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30098 | 136, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3 |
| 30099 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30100 | 136, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3 |
| 30101 | 136, // zsub0_zsub1 -> ZPR3 |
| 30102 | 0, // zsub0_zsub1_zsub2 |
| 30103 | 136, // zsub1_zsub2 -> ZPR3 |
| 30104 | 0, // zsub1_zsub2_zsub3 |
| 30105 | 0, // zsub2_zsub3 |
| 30106 | 136, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3 |
| 30107 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30108 | 136, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3 |
| 30109 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30110 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30111 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30112 | }, |
| 30113 | { // QQQ_with_dsub_in_FPR64_lo |
| 30114 | 137, // bsub -> QQQ_with_dsub_in_FPR64_lo |
| 30115 | 137, // dsub -> QQQ_with_dsub_in_FPR64_lo |
| 30116 | 0, // dsub0 |
| 30117 | 0, // dsub1 |
| 30118 | 0, // dsub2 |
| 30119 | 0, // dsub3 |
| 30120 | 137, // hsub -> QQQ_with_dsub_in_FPR64_lo |
| 30121 | 0, // qhisub |
| 30122 | 0, // qsub |
| 30123 | 137, // qsub0 -> QQQ_with_dsub_in_FPR64_lo |
| 30124 | 137, // qsub1 -> QQQ_with_dsub_in_FPR64_lo |
| 30125 | 137, // qsub2 -> QQQ_with_dsub_in_FPR64_lo |
| 30126 | 0, // qsub3 |
| 30127 | 137, // ssub -> QQQ_with_dsub_in_FPR64_lo |
| 30128 | 0, // sub_32 |
| 30129 | 0, // sube32 |
| 30130 | 0, // sube64 |
| 30131 | 0, // subo32 |
| 30132 | 0, // subo64 |
| 30133 | 0, // x8sub_0 |
| 30134 | 0, // x8sub_1 |
| 30135 | 0, // x8sub_2 |
| 30136 | 0, // x8sub_3 |
| 30137 | 0, // x8sub_4 |
| 30138 | 0, // x8sub_5 |
| 30139 | 0, // x8sub_6 |
| 30140 | 0, // x8sub_7 |
| 30141 | 0, // zsub |
| 30142 | 0, // zsub0 |
| 30143 | 0, // zsub1 |
| 30144 | 0, // zsub2 |
| 30145 | 0, // zsub3 |
| 30146 | 0, // zsub_hi |
| 30147 | 0, // dsub1_then_bsub |
| 30148 | 0, // dsub1_then_hsub |
| 30149 | 0, // dsub1_then_ssub |
| 30150 | 0, // dsub3_then_bsub |
| 30151 | 0, // dsub3_then_hsub |
| 30152 | 0, // dsub3_then_ssub |
| 30153 | 0, // dsub2_then_bsub |
| 30154 | 0, // dsub2_then_hsub |
| 30155 | 0, // dsub2_then_ssub |
| 30156 | 137, // qsub1_then_bsub -> QQQ_with_dsub_in_FPR64_lo |
| 30157 | 137, // qsub1_then_dsub -> QQQ_with_dsub_in_FPR64_lo |
| 30158 | 137, // qsub1_then_hsub -> QQQ_with_dsub_in_FPR64_lo |
| 30159 | 137, // qsub1_then_ssub -> QQQ_with_dsub_in_FPR64_lo |
| 30160 | 0, // qsub3_then_bsub |
| 30161 | 0, // qsub3_then_dsub |
| 30162 | 0, // qsub3_then_hsub |
| 30163 | 0, // qsub3_then_ssub |
| 30164 | 137, // qsub2_then_bsub -> QQQ_with_dsub_in_FPR64_lo |
| 30165 | 137, // qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo |
| 30166 | 137, // qsub2_then_hsub -> QQQ_with_dsub_in_FPR64_lo |
| 30167 | 137, // qsub2_then_ssub -> QQQ_with_dsub_in_FPR64_lo |
| 30168 | 0, // x8sub_7_then_sub_32 |
| 30169 | 0, // x8sub_6_then_sub_32 |
| 30170 | 0, // x8sub_5_then_sub_32 |
| 30171 | 0, // x8sub_4_then_sub_32 |
| 30172 | 0, // x8sub_3_then_sub_32 |
| 30173 | 0, // x8sub_2_then_sub_32 |
| 30174 | 0, // x8sub_1_then_sub_32 |
| 30175 | 0, // subo64_then_sub_32 |
| 30176 | 0, // zsub1_then_bsub |
| 30177 | 0, // zsub1_then_dsub |
| 30178 | 0, // zsub1_then_hsub |
| 30179 | 0, // zsub1_then_ssub |
| 30180 | 0, // zsub1_then_zsub |
| 30181 | 0, // zsub1_then_zsub_hi |
| 30182 | 0, // zsub3_then_bsub |
| 30183 | 0, // zsub3_then_dsub |
| 30184 | 0, // zsub3_then_hsub |
| 30185 | 0, // zsub3_then_ssub |
| 30186 | 0, // zsub3_then_zsub |
| 30187 | 0, // zsub3_then_zsub_hi |
| 30188 | 0, // zsub2_then_bsub |
| 30189 | 0, // zsub2_then_dsub |
| 30190 | 0, // zsub2_then_hsub |
| 30191 | 0, // zsub2_then_ssub |
| 30192 | 0, // zsub2_then_zsub |
| 30193 | 0, // zsub2_then_zsub_hi |
| 30194 | 0, // dsub0_dsub1 |
| 30195 | 0, // dsub0_dsub1_dsub2 |
| 30196 | 0, // dsub1_dsub2 |
| 30197 | 0, // dsub1_dsub2_dsub3 |
| 30198 | 0, // dsub2_dsub3 |
| 30199 | 137, // dsub_qsub1_then_dsub -> QQQ_with_dsub_in_FPR64_lo |
| 30200 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30201 | 137, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo |
| 30202 | 137, // qsub0_qsub1 -> QQQ_with_dsub_in_FPR64_lo |
| 30203 | 0, // qsub0_qsub1_qsub2 |
| 30204 | 137, // qsub1_qsub2 -> QQQ_with_dsub_in_FPR64_lo |
| 30205 | 0, // qsub1_qsub2_qsub3 |
| 30206 | 0, // qsub2_qsub3 |
| 30207 | 137, // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo |
| 30208 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30209 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30210 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30211 | 0, // x8sub_0_x8sub_1 |
| 30212 | 0, // x8sub_2_x8sub_3 |
| 30213 | 0, // x8sub_4_x8sub_5 |
| 30214 | 0, // x8sub_6_x8sub_7 |
| 30215 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30216 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30217 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30218 | 0, // sub_32_subo64_then_sub_32 |
| 30219 | 0, // dsub_zsub1_then_dsub |
| 30220 | 0, // zsub_zsub1_then_zsub |
| 30221 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30222 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 30223 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30224 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 30225 | 0, // zsub0_zsub1 |
| 30226 | 0, // zsub0_zsub1_zsub2 |
| 30227 | 0, // zsub1_zsub2 |
| 30228 | 0, // zsub1_zsub2_zsub3 |
| 30229 | 0, // zsub2_zsub3 |
| 30230 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 30231 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30232 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 30233 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30234 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30235 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30236 | }, |
| 30237 | { // QQQ_with_qsub1_in_FPR128_lo |
| 30238 | 138, // bsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30239 | 138, // dsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30240 | 0, // dsub0 |
| 30241 | 0, // dsub1 |
| 30242 | 0, // dsub2 |
| 30243 | 0, // dsub3 |
| 30244 | 138, // hsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30245 | 0, // qhisub |
| 30246 | 0, // qsub |
| 30247 | 138, // qsub0 -> QQQ_with_qsub1_in_FPR128_lo |
| 30248 | 138, // qsub1 -> QQQ_with_qsub1_in_FPR128_lo |
| 30249 | 138, // qsub2 -> QQQ_with_qsub1_in_FPR128_lo |
| 30250 | 0, // qsub3 |
| 30251 | 138, // ssub -> QQQ_with_qsub1_in_FPR128_lo |
| 30252 | 0, // sub_32 |
| 30253 | 0, // sube32 |
| 30254 | 0, // sube64 |
| 30255 | 0, // subo32 |
| 30256 | 0, // subo64 |
| 30257 | 0, // x8sub_0 |
| 30258 | 0, // x8sub_1 |
| 30259 | 0, // x8sub_2 |
| 30260 | 0, // x8sub_3 |
| 30261 | 0, // x8sub_4 |
| 30262 | 0, // x8sub_5 |
| 30263 | 0, // x8sub_6 |
| 30264 | 0, // x8sub_7 |
| 30265 | 0, // zsub |
| 30266 | 0, // zsub0 |
| 30267 | 0, // zsub1 |
| 30268 | 0, // zsub2 |
| 30269 | 0, // zsub3 |
| 30270 | 0, // zsub_hi |
| 30271 | 0, // dsub1_then_bsub |
| 30272 | 0, // dsub1_then_hsub |
| 30273 | 0, // dsub1_then_ssub |
| 30274 | 0, // dsub3_then_bsub |
| 30275 | 0, // dsub3_then_hsub |
| 30276 | 0, // dsub3_then_ssub |
| 30277 | 0, // dsub2_then_bsub |
| 30278 | 0, // dsub2_then_hsub |
| 30279 | 0, // dsub2_then_ssub |
| 30280 | 138, // qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30281 | 138, // qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30282 | 138, // qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30283 | 138, // qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo |
| 30284 | 0, // qsub3_then_bsub |
| 30285 | 0, // qsub3_then_dsub |
| 30286 | 0, // qsub3_then_hsub |
| 30287 | 0, // qsub3_then_ssub |
| 30288 | 138, // qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30289 | 138, // qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30290 | 138, // qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30291 | 138, // qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo |
| 30292 | 0, // x8sub_7_then_sub_32 |
| 30293 | 0, // x8sub_6_then_sub_32 |
| 30294 | 0, // x8sub_5_then_sub_32 |
| 30295 | 0, // x8sub_4_then_sub_32 |
| 30296 | 0, // x8sub_3_then_sub_32 |
| 30297 | 0, // x8sub_2_then_sub_32 |
| 30298 | 0, // x8sub_1_then_sub_32 |
| 30299 | 0, // subo64_then_sub_32 |
| 30300 | 0, // zsub1_then_bsub |
| 30301 | 0, // zsub1_then_dsub |
| 30302 | 0, // zsub1_then_hsub |
| 30303 | 0, // zsub1_then_ssub |
| 30304 | 0, // zsub1_then_zsub |
| 30305 | 0, // zsub1_then_zsub_hi |
| 30306 | 0, // zsub3_then_bsub |
| 30307 | 0, // zsub3_then_dsub |
| 30308 | 0, // zsub3_then_hsub |
| 30309 | 0, // zsub3_then_ssub |
| 30310 | 0, // zsub3_then_zsub |
| 30311 | 0, // zsub3_then_zsub_hi |
| 30312 | 0, // zsub2_then_bsub |
| 30313 | 0, // zsub2_then_dsub |
| 30314 | 0, // zsub2_then_hsub |
| 30315 | 0, // zsub2_then_ssub |
| 30316 | 0, // zsub2_then_zsub |
| 30317 | 0, // zsub2_then_zsub_hi |
| 30318 | 0, // dsub0_dsub1 |
| 30319 | 0, // dsub0_dsub1_dsub2 |
| 30320 | 0, // dsub1_dsub2 |
| 30321 | 0, // dsub1_dsub2_dsub3 |
| 30322 | 0, // dsub2_dsub3 |
| 30323 | 138, // dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30324 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30325 | 138, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30326 | 138, // qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo |
| 30327 | 0, // qsub0_qsub1_qsub2 |
| 30328 | 138, // qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo |
| 30329 | 0, // qsub1_qsub2_qsub3 |
| 30330 | 0, // qsub2_qsub3 |
| 30331 | 138, // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo |
| 30332 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30333 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30334 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30335 | 0, // x8sub_0_x8sub_1 |
| 30336 | 0, // x8sub_2_x8sub_3 |
| 30337 | 0, // x8sub_4_x8sub_5 |
| 30338 | 0, // x8sub_6_x8sub_7 |
| 30339 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30340 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30341 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30342 | 0, // sub_32_subo64_then_sub_32 |
| 30343 | 0, // dsub_zsub1_then_dsub |
| 30344 | 0, // zsub_zsub1_then_zsub |
| 30345 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30346 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 30347 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30348 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 30349 | 0, // zsub0_zsub1 |
| 30350 | 0, // zsub0_zsub1_zsub2 |
| 30351 | 0, // zsub1_zsub2 |
| 30352 | 0, // zsub1_zsub2_zsub3 |
| 30353 | 0, // zsub2_zsub3 |
| 30354 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 30355 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30356 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 30357 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30358 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30359 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30360 | }, |
| 30361 | { // QQQ_with_qsub2_in_FPR128_lo |
| 30362 | 139, // bsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30363 | 139, // dsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30364 | 0, // dsub0 |
| 30365 | 0, // dsub1 |
| 30366 | 0, // dsub2 |
| 30367 | 0, // dsub3 |
| 30368 | 139, // hsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30369 | 0, // qhisub |
| 30370 | 0, // qsub |
| 30371 | 139, // qsub0 -> QQQ_with_qsub2_in_FPR128_lo |
| 30372 | 139, // qsub1 -> QQQ_with_qsub2_in_FPR128_lo |
| 30373 | 139, // qsub2 -> QQQ_with_qsub2_in_FPR128_lo |
| 30374 | 0, // qsub3 |
| 30375 | 139, // ssub -> QQQ_with_qsub2_in_FPR128_lo |
| 30376 | 0, // sub_32 |
| 30377 | 0, // sube32 |
| 30378 | 0, // sube64 |
| 30379 | 0, // subo32 |
| 30380 | 0, // subo64 |
| 30381 | 0, // x8sub_0 |
| 30382 | 0, // x8sub_1 |
| 30383 | 0, // x8sub_2 |
| 30384 | 0, // x8sub_3 |
| 30385 | 0, // x8sub_4 |
| 30386 | 0, // x8sub_5 |
| 30387 | 0, // x8sub_6 |
| 30388 | 0, // x8sub_7 |
| 30389 | 0, // zsub |
| 30390 | 0, // zsub0 |
| 30391 | 0, // zsub1 |
| 30392 | 0, // zsub2 |
| 30393 | 0, // zsub3 |
| 30394 | 0, // zsub_hi |
| 30395 | 0, // dsub1_then_bsub |
| 30396 | 0, // dsub1_then_hsub |
| 30397 | 0, // dsub1_then_ssub |
| 30398 | 0, // dsub3_then_bsub |
| 30399 | 0, // dsub3_then_hsub |
| 30400 | 0, // dsub3_then_ssub |
| 30401 | 0, // dsub2_then_bsub |
| 30402 | 0, // dsub2_then_hsub |
| 30403 | 0, // dsub2_then_ssub |
| 30404 | 139, // qsub1_then_bsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30405 | 139, // qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30406 | 139, // qsub1_then_hsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30407 | 139, // qsub1_then_ssub -> QQQ_with_qsub2_in_FPR128_lo |
| 30408 | 0, // qsub3_then_bsub |
| 30409 | 0, // qsub3_then_dsub |
| 30410 | 0, // qsub3_then_hsub |
| 30411 | 0, // qsub3_then_ssub |
| 30412 | 139, // qsub2_then_bsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30413 | 139, // qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30414 | 139, // qsub2_then_hsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30415 | 139, // qsub2_then_ssub -> QQQ_with_qsub2_in_FPR128_lo |
| 30416 | 0, // x8sub_7_then_sub_32 |
| 30417 | 0, // x8sub_6_then_sub_32 |
| 30418 | 0, // x8sub_5_then_sub_32 |
| 30419 | 0, // x8sub_4_then_sub_32 |
| 30420 | 0, // x8sub_3_then_sub_32 |
| 30421 | 0, // x8sub_2_then_sub_32 |
| 30422 | 0, // x8sub_1_then_sub_32 |
| 30423 | 0, // subo64_then_sub_32 |
| 30424 | 0, // zsub1_then_bsub |
| 30425 | 0, // zsub1_then_dsub |
| 30426 | 0, // zsub1_then_hsub |
| 30427 | 0, // zsub1_then_ssub |
| 30428 | 0, // zsub1_then_zsub |
| 30429 | 0, // zsub1_then_zsub_hi |
| 30430 | 0, // zsub3_then_bsub |
| 30431 | 0, // zsub3_then_dsub |
| 30432 | 0, // zsub3_then_hsub |
| 30433 | 0, // zsub3_then_ssub |
| 30434 | 0, // zsub3_then_zsub |
| 30435 | 0, // zsub3_then_zsub_hi |
| 30436 | 0, // zsub2_then_bsub |
| 30437 | 0, // zsub2_then_dsub |
| 30438 | 0, // zsub2_then_hsub |
| 30439 | 0, // zsub2_then_ssub |
| 30440 | 0, // zsub2_then_zsub |
| 30441 | 0, // zsub2_then_zsub_hi |
| 30442 | 0, // dsub0_dsub1 |
| 30443 | 0, // dsub0_dsub1_dsub2 |
| 30444 | 0, // dsub1_dsub2 |
| 30445 | 0, // dsub1_dsub2_dsub3 |
| 30446 | 0, // dsub2_dsub3 |
| 30447 | 139, // dsub_qsub1_then_dsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30448 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30449 | 139, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30450 | 139, // qsub0_qsub1 -> QQQ_with_qsub2_in_FPR128_lo |
| 30451 | 0, // qsub0_qsub1_qsub2 |
| 30452 | 139, // qsub1_qsub2 -> QQQ_with_qsub2_in_FPR128_lo |
| 30453 | 0, // qsub1_qsub2_qsub3 |
| 30454 | 0, // qsub2_qsub3 |
| 30455 | 139, // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub2_in_FPR128_lo |
| 30456 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30457 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30458 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30459 | 0, // x8sub_0_x8sub_1 |
| 30460 | 0, // x8sub_2_x8sub_3 |
| 30461 | 0, // x8sub_4_x8sub_5 |
| 30462 | 0, // x8sub_6_x8sub_7 |
| 30463 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30464 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30465 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30466 | 0, // sub_32_subo64_then_sub_32 |
| 30467 | 0, // dsub_zsub1_then_dsub |
| 30468 | 0, // zsub_zsub1_then_zsub |
| 30469 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30470 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 30471 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30472 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 30473 | 0, // zsub0_zsub1 |
| 30474 | 0, // zsub0_zsub1_zsub2 |
| 30475 | 0, // zsub1_zsub2 |
| 30476 | 0, // zsub1_zsub2_zsub3 |
| 30477 | 0, // zsub2_zsub3 |
| 30478 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 30479 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30480 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 30481 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30482 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30483 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30484 | }, |
| 30485 | { // ZPR3_with_dsub_in_FPR64_lo |
| 30486 | 140, // bsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30487 | 140, // dsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30488 | 0, // dsub0 |
| 30489 | 0, // dsub1 |
| 30490 | 0, // dsub2 |
| 30491 | 0, // dsub3 |
| 30492 | 140, // hsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30493 | 0, // qhisub |
| 30494 | 0, // qsub |
| 30495 | 0, // qsub0 |
| 30496 | 0, // qsub1 |
| 30497 | 0, // qsub2 |
| 30498 | 0, // qsub3 |
| 30499 | 140, // ssub -> ZPR3_with_dsub_in_FPR64_lo |
| 30500 | 0, // sub_32 |
| 30501 | 0, // sube32 |
| 30502 | 0, // sube64 |
| 30503 | 0, // subo32 |
| 30504 | 0, // subo64 |
| 30505 | 0, // x8sub_0 |
| 30506 | 0, // x8sub_1 |
| 30507 | 0, // x8sub_2 |
| 30508 | 0, // x8sub_3 |
| 30509 | 0, // x8sub_4 |
| 30510 | 0, // x8sub_5 |
| 30511 | 0, // x8sub_6 |
| 30512 | 0, // x8sub_7 |
| 30513 | 140, // zsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30514 | 140, // zsub0 -> ZPR3_with_dsub_in_FPR64_lo |
| 30515 | 140, // zsub1 -> ZPR3_with_dsub_in_FPR64_lo |
| 30516 | 140, // zsub2 -> ZPR3_with_dsub_in_FPR64_lo |
| 30517 | 0, // zsub3 |
| 30518 | 140, // zsub_hi -> ZPR3_with_dsub_in_FPR64_lo |
| 30519 | 0, // dsub1_then_bsub |
| 30520 | 0, // dsub1_then_hsub |
| 30521 | 0, // dsub1_then_ssub |
| 30522 | 0, // dsub3_then_bsub |
| 30523 | 0, // dsub3_then_hsub |
| 30524 | 0, // dsub3_then_ssub |
| 30525 | 0, // dsub2_then_bsub |
| 30526 | 0, // dsub2_then_hsub |
| 30527 | 0, // dsub2_then_ssub |
| 30528 | 0, // qsub1_then_bsub |
| 30529 | 0, // qsub1_then_dsub |
| 30530 | 0, // qsub1_then_hsub |
| 30531 | 0, // qsub1_then_ssub |
| 30532 | 0, // qsub3_then_bsub |
| 30533 | 0, // qsub3_then_dsub |
| 30534 | 0, // qsub3_then_hsub |
| 30535 | 0, // qsub3_then_ssub |
| 30536 | 0, // qsub2_then_bsub |
| 30537 | 0, // qsub2_then_dsub |
| 30538 | 0, // qsub2_then_hsub |
| 30539 | 0, // qsub2_then_ssub |
| 30540 | 0, // x8sub_7_then_sub_32 |
| 30541 | 0, // x8sub_6_then_sub_32 |
| 30542 | 0, // x8sub_5_then_sub_32 |
| 30543 | 0, // x8sub_4_then_sub_32 |
| 30544 | 0, // x8sub_3_then_sub_32 |
| 30545 | 0, // x8sub_2_then_sub_32 |
| 30546 | 0, // x8sub_1_then_sub_32 |
| 30547 | 0, // subo64_then_sub_32 |
| 30548 | 140, // zsub1_then_bsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30549 | 140, // zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30550 | 140, // zsub1_then_hsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30551 | 140, // zsub1_then_ssub -> ZPR3_with_dsub_in_FPR64_lo |
| 30552 | 140, // zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30553 | 140, // zsub1_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo |
| 30554 | 0, // zsub3_then_bsub |
| 30555 | 0, // zsub3_then_dsub |
| 30556 | 0, // zsub3_then_hsub |
| 30557 | 0, // zsub3_then_ssub |
| 30558 | 0, // zsub3_then_zsub |
| 30559 | 0, // zsub3_then_zsub_hi |
| 30560 | 140, // zsub2_then_bsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30561 | 140, // zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30562 | 140, // zsub2_then_hsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30563 | 140, // zsub2_then_ssub -> ZPR3_with_dsub_in_FPR64_lo |
| 30564 | 140, // zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30565 | 140, // zsub2_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo |
| 30566 | 0, // dsub0_dsub1 |
| 30567 | 0, // dsub0_dsub1_dsub2 |
| 30568 | 0, // dsub1_dsub2 |
| 30569 | 0, // dsub1_dsub2_dsub3 |
| 30570 | 0, // dsub2_dsub3 |
| 30571 | 0, // dsub_qsub1_then_dsub |
| 30572 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30573 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 30574 | 0, // qsub0_qsub1 |
| 30575 | 0, // qsub0_qsub1_qsub2 |
| 30576 | 0, // qsub1_qsub2 |
| 30577 | 0, // qsub1_qsub2_qsub3 |
| 30578 | 0, // qsub2_qsub3 |
| 30579 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 30580 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30581 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30582 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30583 | 0, // x8sub_0_x8sub_1 |
| 30584 | 0, // x8sub_2_x8sub_3 |
| 30585 | 0, // x8sub_4_x8sub_5 |
| 30586 | 0, // x8sub_6_x8sub_7 |
| 30587 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30588 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30589 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30590 | 0, // sub_32_subo64_then_sub_32 |
| 30591 | 140, // dsub_zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30592 | 140, // zsub_zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30593 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30594 | 140, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30595 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30596 | 140, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30597 | 140, // zsub0_zsub1 -> ZPR3_with_dsub_in_FPR64_lo |
| 30598 | 0, // zsub0_zsub1_zsub2 |
| 30599 | 140, // zsub1_zsub2 -> ZPR3_with_dsub_in_FPR64_lo |
| 30600 | 0, // zsub1_zsub2_zsub3 |
| 30601 | 0, // zsub2_zsub3 |
| 30602 | 140, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30603 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30604 | 140, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo |
| 30605 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30606 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30607 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30608 | }, |
| 30609 | { // ZPR3_with_zsub1_in_ZPR_4b |
| 30610 | 141, // bsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30611 | 141, // dsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30612 | 0, // dsub0 |
| 30613 | 0, // dsub1 |
| 30614 | 0, // dsub2 |
| 30615 | 0, // dsub3 |
| 30616 | 141, // hsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30617 | 0, // qhisub |
| 30618 | 0, // qsub |
| 30619 | 0, // qsub0 |
| 30620 | 0, // qsub1 |
| 30621 | 0, // qsub2 |
| 30622 | 0, // qsub3 |
| 30623 | 141, // ssub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30624 | 0, // sub_32 |
| 30625 | 0, // sube32 |
| 30626 | 0, // sube64 |
| 30627 | 0, // subo32 |
| 30628 | 0, // subo64 |
| 30629 | 0, // x8sub_0 |
| 30630 | 0, // x8sub_1 |
| 30631 | 0, // x8sub_2 |
| 30632 | 0, // x8sub_3 |
| 30633 | 0, // x8sub_4 |
| 30634 | 0, // x8sub_5 |
| 30635 | 0, // x8sub_6 |
| 30636 | 0, // x8sub_7 |
| 30637 | 141, // zsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30638 | 141, // zsub0 -> ZPR3_with_zsub1_in_ZPR_4b |
| 30639 | 141, // zsub1 -> ZPR3_with_zsub1_in_ZPR_4b |
| 30640 | 141, // zsub2 -> ZPR3_with_zsub1_in_ZPR_4b |
| 30641 | 0, // zsub3 |
| 30642 | 141, // zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b |
| 30643 | 0, // dsub1_then_bsub |
| 30644 | 0, // dsub1_then_hsub |
| 30645 | 0, // dsub1_then_ssub |
| 30646 | 0, // dsub3_then_bsub |
| 30647 | 0, // dsub3_then_hsub |
| 30648 | 0, // dsub3_then_ssub |
| 30649 | 0, // dsub2_then_bsub |
| 30650 | 0, // dsub2_then_hsub |
| 30651 | 0, // dsub2_then_ssub |
| 30652 | 0, // qsub1_then_bsub |
| 30653 | 0, // qsub1_then_dsub |
| 30654 | 0, // qsub1_then_hsub |
| 30655 | 0, // qsub1_then_ssub |
| 30656 | 0, // qsub3_then_bsub |
| 30657 | 0, // qsub3_then_dsub |
| 30658 | 0, // qsub3_then_hsub |
| 30659 | 0, // qsub3_then_ssub |
| 30660 | 0, // qsub2_then_bsub |
| 30661 | 0, // qsub2_then_dsub |
| 30662 | 0, // qsub2_then_hsub |
| 30663 | 0, // qsub2_then_ssub |
| 30664 | 0, // x8sub_7_then_sub_32 |
| 30665 | 0, // x8sub_6_then_sub_32 |
| 30666 | 0, // x8sub_5_then_sub_32 |
| 30667 | 0, // x8sub_4_then_sub_32 |
| 30668 | 0, // x8sub_3_then_sub_32 |
| 30669 | 0, // x8sub_2_then_sub_32 |
| 30670 | 0, // x8sub_1_then_sub_32 |
| 30671 | 0, // subo64_then_sub_32 |
| 30672 | 141, // zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30673 | 141, // zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30674 | 141, // zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30675 | 141, // zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30676 | 141, // zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30677 | 141, // zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b |
| 30678 | 0, // zsub3_then_bsub |
| 30679 | 0, // zsub3_then_dsub |
| 30680 | 0, // zsub3_then_hsub |
| 30681 | 0, // zsub3_then_ssub |
| 30682 | 0, // zsub3_then_zsub |
| 30683 | 0, // zsub3_then_zsub_hi |
| 30684 | 141, // zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30685 | 141, // zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30686 | 141, // zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30687 | 141, // zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30688 | 141, // zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30689 | 141, // zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b |
| 30690 | 0, // dsub0_dsub1 |
| 30691 | 0, // dsub0_dsub1_dsub2 |
| 30692 | 0, // dsub1_dsub2 |
| 30693 | 0, // dsub1_dsub2_dsub3 |
| 30694 | 0, // dsub2_dsub3 |
| 30695 | 0, // dsub_qsub1_then_dsub |
| 30696 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30697 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 30698 | 0, // qsub0_qsub1 |
| 30699 | 0, // qsub0_qsub1_qsub2 |
| 30700 | 0, // qsub1_qsub2 |
| 30701 | 0, // qsub1_qsub2_qsub3 |
| 30702 | 0, // qsub2_qsub3 |
| 30703 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 30704 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30705 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30706 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30707 | 0, // x8sub_0_x8sub_1 |
| 30708 | 0, // x8sub_2_x8sub_3 |
| 30709 | 0, // x8sub_4_x8sub_5 |
| 30710 | 0, // x8sub_6_x8sub_7 |
| 30711 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30712 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30713 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30714 | 0, // sub_32_subo64_then_sub_32 |
| 30715 | 141, // dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30716 | 141, // zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30717 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30718 | 141, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30719 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30720 | 141, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30721 | 141, // zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_4b |
| 30722 | 0, // zsub0_zsub1_zsub2 |
| 30723 | 141, // zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_4b |
| 30724 | 0, // zsub1_zsub2_zsub3 |
| 30725 | 0, // zsub2_zsub3 |
| 30726 | 141, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30727 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30728 | 141, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b |
| 30729 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30730 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30731 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30732 | }, |
| 30733 | { // ZPR3_with_zsub2_in_ZPR_4b |
| 30734 | 142, // bsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30735 | 142, // dsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30736 | 0, // dsub0 |
| 30737 | 0, // dsub1 |
| 30738 | 0, // dsub2 |
| 30739 | 0, // dsub3 |
| 30740 | 142, // hsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30741 | 0, // qhisub |
| 30742 | 0, // qsub |
| 30743 | 0, // qsub0 |
| 30744 | 0, // qsub1 |
| 30745 | 0, // qsub2 |
| 30746 | 0, // qsub3 |
| 30747 | 142, // ssub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30748 | 0, // sub_32 |
| 30749 | 0, // sube32 |
| 30750 | 0, // sube64 |
| 30751 | 0, // subo32 |
| 30752 | 0, // subo64 |
| 30753 | 0, // x8sub_0 |
| 30754 | 0, // x8sub_1 |
| 30755 | 0, // x8sub_2 |
| 30756 | 0, // x8sub_3 |
| 30757 | 0, // x8sub_4 |
| 30758 | 0, // x8sub_5 |
| 30759 | 0, // x8sub_6 |
| 30760 | 0, // x8sub_7 |
| 30761 | 142, // zsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30762 | 142, // zsub0 -> ZPR3_with_zsub2_in_ZPR_4b |
| 30763 | 142, // zsub1 -> ZPR3_with_zsub2_in_ZPR_4b |
| 30764 | 142, // zsub2 -> ZPR3_with_zsub2_in_ZPR_4b |
| 30765 | 0, // zsub3 |
| 30766 | 142, // zsub_hi -> ZPR3_with_zsub2_in_ZPR_4b |
| 30767 | 0, // dsub1_then_bsub |
| 30768 | 0, // dsub1_then_hsub |
| 30769 | 0, // dsub1_then_ssub |
| 30770 | 0, // dsub3_then_bsub |
| 30771 | 0, // dsub3_then_hsub |
| 30772 | 0, // dsub3_then_ssub |
| 30773 | 0, // dsub2_then_bsub |
| 30774 | 0, // dsub2_then_hsub |
| 30775 | 0, // dsub2_then_ssub |
| 30776 | 0, // qsub1_then_bsub |
| 30777 | 0, // qsub1_then_dsub |
| 30778 | 0, // qsub1_then_hsub |
| 30779 | 0, // qsub1_then_ssub |
| 30780 | 0, // qsub3_then_bsub |
| 30781 | 0, // qsub3_then_dsub |
| 30782 | 0, // qsub3_then_hsub |
| 30783 | 0, // qsub3_then_ssub |
| 30784 | 0, // qsub2_then_bsub |
| 30785 | 0, // qsub2_then_dsub |
| 30786 | 0, // qsub2_then_hsub |
| 30787 | 0, // qsub2_then_ssub |
| 30788 | 0, // x8sub_7_then_sub_32 |
| 30789 | 0, // x8sub_6_then_sub_32 |
| 30790 | 0, // x8sub_5_then_sub_32 |
| 30791 | 0, // x8sub_4_then_sub_32 |
| 30792 | 0, // x8sub_3_then_sub_32 |
| 30793 | 0, // x8sub_2_then_sub_32 |
| 30794 | 0, // x8sub_1_then_sub_32 |
| 30795 | 0, // subo64_then_sub_32 |
| 30796 | 142, // zsub1_then_bsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30797 | 142, // zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30798 | 142, // zsub1_then_hsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30799 | 142, // zsub1_then_ssub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30800 | 142, // zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30801 | 142, // zsub1_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_4b |
| 30802 | 0, // zsub3_then_bsub |
| 30803 | 0, // zsub3_then_dsub |
| 30804 | 0, // zsub3_then_hsub |
| 30805 | 0, // zsub3_then_ssub |
| 30806 | 0, // zsub3_then_zsub |
| 30807 | 0, // zsub3_then_zsub_hi |
| 30808 | 142, // zsub2_then_bsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30809 | 142, // zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30810 | 142, // zsub2_then_hsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30811 | 142, // zsub2_then_ssub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30812 | 142, // zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30813 | 142, // zsub2_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_4b |
| 30814 | 0, // dsub0_dsub1 |
| 30815 | 0, // dsub0_dsub1_dsub2 |
| 30816 | 0, // dsub1_dsub2 |
| 30817 | 0, // dsub1_dsub2_dsub3 |
| 30818 | 0, // dsub2_dsub3 |
| 30819 | 0, // dsub_qsub1_then_dsub |
| 30820 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30821 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 30822 | 0, // qsub0_qsub1 |
| 30823 | 0, // qsub0_qsub1_qsub2 |
| 30824 | 0, // qsub1_qsub2 |
| 30825 | 0, // qsub1_qsub2_qsub3 |
| 30826 | 0, // qsub2_qsub3 |
| 30827 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 30828 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30829 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30830 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30831 | 0, // x8sub_0_x8sub_1 |
| 30832 | 0, // x8sub_2_x8sub_3 |
| 30833 | 0, // x8sub_4_x8sub_5 |
| 30834 | 0, // x8sub_6_x8sub_7 |
| 30835 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30836 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30837 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30838 | 0, // sub_32_subo64_then_sub_32 |
| 30839 | 142, // dsub_zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30840 | 142, // zsub_zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30841 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30842 | 142, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30843 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30844 | 142, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30845 | 142, // zsub0_zsub1 -> ZPR3_with_zsub2_in_ZPR_4b |
| 30846 | 0, // zsub0_zsub1_zsub2 |
| 30847 | 142, // zsub1_zsub2 -> ZPR3_with_zsub2_in_ZPR_4b |
| 30848 | 0, // zsub1_zsub2_zsub3 |
| 30849 | 0, // zsub2_zsub3 |
| 30850 | 142, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30851 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30852 | 142, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_4b |
| 30853 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30854 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30855 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30856 | }, |
| 30857 | { // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30858 | 143, // bsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30859 | 143, // dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30860 | 0, // dsub0 |
| 30861 | 0, // dsub1 |
| 30862 | 0, // dsub2 |
| 30863 | 0, // dsub3 |
| 30864 | 143, // hsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30865 | 0, // qhisub |
| 30866 | 0, // qsub |
| 30867 | 143, // qsub0 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30868 | 143, // qsub1 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30869 | 143, // qsub2 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30870 | 0, // qsub3 |
| 30871 | 143, // ssub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30872 | 0, // sub_32 |
| 30873 | 0, // sube32 |
| 30874 | 0, // sube64 |
| 30875 | 0, // subo32 |
| 30876 | 0, // subo64 |
| 30877 | 0, // x8sub_0 |
| 30878 | 0, // x8sub_1 |
| 30879 | 0, // x8sub_2 |
| 30880 | 0, // x8sub_3 |
| 30881 | 0, // x8sub_4 |
| 30882 | 0, // x8sub_5 |
| 30883 | 0, // x8sub_6 |
| 30884 | 0, // x8sub_7 |
| 30885 | 0, // zsub |
| 30886 | 0, // zsub0 |
| 30887 | 0, // zsub1 |
| 30888 | 0, // zsub2 |
| 30889 | 0, // zsub3 |
| 30890 | 0, // zsub_hi |
| 30891 | 0, // dsub1_then_bsub |
| 30892 | 0, // dsub1_then_hsub |
| 30893 | 0, // dsub1_then_ssub |
| 30894 | 0, // dsub3_then_bsub |
| 30895 | 0, // dsub3_then_hsub |
| 30896 | 0, // dsub3_then_ssub |
| 30897 | 0, // dsub2_then_bsub |
| 30898 | 0, // dsub2_then_hsub |
| 30899 | 0, // dsub2_then_ssub |
| 30900 | 143, // qsub1_then_bsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30901 | 143, // qsub1_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30902 | 143, // qsub1_then_hsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30903 | 143, // qsub1_then_ssub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30904 | 0, // qsub3_then_bsub |
| 30905 | 0, // qsub3_then_dsub |
| 30906 | 0, // qsub3_then_hsub |
| 30907 | 0, // qsub3_then_ssub |
| 30908 | 143, // qsub2_then_bsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30909 | 143, // qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30910 | 143, // qsub2_then_hsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30911 | 143, // qsub2_then_ssub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30912 | 0, // x8sub_7_then_sub_32 |
| 30913 | 0, // x8sub_6_then_sub_32 |
| 30914 | 0, // x8sub_5_then_sub_32 |
| 30915 | 0, // x8sub_4_then_sub_32 |
| 30916 | 0, // x8sub_3_then_sub_32 |
| 30917 | 0, // x8sub_2_then_sub_32 |
| 30918 | 0, // x8sub_1_then_sub_32 |
| 30919 | 0, // subo64_then_sub_32 |
| 30920 | 0, // zsub1_then_bsub |
| 30921 | 0, // zsub1_then_dsub |
| 30922 | 0, // zsub1_then_hsub |
| 30923 | 0, // zsub1_then_ssub |
| 30924 | 0, // zsub1_then_zsub |
| 30925 | 0, // zsub1_then_zsub_hi |
| 30926 | 0, // zsub3_then_bsub |
| 30927 | 0, // zsub3_then_dsub |
| 30928 | 0, // zsub3_then_hsub |
| 30929 | 0, // zsub3_then_ssub |
| 30930 | 0, // zsub3_then_zsub |
| 30931 | 0, // zsub3_then_zsub_hi |
| 30932 | 0, // zsub2_then_bsub |
| 30933 | 0, // zsub2_then_dsub |
| 30934 | 0, // zsub2_then_hsub |
| 30935 | 0, // zsub2_then_ssub |
| 30936 | 0, // zsub2_then_zsub |
| 30937 | 0, // zsub2_then_zsub_hi |
| 30938 | 0, // dsub0_dsub1 |
| 30939 | 0, // dsub0_dsub1_dsub2 |
| 30940 | 0, // dsub1_dsub2 |
| 30941 | 0, // dsub1_dsub2_dsub3 |
| 30942 | 0, // dsub2_dsub3 |
| 30943 | 143, // dsub_qsub1_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30944 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30945 | 143, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30946 | 143, // qsub0_qsub1 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30947 | 0, // qsub0_qsub1_qsub2 |
| 30948 | 143, // qsub1_qsub2 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30949 | 0, // qsub1_qsub2_qsub3 |
| 30950 | 0, // qsub2_qsub3 |
| 30951 | 143, // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 30952 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 30953 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 30954 | 0, // sub_32_x8sub_1_then_sub_32 |
| 30955 | 0, // x8sub_0_x8sub_1 |
| 30956 | 0, // x8sub_2_x8sub_3 |
| 30957 | 0, // x8sub_4_x8sub_5 |
| 30958 | 0, // x8sub_6_x8sub_7 |
| 30959 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 30960 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 30961 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 30962 | 0, // sub_32_subo64_then_sub_32 |
| 30963 | 0, // dsub_zsub1_then_dsub |
| 30964 | 0, // zsub_zsub1_then_zsub |
| 30965 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30966 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 30967 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30968 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 30969 | 0, // zsub0_zsub1 |
| 30970 | 0, // zsub0_zsub1_zsub2 |
| 30971 | 0, // zsub1_zsub2 |
| 30972 | 0, // zsub1_zsub2_zsub3 |
| 30973 | 0, // zsub2_zsub3 |
| 30974 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 30975 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 30976 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 30977 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 30978 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 30979 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 30980 | }, |
| 30981 | { // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30982 | 144, // bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30983 | 144, // dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30984 | 0, // dsub0 |
| 30985 | 0, // dsub1 |
| 30986 | 0, // dsub2 |
| 30987 | 0, // dsub3 |
| 30988 | 144, // hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30989 | 0, // qhisub |
| 30990 | 0, // qsub |
| 30991 | 144, // qsub0 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30992 | 144, // qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30993 | 144, // qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30994 | 0, // qsub3 |
| 30995 | 144, // ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 30996 | 0, // sub_32 |
| 30997 | 0, // sube32 |
| 30998 | 0, // sube64 |
| 30999 | 0, // subo32 |
| 31000 | 0, // subo64 |
| 31001 | 0, // x8sub_0 |
| 31002 | 0, // x8sub_1 |
| 31003 | 0, // x8sub_2 |
| 31004 | 0, // x8sub_3 |
| 31005 | 0, // x8sub_4 |
| 31006 | 0, // x8sub_5 |
| 31007 | 0, // x8sub_6 |
| 31008 | 0, // x8sub_7 |
| 31009 | 0, // zsub |
| 31010 | 0, // zsub0 |
| 31011 | 0, // zsub1 |
| 31012 | 0, // zsub2 |
| 31013 | 0, // zsub3 |
| 31014 | 0, // zsub_hi |
| 31015 | 0, // dsub1_then_bsub |
| 31016 | 0, // dsub1_then_hsub |
| 31017 | 0, // dsub1_then_ssub |
| 31018 | 0, // dsub3_then_bsub |
| 31019 | 0, // dsub3_then_hsub |
| 31020 | 0, // dsub3_then_ssub |
| 31021 | 0, // dsub2_then_bsub |
| 31022 | 0, // dsub2_then_hsub |
| 31023 | 0, // dsub2_then_ssub |
| 31024 | 144, // qsub1_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31025 | 144, // qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31026 | 144, // qsub1_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31027 | 144, // qsub1_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31028 | 0, // qsub3_then_bsub |
| 31029 | 0, // qsub3_then_dsub |
| 31030 | 0, // qsub3_then_hsub |
| 31031 | 0, // qsub3_then_ssub |
| 31032 | 144, // qsub2_then_bsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31033 | 144, // qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31034 | 144, // qsub2_then_hsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31035 | 144, // qsub2_then_ssub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31036 | 0, // x8sub_7_then_sub_32 |
| 31037 | 0, // x8sub_6_then_sub_32 |
| 31038 | 0, // x8sub_5_then_sub_32 |
| 31039 | 0, // x8sub_4_then_sub_32 |
| 31040 | 0, // x8sub_3_then_sub_32 |
| 31041 | 0, // x8sub_2_then_sub_32 |
| 31042 | 0, // x8sub_1_then_sub_32 |
| 31043 | 0, // subo64_then_sub_32 |
| 31044 | 0, // zsub1_then_bsub |
| 31045 | 0, // zsub1_then_dsub |
| 31046 | 0, // zsub1_then_hsub |
| 31047 | 0, // zsub1_then_ssub |
| 31048 | 0, // zsub1_then_zsub |
| 31049 | 0, // zsub1_then_zsub_hi |
| 31050 | 0, // zsub3_then_bsub |
| 31051 | 0, // zsub3_then_dsub |
| 31052 | 0, // zsub3_then_hsub |
| 31053 | 0, // zsub3_then_ssub |
| 31054 | 0, // zsub3_then_zsub |
| 31055 | 0, // zsub3_then_zsub_hi |
| 31056 | 0, // zsub2_then_bsub |
| 31057 | 0, // zsub2_then_dsub |
| 31058 | 0, // zsub2_then_hsub |
| 31059 | 0, // zsub2_then_ssub |
| 31060 | 0, // zsub2_then_zsub |
| 31061 | 0, // zsub2_then_zsub_hi |
| 31062 | 0, // dsub0_dsub1 |
| 31063 | 0, // dsub0_dsub1_dsub2 |
| 31064 | 0, // dsub1_dsub2 |
| 31065 | 0, // dsub1_dsub2_dsub3 |
| 31066 | 0, // dsub2_dsub3 |
| 31067 | 144, // dsub_qsub1_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31068 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31069 | 144, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31070 | 144, // qsub0_qsub1 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31071 | 0, // qsub0_qsub1_qsub2 |
| 31072 | 144, // qsub1_qsub2 -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31073 | 0, // qsub1_qsub2_qsub3 |
| 31074 | 0, // qsub2_qsub3 |
| 31075 | 144, // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31076 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31077 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31078 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31079 | 0, // x8sub_0_x8sub_1 |
| 31080 | 0, // x8sub_2_x8sub_3 |
| 31081 | 0, // x8sub_4_x8sub_5 |
| 31082 | 0, // x8sub_6_x8sub_7 |
| 31083 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31084 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31085 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31086 | 0, // sub_32_subo64_then_sub_32 |
| 31087 | 0, // dsub_zsub1_then_dsub |
| 31088 | 0, // zsub_zsub1_then_zsub |
| 31089 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31090 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 31091 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31092 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 31093 | 0, // zsub0_zsub1 |
| 31094 | 0, // zsub0_zsub1_zsub2 |
| 31095 | 0, // zsub1_zsub2 |
| 31096 | 0, // zsub1_zsub2_zsub3 |
| 31097 | 0, // zsub2_zsub3 |
| 31098 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 31099 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31100 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 31101 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31102 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31103 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31104 | }, |
| 31105 | { // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31106 | 145, // bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31107 | 145, // dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31108 | 0, // dsub0 |
| 31109 | 0, // dsub1 |
| 31110 | 0, // dsub2 |
| 31111 | 0, // dsub3 |
| 31112 | 145, // hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31113 | 0, // qhisub |
| 31114 | 0, // qsub |
| 31115 | 0, // qsub0 |
| 31116 | 0, // qsub1 |
| 31117 | 0, // qsub2 |
| 31118 | 0, // qsub3 |
| 31119 | 145, // ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31120 | 0, // sub_32 |
| 31121 | 0, // sube32 |
| 31122 | 0, // sube64 |
| 31123 | 0, // subo32 |
| 31124 | 0, // subo64 |
| 31125 | 0, // x8sub_0 |
| 31126 | 0, // x8sub_1 |
| 31127 | 0, // x8sub_2 |
| 31128 | 0, // x8sub_3 |
| 31129 | 0, // x8sub_4 |
| 31130 | 0, // x8sub_5 |
| 31131 | 0, // x8sub_6 |
| 31132 | 0, // x8sub_7 |
| 31133 | 145, // zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31134 | 145, // zsub0 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31135 | 145, // zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31136 | 145, // zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31137 | 0, // zsub3 |
| 31138 | 145, // zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31139 | 0, // dsub1_then_bsub |
| 31140 | 0, // dsub1_then_hsub |
| 31141 | 0, // dsub1_then_ssub |
| 31142 | 0, // dsub3_then_bsub |
| 31143 | 0, // dsub3_then_hsub |
| 31144 | 0, // dsub3_then_ssub |
| 31145 | 0, // dsub2_then_bsub |
| 31146 | 0, // dsub2_then_hsub |
| 31147 | 0, // dsub2_then_ssub |
| 31148 | 0, // qsub1_then_bsub |
| 31149 | 0, // qsub1_then_dsub |
| 31150 | 0, // qsub1_then_hsub |
| 31151 | 0, // qsub1_then_ssub |
| 31152 | 0, // qsub3_then_bsub |
| 31153 | 0, // qsub3_then_dsub |
| 31154 | 0, // qsub3_then_hsub |
| 31155 | 0, // qsub3_then_ssub |
| 31156 | 0, // qsub2_then_bsub |
| 31157 | 0, // qsub2_then_dsub |
| 31158 | 0, // qsub2_then_hsub |
| 31159 | 0, // qsub2_then_ssub |
| 31160 | 0, // x8sub_7_then_sub_32 |
| 31161 | 0, // x8sub_6_then_sub_32 |
| 31162 | 0, // x8sub_5_then_sub_32 |
| 31163 | 0, // x8sub_4_then_sub_32 |
| 31164 | 0, // x8sub_3_then_sub_32 |
| 31165 | 0, // x8sub_2_then_sub_32 |
| 31166 | 0, // x8sub_1_then_sub_32 |
| 31167 | 0, // subo64_then_sub_32 |
| 31168 | 145, // zsub1_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31169 | 145, // zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31170 | 145, // zsub1_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31171 | 145, // zsub1_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31172 | 145, // zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31173 | 145, // zsub1_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31174 | 0, // zsub3_then_bsub |
| 31175 | 0, // zsub3_then_dsub |
| 31176 | 0, // zsub3_then_hsub |
| 31177 | 0, // zsub3_then_ssub |
| 31178 | 0, // zsub3_then_zsub |
| 31179 | 0, // zsub3_then_zsub_hi |
| 31180 | 145, // zsub2_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31181 | 145, // zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31182 | 145, // zsub2_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31183 | 145, // zsub2_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31184 | 145, // zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31185 | 145, // zsub2_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31186 | 0, // dsub0_dsub1 |
| 31187 | 0, // dsub0_dsub1_dsub2 |
| 31188 | 0, // dsub1_dsub2 |
| 31189 | 0, // dsub1_dsub2_dsub3 |
| 31190 | 0, // dsub2_dsub3 |
| 31191 | 0, // dsub_qsub1_then_dsub |
| 31192 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31193 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 31194 | 0, // qsub0_qsub1 |
| 31195 | 0, // qsub0_qsub1_qsub2 |
| 31196 | 0, // qsub1_qsub2 |
| 31197 | 0, // qsub1_qsub2_qsub3 |
| 31198 | 0, // qsub2_qsub3 |
| 31199 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 31200 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31201 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31202 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31203 | 0, // x8sub_0_x8sub_1 |
| 31204 | 0, // x8sub_2_x8sub_3 |
| 31205 | 0, // x8sub_4_x8sub_5 |
| 31206 | 0, // x8sub_6_x8sub_7 |
| 31207 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31208 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31209 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31210 | 0, // sub_32_subo64_then_sub_32 |
| 31211 | 145, // dsub_zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31212 | 145, // zsub_zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31213 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31214 | 145, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31215 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31216 | 145, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31217 | 145, // zsub0_zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31218 | 0, // zsub0_zsub1_zsub2 |
| 31219 | 145, // zsub1_zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31220 | 0, // zsub1_zsub2_zsub3 |
| 31221 | 0, // zsub2_zsub3 |
| 31222 | 145, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31223 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31224 | 145, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 31225 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31226 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31227 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31228 | }, |
| 31229 | { // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31230 | 146, // bsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31231 | 146, // dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31232 | 0, // dsub0 |
| 31233 | 0, // dsub1 |
| 31234 | 0, // dsub2 |
| 31235 | 0, // dsub3 |
| 31236 | 146, // hsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31237 | 0, // qhisub |
| 31238 | 0, // qsub |
| 31239 | 0, // qsub0 |
| 31240 | 0, // qsub1 |
| 31241 | 0, // qsub2 |
| 31242 | 0, // qsub3 |
| 31243 | 146, // ssub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31244 | 0, // sub_32 |
| 31245 | 0, // sube32 |
| 31246 | 0, // sube64 |
| 31247 | 0, // subo32 |
| 31248 | 0, // subo64 |
| 31249 | 0, // x8sub_0 |
| 31250 | 0, // x8sub_1 |
| 31251 | 0, // x8sub_2 |
| 31252 | 0, // x8sub_3 |
| 31253 | 0, // x8sub_4 |
| 31254 | 0, // x8sub_5 |
| 31255 | 0, // x8sub_6 |
| 31256 | 0, // x8sub_7 |
| 31257 | 146, // zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31258 | 146, // zsub0 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31259 | 146, // zsub1 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31260 | 146, // zsub2 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31261 | 0, // zsub3 |
| 31262 | 146, // zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31263 | 0, // dsub1_then_bsub |
| 31264 | 0, // dsub1_then_hsub |
| 31265 | 0, // dsub1_then_ssub |
| 31266 | 0, // dsub3_then_bsub |
| 31267 | 0, // dsub3_then_hsub |
| 31268 | 0, // dsub3_then_ssub |
| 31269 | 0, // dsub2_then_bsub |
| 31270 | 0, // dsub2_then_hsub |
| 31271 | 0, // dsub2_then_ssub |
| 31272 | 0, // qsub1_then_bsub |
| 31273 | 0, // qsub1_then_dsub |
| 31274 | 0, // qsub1_then_hsub |
| 31275 | 0, // qsub1_then_ssub |
| 31276 | 0, // qsub3_then_bsub |
| 31277 | 0, // qsub3_then_dsub |
| 31278 | 0, // qsub3_then_hsub |
| 31279 | 0, // qsub3_then_ssub |
| 31280 | 0, // qsub2_then_bsub |
| 31281 | 0, // qsub2_then_dsub |
| 31282 | 0, // qsub2_then_hsub |
| 31283 | 0, // qsub2_then_ssub |
| 31284 | 0, // x8sub_7_then_sub_32 |
| 31285 | 0, // x8sub_6_then_sub_32 |
| 31286 | 0, // x8sub_5_then_sub_32 |
| 31287 | 0, // x8sub_4_then_sub_32 |
| 31288 | 0, // x8sub_3_then_sub_32 |
| 31289 | 0, // x8sub_2_then_sub_32 |
| 31290 | 0, // x8sub_1_then_sub_32 |
| 31291 | 0, // subo64_then_sub_32 |
| 31292 | 146, // zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31293 | 146, // zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31294 | 146, // zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31295 | 146, // zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31296 | 146, // zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31297 | 146, // zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31298 | 0, // zsub3_then_bsub |
| 31299 | 0, // zsub3_then_dsub |
| 31300 | 0, // zsub3_then_hsub |
| 31301 | 0, // zsub3_then_ssub |
| 31302 | 0, // zsub3_then_zsub |
| 31303 | 0, // zsub3_then_zsub_hi |
| 31304 | 146, // zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31305 | 146, // zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31306 | 146, // zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31307 | 146, // zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31308 | 146, // zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31309 | 146, // zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31310 | 0, // dsub0_dsub1 |
| 31311 | 0, // dsub0_dsub1_dsub2 |
| 31312 | 0, // dsub1_dsub2 |
| 31313 | 0, // dsub1_dsub2_dsub3 |
| 31314 | 0, // dsub2_dsub3 |
| 31315 | 0, // dsub_qsub1_then_dsub |
| 31316 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31317 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 31318 | 0, // qsub0_qsub1 |
| 31319 | 0, // qsub0_qsub1_qsub2 |
| 31320 | 0, // qsub1_qsub2 |
| 31321 | 0, // qsub1_qsub2_qsub3 |
| 31322 | 0, // qsub2_qsub3 |
| 31323 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 31324 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31325 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31326 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31327 | 0, // x8sub_0_x8sub_1 |
| 31328 | 0, // x8sub_2_x8sub_3 |
| 31329 | 0, // x8sub_4_x8sub_5 |
| 31330 | 0, // x8sub_6_x8sub_7 |
| 31331 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31332 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31333 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31334 | 0, // sub_32_subo64_then_sub_32 |
| 31335 | 146, // dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31336 | 146, // zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31337 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31338 | 146, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31339 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31340 | 146, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31341 | 146, // zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31342 | 0, // zsub0_zsub1_zsub2 |
| 31343 | 146, // zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31344 | 0, // zsub1_zsub2_zsub3 |
| 31345 | 0, // zsub2_zsub3 |
| 31346 | 146, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31347 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31348 | 146, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31349 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31350 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31351 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31352 | }, |
| 31353 | { // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31354 | 147, // bsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31355 | 147, // dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31356 | 0, // dsub0 |
| 31357 | 0, // dsub1 |
| 31358 | 0, // dsub2 |
| 31359 | 0, // dsub3 |
| 31360 | 147, // hsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31361 | 0, // qhisub |
| 31362 | 0, // qsub |
| 31363 | 147, // qsub0 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31364 | 147, // qsub1 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31365 | 147, // qsub2 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31366 | 0, // qsub3 |
| 31367 | 147, // ssub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31368 | 0, // sub_32 |
| 31369 | 0, // sube32 |
| 31370 | 0, // sube64 |
| 31371 | 0, // subo32 |
| 31372 | 0, // subo64 |
| 31373 | 0, // x8sub_0 |
| 31374 | 0, // x8sub_1 |
| 31375 | 0, // x8sub_2 |
| 31376 | 0, // x8sub_3 |
| 31377 | 0, // x8sub_4 |
| 31378 | 0, // x8sub_5 |
| 31379 | 0, // x8sub_6 |
| 31380 | 0, // x8sub_7 |
| 31381 | 0, // zsub |
| 31382 | 0, // zsub0 |
| 31383 | 0, // zsub1 |
| 31384 | 0, // zsub2 |
| 31385 | 0, // zsub3 |
| 31386 | 0, // zsub_hi |
| 31387 | 0, // dsub1_then_bsub |
| 31388 | 0, // dsub1_then_hsub |
| 31389 | 0, // dsub1_then_ssub |
| 31390 | 0, // dsub3_then_bsub |
| 31391 | 0, // dsub3_then_hsub |
| 31392 | 0, // dsub3_then_ssub |
| 31393 | 0, // dsub2_then_bsub |
| 31394 | 0, // dsub2_then_hsub |
| 31395 | 0, // dsub2_then_ssub |
| 31396 | 147, // qsub1_then_bsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31397 | 147, // qsub1_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31398 | 147, // qsub1_then_hsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31399 | 147, // qsub1_then_ssub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31400 | 0, // qsub3_then_bsub |
| 31401 | 0, // qsub3_then_dsub |
| 31402 | 0, // qsub3_then_hsub |
| 31403 | 0, // qsub3_then_ssub |
| 31404 | 147, // qsub2_then_bsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31405 | 147, // qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31406 | 147, // qsub2_then_hsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31407 | 147, // qsub2_then_ssub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31408 | 0, // x8sub_7_then_sub_32 |
| 31409 | 0, // x8sub_6_then_sub_32 |
| 31410 | 0, // x8sub_5_then_sub_32 |
| 31411 | 0, // x8sub_4_then_sub_32 |
| 31412 | 0, // x8sub_3_then_sub_32 |
| 31413 | 0, // x8sub_2_then_sub_32 |
| 31414 | 0, // x8sub_1_then_sub_32 |
| 31415 | 0, // subo64_then_sub_32 |
| 31416 | 0, // zsub1_then_bsub |
| 31417 | 0, // zsub1_then_dsub |
| 31418 | 0, // zsub1_then_hsub |
| 31419 | 0, // zsub1_then_ssub |
| 31420 | 0, // zsub1_then_zsub |
| 31421 | 0, // zsub1_then_zsub_hi |
| 31422 | 0, // zsub3_then_bsub |
| 31423 | 0, // zsub3_then_dsub |
| 31424 | 0, // zsub3_then_hsub |
| 31425 | 0, // zsub3_then_ssub |
| 31426 | 0, // zsub3_then_zsub |
| 31427 | 0, // zsub3_then_zsub_hi |
| 31428 | 0, // zsub2_then_bsub |
| 31429 | 0, // zsub2_then_dsub |
| 31430 | 0, // zsub2_then_hsub |
| 31431 | 0, // zsub2_then_ssub |
| 31432 | 0, // zsub2_then_zsub |
| 31433 | 0, // zsub2_then_zsub_hi |
| 31434 | 0, // dsub0_dsub1 |
| 31435 | 0, // dsub0_dsub1_dsub2 |
| 31436 | 0, // dsub1_dsub2 |
| 31437 | 0, // dsub1_dsub2_dsub3 |
| 31438 | 0, // dsub2_dsub3 |
| 31439 | 147, // dsub_qsub1_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31440 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31441 | 147, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31442 | 147, // qsub0_qsub1 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31443 | 0, // qsub0_qsub1_qsub2 |
| 31444 | 147, // qsub1_qsub2 -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31445 | 0, // qsub1_qsub2_qsub3 |
| 31446 | 0, // qsub2_qsub3 |
| 31447 | 147, // qsub1_then_dsub_qsub2_then_dsub -> QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 31448 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31449 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31450 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31451 | 0, // x8sub_0_x8sub_1 |
| 31452 | 0, // x8sub_2_x8sub_3 |
| 31453 | 0, // x8sub_4_x8sub_5 |
| 31454 | 0, // x8sub_6_x8sub_7 |
| 31455 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31456 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31457 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31458 | 0, // sub_32_subo64_then_sub_32 |
| 31459 | 0, // dsub_zsub1_then_dsub |
| 31460 | 0, // zsub_zsub1_then_zsub |
| 31461 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31462 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 31463 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31464 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 31465 | 0, // zsub0_zsub1 |
| 31466 | 0, // zsub0_zsub1_zsub2 |
| 31467 | 0, // zsub1_zsub2 |
| 31468 | 0, // zsub1_zsub2_zsub3 |
| 31469 | 0, // zsub2_zsub3 |
| 31470 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 31471 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31472 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 31473 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31474 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31475 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31476 | }, |
| 31477 | { // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31478 | 148, // bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31479 | 148, // dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31480 | 0, // dsub0 |
| 31481 | 0, // dsub1 |
| 31482 | 0, // dsub2 |
| 31483 | 0, // dsub3 |
| 31484 | 148, // hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31485 | 0, // qhisub |
| 31486 | 0, // qsub |
| 31487 | 0, // qsub0 |
| 31488 | 0, // qsub1 |
| 31489 | 0, // qsub2 |
| 31490 | 0, // qsub3 |
| 31491 | 148, // ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31492 | 0, // sub_32 |
| 31493 | 0, // sube32 |
| 31494 | 0, // sube64 |
| 31495 | 0, // subo32 |
| 31496 | 0, // subo64 |
| 31497 | 0, // x8sub_0 |
| 31498 | 0, // x8sub_1 |
| 31499 | 0, // x8sub_2 |
| 31500 | 0, // x8sub_3 |
| 31501 | 0, // x8sub_4 |
| 31502 | 0, // x8sub_5 |
| 31503 | 0, // x8sub_6 |
| 31504 | 0, // x8sub_7 |
| 31505 | 148, // zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31506 | 148, // zsub0 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31507 | 148, // zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31508 | 148, // zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31509 | 0, // zsub3 |
| 31510 | 148, // zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31511 | 0, // dsub1_then_bsub |
| 31512 | 0, // dsub1_then_hsub |
| 31513 | 0, // dsub1_then_ssub |
| 31514 | 0, // dsub3_then_bsub |
| 31515 | 0, // dsub3_then_hsub |
| 31516 | 0, // dsub3_then_ssub |
| 31517 | 0, // dsub2_then_bsub |
| 31518 | 0, // dsub2_then_hsub |
| 31519 | 0, // dsub2_then_ssub |
| 31520 | 0, // qsub1_then_bsub |
| 31521 | 0, // qsub1_then_dsub |
| 31522 | 0, // qsub1_then_hsub |
| 31523 | 0, // qsub1_then_ssub |
| 31524 | 0, // qsub3_then_bsub |
| 31525 | 0, // qsub3_then_dsub |
| 31526 | 0, // qsub3_then_hsub |
| 31527 | 0, // qsub3_then_ssub |
| 31528 | 0, // qsub2_then_bsub |
| 31529 | 0, // qsub2_then_dsub |
| 31530 | 0, // qsub2_then_hsub |
| 31531 | 0, // qsub2_then_ssub |
| 31532 | 0, // x8sub_7_then_sub_32 |
| 31533 | 0, // x8sub_6_then_sub_32 |
| 31534 | 0, // x8sub_5_then_sub_32 |
| 31535 | 0, // x8sub_4_then_sub_32 |
| 31536 | 0, // x8sub_3_then_sub_32 |
| 31537 | 0, // x8sub_2_then_sub_32 |
| 31538 | 0, // x8sub_1_then_sub_32 |
| 31539 | 0, // subo64_then_sub_32 |
| 31540 | 148, // zsub1_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31541 | 148, // zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31542 | 148, // zsub1_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31543 | 148, // zsub1_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31544 | 148, // zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31545 | 148, // zsub1_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31546 | 0, // zsub3_then_bsub |
| 31547 | 0, // zsub3_then_dsub |
| 31548 | 0, // zsub3_then_hsub |
| 31549 | 0, // zsub3_then_ssub |
| 31550 | 0, // zsub3_then_zsub |
| 31551 | 0, // zsub3_then_zsub_hi |
| 31552 | 148, // zsub2_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31553 | 148, // zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31554 | 148, // zsub2_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31555 | 148, // zsub2_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31556 | 148, // zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31557 | 148, // zsub2_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31558 | 0, // dsub0_dsub1 |
| 31559 | 0, // dsub0_dsub1_dsub2 |
| 31560 | 0, // dsub1_dsub2 |
| 31561 | 0, // dsub1_dsub2_dsub3 |
| 31562 | 0, // dsub2_dsub3 |
| 31563 | 0, // dsub_qsub1_then_dsub |
| 31564 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31565 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 31566 | 0, // qsub0_qsub1 |
| 31567 | 0, // qsub0_qsub1_qsub2 |
| 31568 | 0, // qsub1_qsub2 |
| 31569 | 0, // qsub1_qsub2_qsub3 |
| 31570 | 0, // qsub2_qsub3 |
| 31571 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 31572 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31573 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31574 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31575 | 0, // x8sub_0_x8sub_1 |
| 31576 | 0, // x8sub_2_x8sub_3 |
| 31577 | 0, // x8sub_4_x8sub_5 |
| 31578 | 0, // x8sub_6_x8sub_7 |
| 31579 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31580 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31581 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31582 | 0, // sub_32_subo64_then_sub_32 |
| 31583 | 148, // dsub_zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31584 | 148, // zsub_zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31585 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31586 | 148, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31587 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31588 | 148, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31589 | 148, // zsub0_zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31590 | 0, // zsub0_zsub1_zsub2 |
| 31591 | 148, // zsub1_zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31592 | 0, // zsub1_zsub2_zsub3 |
| 31593 | 0, // zsub2_zsub3 |
| 31594 | 148, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31595 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31596 | 148, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 31597 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31598 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31599 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31600 | }, |
| 31601 | { // ZPR3_with_zsub0_in_ZPR_3b |
| 31602 | 149, // bsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31603 | 149, // dsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31604 | 0, // dsub0 |
| 31605 | 0, // dsub1 |
| 31606 | 0, // dsub2 |
| 31607 | 0, // dsub3 |
| 31608 | 149, // hsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31609 | 0, // qhisub |
| 31610 | 0, // qsub |
| 31611 | 0, // qsub0 |
| 31612 | 0, // qsub1 |
| 31613 | 0, // qsub2 |
| 31614 | 0, // qsub3 |
| 31615 | 149, // ssub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31616 | 0, // sub_32 |
| 31617 | 0, // sube32 |
| 31618 | 0, // sube64 |
| 31619 | 0, // subo32 |
| 31620 | 0, // subo64 |
| 31621 | 0, // x8sub_0 |
| 31622 | 0, // x8sub_1 |
| 31623 | 0, // x8sub_2 |
| 31624 | 0, // x8sub_3 |
| 31625 | 0, // x8sub_4 |
| 31626 | 0, // x8sub_5 |
| 31627 | 0, // x8sub_6 |
| 31628 | 0, // x8sub_7 |
| 31629 | 149, // zsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31630 | 149, // zsub0 -> ZPR3_with_zsub0_in_ZPR_3b |
| 31631 | 149, // zsub1 -> ZPR3_with_zsub0_in_ZPR_3b |
| 31632 | 149, // zsub2 -> ZPR3_with_zsub0_in_ZPR_3b |
| 31633 | 0, // zsub3 |
| 31634 | 149, // zsub_hi -> ZPR3_with_zsub0_in_ZPR_3b |
| 31635 | 0, // dsub1_then_bsub |
| 31636 | 0, // dsub1_then_hsub |
| 31637 | 0, // dsub1_then_ssub |
| 31638 | 0, // dsub3_then_bsub |
| 31639 | 0, // dsub3_then_hsub |
| 31640 | 0, // dsub3_then_ssub |
| 31641 | 0, // dsub2_then_bsub |
| 31642 | 0, // dsub2_then_hsub |
| 31643 | 0, // dsub2_then_ssub |
| 31644 | 0, // qsub1_then_bsub |
| 31645 | 0, // qsub1_then_dsub |
| 31646 | 0, // qsub1_then_hsub |
| 31647 | 0, // qsub1_then_ssub |
| 31648 | 0, // qsub3_then_bsub |
| 31649 | 0, // qsub3_then_dsub |
| 31650 | 0, // qsub3_then_hsub |
| 31651 | 0, // qsub3_then_ssub |
| 31652 | 0, // qsub2_then_bsub |
| 31653 | 0, // qsub2_then_dsub |
| 31654 | 0, // qsub2_then_hsub |
| 31655 | 0, // qsub2_then_ssub |
| 31656 | 0, // x8sub_7_then_sub_32 |
| 31657 | 0, // x8sub_6_then_sub_32 |
| 31658 | 0, // x8sub_5_then_sub_32 |
| 31659 | 0, // x8sub_4_then_sub_32 |
| 31660 | 0, // x8sub_3_then_sub_32 |
| 31661 | 0, // x8sub_2_then_sub_32 |
| 31662 | 0, // x8sub_1_then_sub_32 |
| 31663 | 0, // subo64_then_sub_32 |
| 31664 | 149, // zsub1_then_bsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31665 | 149, // zsub1_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31666 | 149, // zsub1_then_hsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31667 | 149, // zsub1_then_ssub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31668 | 149, // zsub1_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31669 | 149, // zsub1_then_zsub_hi -> ZPR3_with_zsub0_in_ZPR_3b |
| 31670 | 0, // zsub3_then_bsub |
| 31671 | 0, // zsub3_then_dsub |
| 31672 | 0, // zsub3_then_hsub |
| 31673 | 0, // zsub3_then_ssub |
| 31674 | 0, // zsub3_then_zsub |
| 31675 | 0, // zsub3_then_zsub_hi |
| 31676 | 149, // zsub2_then_bsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31677 | 149, // zsub2_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31678 | 149, // zsub2_then_hsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31679 | 149, // zsub2_then_ssub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31680 | 149, // zsub2_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31681 | 149, // zsub2_then_zsub_hi -> ZPR3_with_zsub0_in_ZPR_3b |
| 31682 | 0, // dsub0_dsub1 |
| 31683 | 0, // dsub0_dsub1_dsub2 |
| 31684 | 0, // dsub1_dsub2 |
| 31685 | 0, // dsub1_dsub2_dsub3 |
| 31686 | 0, // dsub2_dsub3 |
| 31687 | 0, // dsub_qsub1_then_dsub |
| 31688 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31689 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 31690 | 0, // qsub0_qsub1 |
| 31691 | 0, // qsub0_qsub1_qsub2 |
| 31692 | 0, // qsub1_qsub2 |
| 31693 | 0, // qsub1_qsub2_qsub3 |
| 31694 | 0, // qsub2_qsub3 |
| 31695 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 31696 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31697 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31698 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31699 | 0, // x8sub_0_x8sub_1 |
| 31700 | 0, // x8sub_2_x8sub_3 |
| 31701 | 0, // x8sub_4_x8sub_5 |
| 31702 | 0, // x8sub_6_x8sub_7 |
| 31703 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31704 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31705 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31706 | 0, // sub_32_subo64_then_sub_32 |
| 31707 | 149, // dsub_zsub1_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31708 | 149, // zsub_zsub1_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31709 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31710 | 149, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31711 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31712 | 149, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31713 | 149, // zsub0_zsub1 -> ZPR3_with_zsub0_in_ZPR_3b |
| 31714 | 0, // zsub0_zsub1_zsub2 |
| 31715 | 149, // zsub1_zsub2 -> ZPR3_with_zsub0_in_ZPR_3b |
| 31716 | 0, // zsub1_zsub2_zsub3 |
| 31717 | 0, // zsub2_zsub3 |
| 31718 | 149, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31719 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31720 | 149, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub0_in_ZPR_3b |
| 31721 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31722 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31723 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31724 | }, |
| 31725 | { // ZPR3_with_zsub1_in_ZPR_3b |
| 31726 | 150, // bsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31727 | 150, // dsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31728 | 0, // dsub0 |
| 31729 | 0, // dsub1 |
| 31730 | 0, // dsub2 |
| 31731 | 0, // dsub3 |
| 31732 | 150, // hsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31733 | 0, // qhisub |
| 31734 | 0, // qsub |
| 31735 | 0, // qsub0 |
| 31736 | 0, // qsub1 |
| 31737 | 0, // qsub2 |
| 31738 | 0, // qsub3 |
| 31739 | 150, // ssub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31740 | 0, // sub_32 |
| 31741 | 0, // sube32 |
| 31742 | 0, // sube64 |
| 31743 | 0, // subo32 |
| 31744 | 0, // subo64 |
| 31745 | 0, // x8sub_0 |
| 31746 | 0, // x8sub_1 |
| 31747 | 0, // x8sub_2 |
| 31748 | 0, // x8sub_3 |
| 31749 | 0, // x8sub_4 |
| 31750 | 0, // x8sub_5 |
| 31751 | 0, // x8sub_6 |
| 31752 | 0, // x8sub_7 |
| 31753 | 150, // zsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31754 | 150, // zsub0 -> ZPR3_with_zsub1_in_ZPR_3b |
| 31755 | 150, // zsub1 -> ZPR3_with_zsub1_in_ZPR_3b |
| 31756 | 150, // zsub2 -> ZPR3_with_zsub1_in_ZPR_3b |
| 31757 | 0, // zsub3 |
| 31758 | 150, // zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b |
| 31759 | 0, // dsub1_then_bsub |
| 31760 | 0, // dsub1_then_hsub |
| 31761 | 0, // dsub1_then_ssub |
| 31762 | 0, // dsub3_then_bsub |
| 31763 | 0, // dsub3_then_hsub |
| 31764 | 0, // dsub3_then_ssub |
| 31765 | 0, // dsub2_then_bsub |
| 31766 | 0, // dsub2_then_hsub |
| 31767 | 0, // dsub2_then_ssub |
| 31768 | 0, // qsub1_then_bsub |
| 31769 | 0, // qsub1_then_dsub |
| 31770 | 0, // qsub1_then_hsub |
| 31771 | 0, // qsub1_then_ssub |
| 31772 | 0, // qsub3_then_bsub |
| 31773 | 0, // qsub3_then_dsub |
| 31774 | 0, // qsub3_then_hsub |
| 31775 | 0, // qsub3_then_ssub |
| 31776 | 0, // qsub2_then_bsub |
| 31777 | 0, // qsub2_then_dsub |
| 31778 | 0, // qsub2_then_hsub |
| 31779 | 0, // qsub2_then_ssub |
| 31780 | 0, // x8sub_7_then_sub_32 |
| 31781 | 0, // x8sub_6_then_sub_32 |
| 31782 | 0, // x8sub_5_then_sub_32 |
| 31783 | 0, // x8sub_4_then_sub_32 |
| 31784 | 0, // x8sub_3_then_sub_32 |
| 31785 | 0, // x8sub_2_then_sub_32 |
| 31786 | 0, // x8sub_1_then_sub_32 |
| 31787 | 0, // subo64_then_sub_32 |
| 31788 | 150, // zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31789 | 150, // zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31790 | 150, // zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31791 | 150, // zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31792 | 150, // zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31793 | 150, // zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b |
| 31794 | 0, // zsub3_then_bsub |
| 31795 | 0, // zsub3_then_dsub |
| 31796 | 0, // zsub3_then_hsub |
| 31797 | 0, // zsub3_then_ssub |
| 31798 | 0, // zsub3_then_zsub |
| 31799 | 0, // zsub3_then_zsub_hi |
| 31800 | 150, // zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31801 | 150, // zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31802 | 150, // zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31803 | 150, // zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31804 | 150, // zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31805 | 150, // zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b |
| 31806 | 0, // dsub0_dsub1 |
| 31807 | 0, // dsub0_dsub1_dsub2 |
| 31808 | 0, // dsub1_dsub2 |
| 31809 | 0, // dsub1_dsub2_dsub3 |
| 31810 | 0, // dsub2_dsub3 |
| 31811 | 0, // dsub_qsub1_then_dsub |
| 31812 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31813 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 31814 | 0, // qsub0_qsub1 |
| 31815 | 0, // qsub0_qsub1_qsub2 |
| 31816 | 0, // qsub1_qsub2 |
| 31817 | 0, // qsub1_qsub2_qsub3 |
| 31818 | 0, // qsub2_qsub3 |
| 31819 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 31820 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31821 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31822 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31823 | 0, // x8sub_0_x8sub_1 |
| 31824 | 0, // x8sub_2_x8sub_3 |
| 31825 | 0, // x8sub_4_x8sub_5 |
| 31826 | 0, // x8sub_6_x8sub_7 |
| 31827 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31828 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31829 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31830 | 0, // sub_32_subo64_then_sub_32 |
| 31831 | 150, // dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31832 | 150, // zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31833 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31834 | 150, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31835 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31836 | 150, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31837 | 150, // zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_3b |
| 31838 | 0, // zsub0_zsub1_zsub2 |
| 31839 | 150, // zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_3b |
| 31840 | 0, // zsub1_zsub2_zsub3 |
| 31841 | 0, // zsub2_zsub3 |
| 31842 | 150, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31843 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31844 | 150, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b |
| 31845 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31846 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31847 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31848 | }, |
| 31849 | { // ZPR3_with_zsub2_in_ZPR_3b |
| 31850 | 151, // bsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31851 | 151, // dsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31852 | 0, // dsub0 |
| 31853 | 0, // dsub1 |
| 31854 | 0, // dsub2 |
| 31855 | 0, // dsub3 |
| 31856 | 151, // hsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31857 | 0, // qhisub |
| 31858 | 0, // qsub |
| 31859 | 0, // qsub0 |
| 31860 | 0, // qsub1 |
| 31861 | 0, // qsub2 |
| 31862 | 0, // qsub3 |
| 31863 | 151, // ssub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31864 | 0, // sub_32 |
| 31865 | 0, // sube32 |
| 31866 | 0, // sube64 |
| 31867 | 0, // subo32 |
| 31868 | 0, // subo64 |
| 31869 | 0, // x8sub_0 |
| 31870 | 0, // x8sub_1 |
| 31871 | 0, // x8sub_2 |
| 31872 | 0, // x8sub_3 |
| 31873 | 0, // x8sub_4 |
| 31874 | 0, // x8sub_5 |
| 31875 | 0, // x8sub_6 |
| 31876 | 0, // x8sub_7 |
| 31877 | 151, // zsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31878 | 151, // zsub0 -> ZPR3_with_zsub2_in_ZPR_3b |
| 31879 | 151, // zsub1 -> ZPR3_with_zsub2_in_ZPR_3b |
| 31880 | 151, // zsub2 -> ZPR3_with_zsub2_in_ZPR_3b |
| 31881 | 0, // zsub3 |
| 31882 | 151, // zsub_hi -> ZPR3_with_zsub2_in_ZPR_3b |
| 31883 | 0, // dsub1_then_bsub |
| 31884 | 0, // dsub1_then_hsub |
| 31885 | 0, // dsub1_then_ssub |
| 31886 | 0, // dsub3_then_bsub |
| 31887 | 0, // dsub3_then_hsub |
| 31888 | 0, // dsub3_then_ssub |
| 31889 | 0, // dsub2_then_bsub |
| 31890 | 0, // dsub2_then_hsub |
| 31891 | 0, // dsub2_then_ssub |
| 31892 | 0, // qsub1_then_bsub |
| 31893 | 0, // qsub1_then_dsub |
| 31894 | 0, // qsub1_then_hsub |
| 31895 | 0, // qsub1_then_ssub |
| 31896 | 0, // qsub3_then_bsub |
| 31897 | 0, // qsub3_then_dsub |
| 31898 | 0, // qsub3_then_hsub |
| 31899 | 0, // qsub3_then_ssub |
| 31900 | 0, // qsub2_then_bsub |
| 31901 | 0, // qsub2_then_dsub |
| 31902 | 0, // qsub2_then_hsub |
| 31903 | 0, // qsub2_then_ssub |
| 31904 | 0, // x8sub_7_then_sub_32 |
| 31905 | 0, // x8sub_6_then_sub_32 |
| 31906 | 0, // x8sub_5_then_sub_32 |
| 31907 | 0, // x8sub_4_then_sub_32 |
| 31908 | 0, // x8sub_3_then_sub_32 |
| 31909 | 0, // x8sub_2_then_sub_32 |
| 31910 | 0, // x8sub_1_then_sub_32 |
| 31911 | 0, // subo64_then_sub_32 |
| 31912 | 151, // zsub1_then_bsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31913 | 151, // zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31914 | 151, // zsub1_then_hsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31915 | 151, // zsub1_then_ssub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31916 | 151, // zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31917 | 151, // zsub1_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_3b |
| 31918 | 0, // zsub3_then_bsub |
| 31919 | 0, // zsub3_then_dsub |
| 31920 | 0, // zsub3_then_hsub |
| 31921 | 0, // zsub3_then_ssub |
| 31922 | 0, // zsub3_then_zsub |
| 31923 | 0, // zsub3_then_zsub_hi |
| 31924 | 151, // zsub2_then_bsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31925 | 151, // zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31926 | 151, // zsub2_then_hsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31927 | 151, // zsub2_then_ssub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31928 | 151, // zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31929 | 151, // zsub2_then_zsub_hi -> ZPR3_with_zsub2_in_ZPR_3b |
| 31930 | 0, // dsub0_dsub1 |
| 31931 | 0, // dsub0_dsub1_dsub2 |
| 31932 | 0, // dsub1_dsub2 |
| 31933 | 0, // dsub1_dsub2_dsub3 |
| 31934 | 0, // dsub2_dsub3 |
| 31935 | 0, // dsub_qsub1_then_dsub |
| 31936 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31937 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 31938 | 0, // qsub0_qsub1 |
| 31939 | 0, // qsub0_qsub1_qsub2 |
| 31940 | 0, // qsub1_qsub2 |
| 31941 | 0, // qsub1_qsub2_qsub3 |
| 31942 | 0, // qsub2_qsub3 |
| 31943 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 31944 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 31945 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 31946 | 0, // sub_32_x8sub_1_then_sub_32 |
| 31947 | 0, // x8sub_0_x8sub_1 |
| 31948 | 0, // x8sub_2_x8sub_3 |
| 31949 | 0, // x8sub_4_x8sub_5 |
| 31950 | 0, // x8sub_6_x8sub_7 |
| 31951 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 31952 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 31953 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 31954 | 0, // sub_32_subo64_then_sub_32 |
| 31955 | 151, // dsub_zsub1_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31956 | 151, // zsub_zsub1_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31957 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31958 | 151, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31959 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31960 | 151, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31961 | 151, // zsub0_zsub1 -> ZPR3_with_zsub2_in_ZPR_3b |
| 31962 | 0, // zsub0_zsub1_zsub2 |
| 31963 | 151, // zsub1_zsub2 -> ZPR3_with_zsub2_in_ZPR_3b |
| 31964 | 0, // zsub1_zsub2_zsub3 |
| 31965 | 0, // zsub2_zsub3 |
| 31966 | 151, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31967 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 31968 | 151, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub2_in_ZPR_3b |
| 31969 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 31970 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 31971 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 31972 | }, |
| 31973 | { // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 31974 | 152, // bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 31975 | 152, // dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 31976 | 0, // dsub0 |
| 31977 | 0, // dsub1 |
| 31978 | 0, // dsub2 |
| 31979 | 0, // dsub3 |
| 31980 | 152, // hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 31981 | 0, // qhisub |
| 31982 | 0, // qsub |
| 31983 | 0, // qsub0 |
| 31984 | 0, // qsub1 |
| 31985 | 0, // qsub2 |
| 31986 | 0, // qsub3 |
| 31987 | 152, // ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 31988 | 0, // sub_32 |
| 31989 | 0, // sube32 |
| 31990 | 0, // sube64 |
| 31991 | 0, // subo32 |
| 31992 | 0, // subo64 |
| 31993 | 0, // x8sub_0 |
| 31994 | 0, // x8sub_1 |
| 31995 | 0, // x8sub_2 |
| 31996 | 0, // x8sub_3 |
| 31997 | 0, // x8sub_4 |
| 31998 | 0, // x8sub_5 |
| 31999 | 0, // x8sub_6 |
| 32000 | 0, // x8sub_7 |
| 32001 | 152, // zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32002 | 152, // zsub0 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32003 | 152, // zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32004 | 152, // zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32005 | 0, // zsub3 |
| 32006 | 152, // zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32007 | 0, // dsub1_then_bsub |
| 32008 | 0, // dsub1_then_hsub |
| 32009 | 0, // dsub1_then_ssub |
| 32010 | 0, // dsub3_then_bsub |
| 32011 | 0, // dsub3_then_hsub |
| 32012 | 0, // dsub3_then_ssub |
| 32013 | 0, // dsub2_then_bsub |
| 32014 | 0, // dsub2_then_hsub |
| 32015 | 0, // dsub2_then_ssub |
| 32016 | 0, // qsub1_then_bsub |
| 32017 | 0, // qsub1_then_dsub |
| 32018 | 0, // qsub1_then_hsub |
| 32019 | 0, // qsub1_then_ssub |
| 32020 | 0, // qsub3_then_bsub |
| 32021 | 0, // qsub3_then_dsub |
| 32022 | 0, // qsub3_then_hsub |
| 32023 | 0, // qsub3_then_ssub |
| 32024 | 0, // qsub2_then_bsub |
| 32025 | 0, // qsub2_then_dsub |
| 32026 | 0, // qsub2_then_hsub |
| 32027 | 0, // qsub2_then_ssub |
| 32028 | 0, // x8sub_7_then_sub_32 |
| 32029 | 0, // x8sub_6_then_sub_32 |
| 32030 | 0, // x8sub_5_then_sub_32 |
| 32031 | 0, // x8sub_4_then_sub_32 |
| 32032 | 0, // x8sub_3_then_sub_32 |
| 32033 | 0, // x8sub_2_then_sub_32 |
| 32034 | 0, // x8sub_1_then_sub_32 |
| 32035 | 0, // subo64_then_sub_32 |
| 32036 | 152, // zsub1_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32037 | 152, // zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32038 | 152, // zsub1_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32039 | 152, // zsub1_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32040 | 152, // zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32041 | 152, // zsub1_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32042 | 0, // zsub3_then_bsub |
| 32043 | 0, // zsub3_then_dsub |
| 32044 | 0, // zsub3_then_hsub |
| 32045 | 0, // zsub3_then_ssub |
| 32046 | 0, // zsub3_then_zsub |
| 32047 | 0, // zsub3_then_zsub_hi |
| 32048 | 152, // zsub2_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32049 | 152, // zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32050 | 152, // zsub2_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32051 | 152, // zsub2_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32052 | 152, // zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32053 | 152, // zsub2_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32054 | 0, // dsub0_dsub1 |
| 32055 | 0, // dsub0_dsub1_dsub2 |
| 32056 | 0, // dsub1_dsub2 |
| 32057 | 0, // dsub1_dsub2_dsub3 |
| 32058 | 0, // dsub2_dsub3 |
| 32059 | 0, // dsub_qsub1_then_dsub |
| 32060 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32061 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 32062 | 0, // qsub0_qsub1 |
| 32063 | 0, // qsub0_qsub1_qsub2 |
| 32064 | 0, // qsub1_qsub2 |
| 32065 | 0, // qsub1_qsub2_qsub3 |
| 32066 | 0, // qsub2_qsub3 |
| 32067 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 32068 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32069 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 32070 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32071 | 0, // x8sub_0_x8sub_1 |
| 32072 | 0, // x8sub_2_x8sub_3 |
| 32073 | 0, // x8sub_4_x8sub_5 |
| 32074 | 0, // x8sub_6_x8sub_7 |
| 32075 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32076 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32077 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32078 | 0, // sub_32_subo64_then_sub_32 |
| 32079 | 152, // dsub_zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32080 | 152, // zsub_zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32081 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32082 | 152, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32083 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32084 | 152, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32085 | 152, // zsub0_zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32086 | 0, // zsub0_zsub1_zsub2 |
| 32087 | 152, // zsub1_zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32088 | 0, // zsub1_zsub2_zsub3 |
| 32089 | 0, // zsub2_zsub3 |
| 32090 | 152, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32091 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32092 | 152, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 32093 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32094 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32095 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32096 | }, |
| 32097 | { // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32098 | 153, // bsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32099 | 153, // dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32100 | 0, // dsub0 |
| 32101 | 0, // dsub1 |
| 32102 | 0, // dsub2 |
| 32103 | 0, // dsub3 |
| 32104 | 153, // hsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32105 | 0, // qhisub |
| 32106 | 0, // qsub |
| 32107 | 0, // qsub0 |
| 32108 | 0, // qsub1 |
| 32109 | 0, // qsub2 |
| 32110 | 0, // qsub3 |
| 32111 | 153, // ssub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32112 | 0, // sub_32 |
| 32113 | 0, // sube32 |
| 32114 | 0, // sube64 |
| 32115 | 0, // subo32 |
| 32116 | 0, // subo64 |
| 32117 | 0, // x8sub_0 |
| 32118 | 0, // x8sub_1 |
| 32119 | 0, // x8sub_2 |
| 32120 | 0, // x8sub_3 |
| 32121 | 0, // x8sub_4 |
| 32122 | 0, // x8sub_5 |
| 32123 | 0, // x8sub_6 |
| 32124 | 0, // x8sub_7 |
| 32125 | 153, // zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32126 | 153, // zsub0 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32127 | 153, // zsub1 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32128 | 153, // zsub2 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32129 | 0, // zsub3 |
| 32130 | 153, // zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32131 | 0, // dsub1_then_bsub |
| 32132 | 0, // dsub1_then_hsub |
| 32133 | 0, // dsub1_then_ssub |
| 32134 | 0, // dsub3_then_bsub |
| 32135 | 0, // dsub3_then_hsub |
| 32136 | 0, // dsub3_then_ssub |
| 32137 | 0, // dsub2_then_bsub |
| 32138 | 0, // dsub2_then_hsub |
| 32139 | 0, // dsub2_then_ssub |
| 32140 | 0, // qsub1_then_bsub |
| 32141 | 0, // qsub1_then_dsub |
| 32142 | 0, // qsub1_then_hsub |
| 32143 | 0, // qsub1_then_ssub |
| 32144 | 0, // qsub3_then_bsub |
| 32145 | 0, // qsub3_then_dsub |
| 32146 | 0, // qsub3_then_hsub |
| 32147 | 0, // qsub3_then_ssub |
| 32148 | 0, // qsub2_then_bsub |
| 32149 | 0, // qsub2_then_dsub |
| 32150 | 0, // qsub2_then_hsub |
| 32151 | 0, // qsub2_then_ssub |
| 32152 | 0, // x8sub_7_then_sub_32 |
| 32153 | 0, // x8sub_6_then_sub_32 |
| 32154 | 0, // x8sub_5_then_sub_32 |
| 32155 | 0, // x8sub_4_then_sub_32 |
| 32156 | 0, // x8sub_3_then_sub_32 |
| 32157 | 0, // x8sub_2_then_sub_32 |
| 32158 | 0, // x8sub_1_then_sub_32 |
| 32159 | 0, // subo64_then_sub_32 |
| 32160 | 153, // zsub1_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32161 | 153, // zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32162 | 153, // zsub1_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32163 | 153, // zsub1_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32164 | 153, // zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32165 | 153, // zsub1_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32166 | 0, // zsub3_then_bsub |
| 32167 | 0, // zsub3_then_dsub |
| 32168 | 0, // zsub3_then_hsub |
| 32169 | 0, // zsub3_then_ssub |
| 32170 | 0, // zsub3_then_zsub |
| 32171 | 0, // zsub3_then_zsub_hi |
| 32172 | 153, // zsub2_then_bsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32173 | 153, // zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32174 | 153, // zsub2_then_hsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32175 | 153, // zsub2_then_ssub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32176 | 153, // zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32177 | 153, // zsub2_then_zsub_hi -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32178 | 0, // dsub0_dsub1 |
| 32179 | 0, // dsub0_dsub1_dsub2 |
| 32180 | 0, // dsub1_dsub2 |
| 32181 | 0, // dsub1_dsub2_dsub3 |
| 32182 | 0, // dsub2_dsub3 |
| 32183 | 0, // dsub_qsub1_then_dsub |
| 32184 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32185 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 32186 | 0, // qsub0_qsub1 |
| 32187 | 0, // qsub0_qsub1_qsub2 |
| 32188 | 0, // qsub1_qsub2 |
| 32189 | 0, // qsub1_qsub2_qsub3 |
| 32190 | 0, // qsub2_qsub3 |
| 32191 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 32192 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32193 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 32194 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32195 | 0, // x8sub_0_x8sub_1 |
| 32196 | 0, // x8sub_2_x8sub_3 |
| 32197 | 0, // x8sub_4_x8sub_5 |
| 32198 | 0, // x8sub_6_x8sub_7 |
| 32199 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32200 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32201 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32202 | 0, // sub_32_subo64_then_sub_32 |
| 32203 | 153, // dsub_zsub1_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32204 | 153, // zsub_zsub1_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32205 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32206 | 153, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32207 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32208 | 153, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32209 | 153, // zsub0_zsub1 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32210 | 0, // zsub0_zsub1_zsub2 |
| 32211 | 153, // zsub1_zsub2 -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32212 | 0, // zsub1_zsub2_zsub3 |
| 32213 | 0, // zsub2_zsub3 |
| 32214 | 153, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32215 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32216 | 153, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32217 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32218 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32219 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32220 | }, |
| 32221 | { // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32222 | 154, // bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32223 | 154, // dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32224 | 0, // dsub0 |
| 32225 | 0, // dsub1 |
| 32226 | 0, // dsub2 |
| 32227 | 0, // dsub3 |
| 32228 | 154, // hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32229 | 0, // qhisub |
| 32230 | 0, // qsub |
| 32231 | 0, // qsub0 |
| 32232 | 0, // qsub1 |
| 32233 | 0, // qsub2 |
| 32234 | 0, // qsub3 |
| 32235 | 154, // ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32236 | 0, // sub_32 |
| 32237 | 0, // sube32 |
| 32238 | 0, // sube64 |
| 32239 | 0, // subo32 |
| 32240 | 0, // subo64 |
| 32241 | 0, // x8sub_0 |
| 32242 | 0, // x8sub_1 |
| 32243 | 0, // x8sub_2 |
| 32244 | 0, // x8sub_3 |
| 32245 | 0, // x8sub_4 |
| 32246 | 0, // x8sub_5 |
| 32247 | 0, // x8sub_6 |
| 32248 | 0, // x8sub_7 |
| 32249 | 154, // zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32250 | 154, // zsub0 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32251 | 154, // zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32252 | 154, // zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32253 | 0, // zsub3 |
| 32254 | 154, // zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32255 | 0, // dsub1_then_bsub |
| 32256 | 0, // dsub1_then_hsub |
| 32257 | 0, // dsub1_then_ssub |
| 32258 | 0, // dsub3_then_bsub |
| 32259 | 0, // dsub3_then_hsub |
| 32260 | 0, // dsub3_then_ssub |
| 32261 | 0, // dsub2_then_bsub |
| 32262 | 0, // dsub2_then_hsub |
| 32263 | 0, // dsub2_then_ssub |
| 32264 | 0, // qsub1_then_bsub |
| 32265 | 0, // qsub1_then_dsub |
| 32266 | 0, // qsub1_then_hsub |
| 32267 | 0, // qsub1_then_ssub |
| 32268 | 0, // qsub3_then_bsub |
| 32269 | 0, // qsub3_then_dsub |
| 32270 | 0, // qsub3_then_hsub |
| 32271 | 0, // qsub3_then_ssub |
| 32272 | 0, // qsub2_then_bsub |
| 32273 | 0, // qsub2_then_dsub |
| 32274 | 0, // qsub2_then_hsub |
| 32275 | 0, // qsub2_then_ssub |
| 32276 | 0, // x8sub_7_then_sub_32 |
| 32277 | 0, // x8sub_6_then_sub_32 |
| 32278 | 0, // x8sub_5_then_sub_32 |
| 32279 | 0, // x8sub_4_then_sub_32 |
| 32280 | 0, // x8sub_3_then_sub_32 |
| 32281 | 0, // x8sub_2_then_sub_32 |
| 32282 | 0, // x8sub_1_then_sub_32 |
| 32283 | 0, // subo64_then_sub_32 |
| 32284 | 154, // zsub1_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32285 | 154, // zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32286 | 154, // zsub1_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32287 | 154, // zsub1_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32288 | 154, // zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32289 | 154, // zsub1_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32290 | 0, // zsub3_then_bsub |
| 32291 | 0, // zsub3_then_dsub |
| 32292 | 0, // zsub3_then_hsub |
| 32293 | 0, // zsub3_then_ssub |
| 32294 | 0, // zsub3_then_zsub |
| 32295 | 0, // zsub3_then_zsub_hi |
| 32296 | 154, // zsub2_then_bsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32297 | 154, // zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32298 | 154, // zsub2_then_hsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32299 | 154, // zsub2_then_ssub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32300 | 154, // zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32301 | 154, // zsub2_then_zsub_hi -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32302 | 0, // dsub0_dsub1 |
| 32303 | 0, // dsub0_dsub1_dsub2 |
| 32304 | 0, // dsub1_dsub2 |
| 32305 | 0, // dsub1_dsub2_dsub3 |
| 32306 | 0, // dsub2_dsub3 |
| 32307 | 0, // dsub_qsub1_then_dsub |
| 32308 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32309 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 32310 | 0, // qsub0_qsub1 |
| 32311 | 0, // qsub0_qsub1_qsub2 |
| 32312 | 0, // qsub1_qsub2 |
| 32313 | 0, // qsub1_qsub2_qsub3 |
| 32314 | 0, // qsub2_qsub3 |
| 32315 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 32316 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32317 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 32318 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32319 | 0, // x8sub_0_x8sub_1 |
| 32320 | 0, // x8sub_2_x8sub_3 |
| 32321 | 0, // x8sub_4_x8sub_5 |
| 32322 | 0, // x8sub_6_x8sub_7 |
| 32323 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32324 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32325 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32326 | 0, // sub_32_subo64_then_sub_32 |
| 32327 | 154, // dsub_zsub1_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32328 | 154, // zsub_zsub1_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32329 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32330 | 154, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32331 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32332 | 154, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32333 | 154, // zsub0_zsub1 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32334 | 0, // zsub0_zsub1_zsub2 |
| 32335 | 154, // zsub1_zsub2 -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32336 | 0, // zsub1_zsub2_zsub3 |
| 32337 | 0, // zsub2_zsub3 |
| 32338 | 154, // zsub1_then_dsub_zsub2_then_dsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32339 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32340 | 154, // zsub1_then_zsub_zsub2_then_zsub -> ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 32341 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32342 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32343 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32344 | }, |
| 32345 | { // QQQQ |
| 32346 | 155, // bsub -> QQQQ |
| 32347 | 155, // dsub -> QQQQ |
| 32348 | 0, // dsub0 |
| 32349 | 0, // dsub1 |
| 32350 | 0, // dsub2 |
| 32351 | 0, // dsub3 |
| 32352 | 155, // hsub -> QQQQ |
| 32353 | 0, // qhisub |
| 32354 | 0, // qsub |
| 32355 | 155, // qsub0 -> QQQQ |
| 32356 | 155, // qsub1 -> QQQQ |
| 32357 | 155, // qsub2 -> QQQQ |
| 32358 | 155, // qsub3 -> QQQQ |
| 32359 | 155, // ssub -> QQQQ |
| 32360 | 0, // sub_32 |
| 32361 | 0, // sube32 |
| 32362 | 0, // sube64 |
| 32363 | 0, // subo32 |
| 32364 | 0, // subo64 |
| 32365 | 0, // x8sub_0 |
| 32366 | 0, // x8sub_1 |
| 32367 | 0, // x8sub_2 |
| 32368 | 0, // x8sub_3 |
| 32369 | 0, // x8sub_4 |
| 32370 | 0, // x8sub_5 |
| 32371 | 0, // x8sub_6 |
| 32372 | 0, // x8sub_7 |
| 32373 | 0, // zsub |
| 32374 | 0, // zsub0 |
| 32375 | 0, // zsub1 |
| 32376 | 0, // zsub2 |
| 32377 | 0, // zsub3 |
| 32378 | 0, // zsub_hi |
| 32379 | 0, // dsub1_then_bsub |
| 32380 | 0, // dsub1_then_hsub |
| 32381 | 0, // dsub1_then_ssub |
| 32382 | 0, // dsub3_then_bsub |
| 32383 | 0, // dsub3_then_hsub |
| 32384 | 0, // dsub3_then_ssub |
| 32385 | 0, // dsub2_then_bsub |
| 32386 | 0, // dsub2_then_hsub |
| 32387 | 0, // dsub2_then_ssub |
| 32388 | 155, // qsub1_then_bsub -> QQQQ |
| 32389 | 155, // qsub1_then_dsub -> QQQQ |
| 32390 | 155, // qsub1_then_hsub -> QQQQ |
| 32391 | 155, // qsub1_then_ssub -> QQQQ |
| 32392 | 155, // qsub3_then_bsub -> QQQQ |
| 32393 | 155, // qsub3_then_dsub -> QQQQ |
| 32394 | 155, // qsub3_then_hsub -> QQQQ |
| 32395 | 155, // qsub3_then_ssub -> QQQQ |
| 32396 | 155, // qsub2_then_bsub -> QQQQ |
| 32397 | 155, // qsub2_then_dsub -> QQQQ |
| 32398 | 155, // qsub2_then_hsub -> QQQQ |
| 32399 | 155, // qsub2_then_ssub -> QQQQ |
| 32400 | 0, // x8sub_7_then_sub_32 |
| 32401 | 0, // x8sub_6_then_sub_32 |
| 32402 | 0, // x8sub_5_then_sub_32 |
| 32403 | 0, // x8sub_4_then_sub_32 |
| 32404 | 0, // x8sub_3_then_sub_32 |
| 32405 | 0, // x8sub_2_then_sub_32 |
| 32406 | 0, // x8sub_1_then_sub_32 |
| 32407 | 0, // subo64_then_sub_32 |
| 32408 | 0, // zsub1_then_bsub |
| 32409 | 0, // zsub1_then_dsub |
| 32410 | 0, // zsub1_then_hsub |
| 32411 | 0, // zsub1_then_ssub |
| 32412 | 0, // zsub1_then_zsub |
| 32413 | 0, // zsub1_then_zsub_hi |
| 32414 | 0, // zsub3_then_bsub |
| 32415 | 0, // zsub3_then_dsub |
| 32416 | 0, // zsub3_then_hsub |
| 32417 | 0, // zsub3_then_ssub |
| 32418 | 0, // zsub3_then_zsub |
| 32419 | 0, // zsub3_then_zsub_hi |
| 32420 | 0, // zsub2_then_bsub |
| 32421 | 0, // zsub2_then_dsub |
| 32422 | 0, // zsub2_then_hsub |
| 32423 | 0, // zsub2_then_ssub |
| 32424 | 0, // zsub2_then_zsub |
| 32425 | 0, // zsub2_then_zsub_hi |
| 32426 | 0, // dsub0_dsub1 |
| 32427 | 0, // dsub0_dsub1_dsub2 |
| 32428 | 0, // dsub1_dsub2 |
| 32429 | 0, // dsub1_dsub2_dsub3 |
| 32430 | 0, // dsub2_dsub3 |
| 32431 | 155, // dsub_qsub1_then_dsub -> QQQQ |
| 32432 | 155, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ |
| 32433 | 155, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ |
| 32434 | 155, // qsub0_qsub1 -> QQQQ |
| 32435 | 155, // qsub0_qsub1_qsub2 -> QQQQ |
| 32436 | 155, // qsub1_qsub2 -> QQQQ |
| 32437 | 155, // qsub1_qsub2_qsub3 -> QQQQ |
| 32438 | 155, // qsub2_qsub3 -> QQQQ |
| 32439 | 155, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ |
| 32440 | 155, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ |
| 32441 | 155, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ |
| 32442 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32443 | 0, // x8sub_0_x8sub_1 |
| 32444 | 0, // x8sub_2_x8sub_3 |
| 32445 | 0, // x8sub_4_x8sub_5 |
| 32446 | 0, // x8sub_6_x8sub_7 |
| 32447 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32448 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32449 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32450 | 0, // sub_32_subo64_then_sub_32 |
| 32451 | 0, // dsub_zsub1_then_dsub |
| 32452 | 0, // zsub_zsub1_then_zsub |
| 32453 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32454 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 32455 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32456 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 32457 | 0, // zsub0_zsub1 |
| 32458 | 0, // zsub0_zsub1_zsub2 |
| 32459 | 0, // zsub1_zsub2 |
| 32460 | 0, // zsub1_zsub2_zsub3 |
| 32461 | 0, // zsub2_zsub3 |
| 32462 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 32463 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32464 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 32465 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32466 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32467 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32468 | }, |
| 32469 | { // ZPR4 |
| 32470 | 156, // bsub -> ZPR4 |
| 32471 | 156, // dsub -> ZPR4 |
| 32472 | 0, // dsub0 |
| 32473 | 0, // dsub1 |
| 32474 | 0, // dsub2 |
| 32475 | 0, // dsub3 |
| 32476 | 156, // hsub -> ZPR4 |
| 32477 | 0, // qhisub |
| 32478 | 0, // qsub |
| 32479 | 0, // qsub0 |
| 32480 | 0, // qsub1 |
| 32481 | 0, // qsub2 |
| 32482 | 0, // qsub3 |
| 32483 | 156, // ssub -> ZPR4 |
| 32484 | 0, // sub_32 |
| 32485 | 0, // sube32 |
| 32486 | 0, // sube64 |
| 32487 | 0, // subo32 |
| 32488 | 0, // subo64 |
| 32489 | 0, // x8sub_0 |
| 32490 | 0, // x8sub_1 |
| 32491 | 0, // x8sub_2 |
| 32492 | 0, // x8sub_3 |
| 32493 | 0, // x8sub_4 |
| 32494 | 0, // x8sub_5 |
| 32495 | 0, // x8sub_6 |
| 32496 | 0, // x8sub_7 |
| 32497 | 156, // zsub -> ZPR4 |
| 32498 | 156, // zsub0 -> ZPR4 |
| 32499 | 156, // zsub1 -> ZPR4 |
| 32500 | 156, // zsub2 -> ZPR4 |
| 32501 | 156, // zsub3 -> ZPR4 |
| 32502 | 156, // zsub_hi -> ZPR4 |
| 32503 | 0, // dsub1_then_bsub |
| 32504 | 0, // dsub1_then_hsub |
| 32505 | 0, // dsub1_then_ssub |
| 32506 | 0, // dsub3_then_bsub |
| 32507 | 0, // dsub3_then_hsub |
| 32508 | 0, // dsub3_then_ssub |
| 32509 | 0, // dsub2_then_bsub |
| 32510 | 0, // dsub2_then_hsub |
| 32511 | 0, // dsub2_then_ssub |
| 32512 | 0, // qsub1_then_bsub |
| 32513 | 0, // qsub1_then_dsub |
| 32514 | 0, // qsub1_then_hsub |
| 32515 | 0, // qsub1_then_ssub |
| 32516 | 0, // qsub3_then_bsub |
| 32517 | 0, // qsub3_then_dsub |
| 32518 | 0, // qsub3_then_hsub |
| 32519 | 0, // qsub3_then_ssub |
| 32520 | 0, // qsub2_then_bsub |
| 32521 | 0, // qsub2_then_dsub |
| 32522 | 0, // qsub2_then_hsub |
| 32523 | 0, // qsub2_then_ssub |
| 32524 | 0, // x8sub_7_then_sub_32 |
| 32525 | 0, // x8sub_6_then_sub_32 |
| 32526 | 0, // x8sub_5_then_sub_32 |
| 32527 | 0, // x8sub_4_then_sub_32 |
| 32528 | 0, // x8sub_3_then_sub_32 |
| 32529 | 0, // x8sub_2_then_sub_32 |
| 32530 | 0, // x8sub_1_then_sub_32 |
| 32531 | 0, // subo64_then_sub_32 |
| 32532 | 156, // zsub1_then_bsub -> ZPR4 |
| 32533 | 156, // zsub1_then_dsub -> ZPR4 |
| 32534 | 156, // zsub1_then_hsub -> ZPR4 |
| 32535 | 156, // zsub1_then_ssub -> ZPR4 |
| 32536 | 156, // zsub1_then_zsub -> ZPR4 |
| 32537 | 156, // zsub1_then_zsub_hi -> ZPR4 |
| 32538 | 156, // zsub3_then_bsub -> ZPR4 |
| 32539 | 156, // zsub3_then_dsub -> ZPR4 |
| 32540 | 156, // zsub3_then_hsub -> ZPR4 |
| 32541 | 156, // zsub3_then_ssub -> ZPR4 |
| 32542 | 156, // zsub3_then_zsub -> ZPR4 |
| 32543 | 156, // zsub3_then_zsub_hi -> ZPR4 |
| 32544 | 156, // zsub2_then_bsub -> ZPR4 |
| 32545 | 156, // zsub2_then_dsub -> ZPR4 |
| 32546 | 156, // zsub2_then_hsub -> ZPR4 |
| 32547 | 156, // zsub2_then_ssub -> ZPR4 |
| 32548 | 156, // zsub2_then_zsub -> ZPR4 |
| 32549 | 156, // zsub2_then_zsub_hi -> ZPR4 |
| 32550 | 0, // dsub0_dsub1 |
| 32551 | 0, // dsub0_dsub1_dsub2 |
| 32552 | 0, // dsub1_dsub2 |
| 32553 | 0, // dsub1_dsub2_dsub3 |
| 32554 | 0, // dsub2_dsub3 |
| 32555 | 0, // dsub_qsub1_then_dsub |
| 32556 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32557 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 32558 | 0, // qsub0_qsub1 |
| 32559 | 0, // qsub0_qsub1_qsub2 |
| 32560 | 0, // qsub1_qsub2 |
| 32561 | 0, // qsub1_qsub2_qsub3 |
| 32562 | 0, // qsub2_qsub3 |
| 32563 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 32564 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 32565 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 32566 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32567 | 0, // x8sub_0_x8sub_1 |
| 32568 | 0, // x8sub_2_x8sub_3 |
| 32569 | 0, // x8sub_4_x8sub_5 |
| 32570 | 0, // x8sub_6_x8sub_7 |
| 32571 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32572 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32573 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32574 | 0, // sub_32_subo64_then_sub_32 |
| 32575 | 156, // dsub_zsub1_then_dsub -> ZPR4 |
| 32576 | 156, // zsub_zsub1_then_zsub -> ZPR4 |
| 32577 | 156, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4 |
| 32578 | 156, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4 |
| 32579 | 156, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4 |
| 32580 | 156, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4 |
| 32581 | 156, // zsub0_zsub1 -> ZPR4 |
| 32582 | 156, // zsub0_zsub1_zsub2 -> ZPR4 |
| 32583 | 156, // zsub1_zsub2 -> ZPR4 |
| 32584 | 156, // zsub1_zsub2_zsub3 -> ZPR4 |
| 32585 | 156, // zsub2_zsub3 -> ZPR4 |
| 32586 | 156, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4 |
| 32587 | 156, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4 |
| 32588 | 156, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4 |
| 32589 | 156, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4 |
| 32590 | 156, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4 |
| 32591 | 156, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4 |
| 32592 | }, |
| 32593 | { // QQQQ_with_dsub_in_FPR64_lo |
| 32594 | 157, // bsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32595 | 157, // dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32596 | 0, // dsub0 |
| 32597 | 0, // dsub1 |
| 32598 | 0, // dsub2 |
| 32599 | 0, // dsub3 |
| 32600 | 157, // hsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32601 | 0, // qhisub |
| 32602 | 0, // qsub |
| 32603 | 157, // qsub0 -> QQQQ_with_dsub_in_FPR64_lo |
| 32604 | 157, // qsub1 -> QQQQ_with_dsub_in_FPR64_lo |
| 32605 | 157, // qsub2 -> QQQQ_with_dsub_in_FPR64_lo |
| 32606 | 157, // qsub3 -> QQQQ_with_dsub_in_FPR64_lo |
| 32607 | 157, // ssub -> QQQQ_with_dsub_in_FPR64_lo |
| 32608 | 0, // sub_32 |
| 32609 | 0, // sube32 |
| 32610 | 0, // sube64 |
| 32611 | 0, // subo32 |
| 32612 | 0, // subo64 |
| 32613 | 0, // x8sub_0 |
| 32614 | 0, // x8sub_1 |
| 32615 | 0, // x8sub_2 |
| 32616 | 0, // x8sub_3 |
| 32617 | 0, // x8sub_4 |
| 32618 | 0, // x8sub_5 |
| 32619 | 0, // x8sub_6 |
| 32620 | 0, // x8sub_7 |
| 32621 | 0, // zsub |
| 32622 | 0, // zsub0 |
| 32623 | 0, // zsub1 |
| 32624 | 0, // zsub2 |
| 32625 | 0, // zsub3 |
| 32626 | 0, // zsub_hi |
| 32627 | 0, // dsub1_then_bsub |
| 32628 | 0, // dsub1_then_hsub |
| 32629 | 0, // dsub1_then_ssub |
| 32630 | 0, // dsub3_then_bsub |
| 32631 | 0, // dsub3_then_hsub |
| 32632 | 0, // dsub3_then_ssub |
| 32633 | 0, // dsub2_then_bsub |
| 32634 | 0, // dsub2_then_hsub |
| 32635 | 0, // dsub2_then_ssub |
| 32636 | 157, // qsub1_then_bsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32637 | 157, // qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32638 | 157, // qsub1_then_hsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32639 | 157, // qsub1_then_ssub -> QQQQ_with_dsub_in_FPR64_lo |
| 32640 | 157, // qsub3_then_bsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32641 | 157, // qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32642 | 157, // qsub3_then_hsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32643 | 157, // qsub3_then_ssub -> QQQQ_with_dsub_in_FPR64_lo |
| 32644 | 157, // qsub2_then_bsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32645 | 157, // qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32646 | 157, // qsub2_then_hsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32647 | 157, // qsub2_then_ssub -> QQQQ_with_dsub_in_FPR64_lo |
| 32648 | 0, // x8sub_7_then_sub_32 |
| 32649 | 0, // x8sub_6_then_sub_32 |
| 32650 | 0, // x8sub_5_then_sub_32 |
| 32651 | 0, // x8sub_4_then_sub_32 |
| 32652 | 0, // x8sub_3_then_sub_32 |
| 32653 | 0, // x8sub_2_then_sub_32 |
| 32654 | 0, // x8sub_1_then_sub_32 |
| 32655 | 0, // subo64_then_sub_32 |
| 32656 | 0, // zsub1_then_bsub |
| 32657 | 0, // zsub1_then_dsub |
| 32658 | 0, // zsub1_then_hsub |
| 32659 | 0, // zsub1_then_ssub |
| 32660 | 0, // zsub1_then_zsub |
| 32661 | 0, // zsub1_then_zsub_hi |
| 32662 | 0, // zsub3_then_bsub |
| 32663 | 0, // zsub3_then_dsub |
| 32664 | 0, // zsub3_then_hsub |
| 32665 | 0, // zsub3_then_ssub |
| 32666 | 0, // zsub3_then_zsub |
| 32667 | 0, // zsub3_then_zsub_hi |
| 32668 | 0, // zsub2_then_bsub |
| 32669 | 0, // zsub2_then_dsub |
| 32670 | 0, // zsub2_then_hsub |
| 32671 | 0, // zsub2_then_ssub |
| 32672 | 0, // zsub2_then_zsub |
| 32673 | 0, // zsub2_then_zsub_hi |
| 32674 | 0, // dsub0_dsub1 |
| 32675 | 0, // dsub0_dsub1_dsub2 |
| 32676 | 0, // dsub1_dsub2 |
| 32677 | 0, // dsub1_dsub2_dsub3 |
| 32678 | 0, // dsub2_dsub3 |
| 32679 | 157, // dsub_qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32680 | 157, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32681 | 157, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32682 | 157, // qsub0_qsub1 -> QQQQ_with_dsub_in_FPR64_lo |
| 32683 | 157, // qsub0_qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo |
| 32684 | 157, // qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo |
| 32685 | 157, // qsub1_qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo |
| 32686 | 157, // qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo |
| 32687 | 157, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32688 | 157, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32689 | 157, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo |
| 32690 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32691 | 0, // x8sub_0_x8sub_1 |
| 32692 | 0, // x8sub_2_x8sub_3 |
| 32693 | 0, // x8sub_4_x8sub_5 |
| 32694 | 0, // x8sub_6_x8sub_7 |
| 32695 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32696 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32697 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32698 | 0, // sub_32_subo64_then_sub_32 |
| 32699 | 0, // dsub_zsub1_then_dsub |
| 32700 | 0, // zsub_zsub1_then_zsub |
| 32701 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32702 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 32703 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32704 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 32705 | 0, // zsub0_zsub1 |
| 32706 | 0, // zsub0_zsub1_zsub2 |
| 32707 | 0, // zsub1_zsub2 |
| 32708 | 0, // zsub1_zsub2_zsub3 |
| 32709 | 0, // zsub2_zsub3 |
| 32710 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 32711 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32712 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 32713 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32714 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32715 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32716 | }, |
| 32717 | { // QQQQ_with_qsub1_in_FPR128_lo |
| 32718 | 158, // bsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32719 | 158, // dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32720 | 0, // dsub0 |
| 32721 | 0, // dsub1 |
| 32722 | 0, // dsub2 |
| 32723 | 0, // dsub3 |
| 32724 | 158, // hsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32725 | 0, // qhisub |
| 32726 | 0, // qsub |
| 32727 | 158, // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32728 | 158, // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32729 | 158, // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32730 | 158, // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32731 | 158, // ssub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32732 | 0, // sub_32 |
| 32733 | 0, // sube32 |
| 32734 | 0, // sube64 |
| 32735 | 0, // subo32 |
| 32736 | 0, // subo64 |
| 32737 | 0, // x8sub_0 |
| 32738 | 0, // x8sub_1 |
| 32739 | 0, // x8sub_2 |
| 32740 | 0, // x8sub_3 |
| 32741 | 0, // x8sub_4 |
| 32742 | 0, // x8sub_5 |
| 32743 | 0, // x8sub_6 |
| 32744 | 0, // x8sub_7 |
| 32745 | 0, // zsub |
| 32746 | 0, // zsub0 |
| 32747 | 0, // zsub1 |
| 32748 | 0, // zsub2 |
| 32749 | 0, // zsub3 |
| 32750 | 0, // zsub_hi |
| 32751 | 0, // dsub1_then_bsub |
| 32752 | 0, // dsub1_then_hsub |
| 32753 | 0, // dsub1_then_ssub |
| 32754 | 0, // dsub3_then_bsub |
| 32755 | 0, // dsub3_then_hsub |
| 32756 | 0, // dsub3_then_ssub |
| 32757 | 0, // dsub2_then_bsub |
| 32758 | 0, // dsub2_then_hsub |
| 32759 | 0, // dsub2_then_ssub |
| 32760 | 158, // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32761 | 158, // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32762 | 158, // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32763 | 158, // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32764 | 158, // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32765 | 158, // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32766 | 158, // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32767 | 158, // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32768 | 158, // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32769 | 158, // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32770 | 158, // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32771 | 158, // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32772 | 0, // x8sub_7_then_sub_32 |
| 32773 | 0, // x8sub_6_then_sub_32 |
| 32774 | 0, // x8sub_5_then_sub_32 |
| 32775 | 0, // x8sub_4_then_sub_32 |
| 32776 | 0, // x8sub_3_then_sub_32 |
| 32777 | 0, // x8sub_2_then_sub_32 |
| 32778 | 0, // x8sub_1_then_sub_32 |
| 32779 | 0, // subo64_then_sub_32 |
| 32780 | 0, // zsub1_then_bsub |
| 32781 | 0, // zsub1_then_dsub |
| 32782 | 0, // zsub1_then_hsub |
| 32783 | 0, // zsub1_then_ssub |
| 32784 | 0, // zsub1_then_zsub |
| 32785 | 0, // zsub1_then_zsub_hi |
| 32786 | 0, // zsub3_then_bsub |
| 32787 | 0, // zsub3_then_dsub |
| 32788 | 0, // zsub3_then_hsub |
| 32789 | 0, // zsub3_then_ssub |
| 32790 | 0, // zsub3_then_zsub |
| 32791 | 0, // zsub3_then_zsub_hi |
| 32792 | 0, // zsub2_then_bsub |
| 32793 | 0, // zsub2_then_dsub |
| 32794 | 0, // zsub2_then_hsub |
| 32795 | 0, // zsub2_then_ssub |
| 32796 | 0, // zsub2_then_zsub |
| 32797 | 0, // zsub2_then_zsub_hi |
| 32798 | 0, // dsub0_dsub1 |
| 32799 | 0, // dsub0_dsub1_dsub2 |
| 32800 | 0, // dsub1_dsub2 |
| 32801 | 0, // dsub1_dsub2_dsub3 |
| 32802 | 0, // dsub2_dsub3 |
| 32803 | 158, // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32804 | 158, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32805 | 158, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32806 | 158, // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32807 | 158, // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32808 | 158, // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32809 | 158, // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32810 | 158, // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo |
| 32811 | 158, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32812 | 158, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32813 | 158, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo |
| 32814 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32815 | 0, // x8sub_0_x8sub_1 |
| 32816 | 0, // x8sub_2_x8sub_3 |
| 32817 | 0, // x8sub_4_x8sub_5 |
| 32818 | 0, // x8sub_6_x8sub_7 |
| 32819 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32820 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32821 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32822 | 0, // sub_32_subo64_then_sub_32 |
| 32823 | 0, // dsub_zsub1_then_dsub |
| 32824 | 0, // zsub_zsub1_then_zsub |
| 32825 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32826 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 32827 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32828 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 32829 | 0, // zsub0_zsub1 |
| 32830 | 0, // zsub0_zsub1_zsub2 |
| 32831 | 0, // zsub1_zsub2 |
| 32832 | 0, // zsub1_zsub2_zsub3 |
| 32833 | 0, // zsub2_zsub3 |
| 32834 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 32835 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32836 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 32837 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32838 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32839 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32840 | }, |
| 32841 | { // QQQQ_with_qsub2_in_FPR128_lo |
| 32842 | 159, // bsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32843 | 159, // dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32844 | 0, // dsub0 |
| 32845 | 0, // dsub1 |
| 32846 | 0, // dsub2 |
| 32847 | 0, // dsub3 |
| 32848 | 159, // hsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32849 | 0, // qhisub |
| 32850 | 0, // qsub |
| 32851 | 159, // qsub0 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32852 | 159, // qsub1 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32853 | 159, // qsub2 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32854 | 159, // qsub3 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32855 | 159, // ssub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32856 | 0, // sub_32 |
| 32857 | 0, // sube32 |
| 32858 | 0, // sube64 |
| 32859 | 0, // subo32 |
| 32860 | 0, // subo64 |
| 32861 | 0, // x8sub_0 |
| 32862 | 0, // x8sub_1 |
| 32863 | 0, // x8sub_2 |
| 32864 | 0, // x8sub_3 |
| 32865 | 0, // x8sub_4 |
| 32866 | 0, // x8sub_5 |
| 32867 | 0, // x8sub_6 |
| 32868 | 0, // x8sub_7 |
| 32869 | 0, // zsub |
| 32870 | 0, // zsub0 |
| 32871 | 0, // zsub1 |
| 32872 | 0, // zsub2 |
| 32873 | 0, // zsub3 |
| 32874 | 0, // zsub_hi |
| 32875 | 0, // dsub1_then_bsub |
| 32876 | 0, // dsub1_then_hsub |
| 32877 | 0, // dsub1_then_ssub |
| 32878 | 0, // dsub3_then_bsub |
| 32879 | 0, // dsub3_then_hsub |
| 32880 | 0, // dsub3_then_ssub |
| 32881 | 0, // dsub2_then_bsub |
| 32882 | 0, // dsub2_then_hsub |
| 32883 | 0, // dsub2_then_ssub |
| 32884 | 159, // qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32885 | 159, // qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32886 | 159, // qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32887 | 159, // qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32888 | 159, // qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32889 | 159, // qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32890 | 159, // qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32891 | 159, // qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32892 | 159, // qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32893 | 159, // qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32894 | 159, // qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32895 | 159, // qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32896 | 0, // x8sub_7_then_sub_32 |
| 32897 | 0, // x8sub_6_then_sub_32 |
| 32898 | 0, // x8sub_5_then_sub_32 |
| 32899 | 0, // x8sub_4_then_sub_32 |
| 32900 | 0, // x8sub_3_then_sub_32 |
| 32901 | 0, // x8sub_2_then_sub_32 |
| 32902 | 0, // x8sub_1_then_sub_32 |
| 32903 | 0, // subo64_then_sub_32 |
| 32904 | 0, // zsub1_then_bsub |
| 32905 | 0, // zsub1_then_dsub |
| 32906 | 0, // zsub1_then_hsub |
| 32907 | 0, // zsub1_then_ssub |
| 32908 | 0, // zsub1_then_zsub |
| 32909 | 0, // zsub1_then_zsub_hi |
| 32910 | 0, // zsub3_then_bsub |
| 32911 | 0, // zsub3_then_dsub |
| 32912 | 0, // zsub3_then_hsub |
| 32913 | 0, // zsub3_then_ssub |
| 32914 | 0, // zsub3_then_zsub |
| 32915 | 0, // zsub3_then_zsub_hi |
| 32916 | 0, // zsub2_then_bsub |
| 32917 | 0, // zsub2_then_dsub |
| 32918 | 0, // zsub2_then_hsub |
| 32919 | 0, // zsub2_then_ssub |
| 32920 | 0, // zsub2_then_zsub |
| 32921 | 0, // zsub2_then_zsub_hi |
| 32922 | 0, // dsub0_dsub1 |
| 32923 | 0, // dsub0_dsub1_dsub2 |
| 32924 | 0, // dsub1_dsub2 |
| 32925 | 0, // dsub1_dsub2_dsub3 |
| 32926 | 0, // dsub2_dsub3 |
| 32927 | 159, // dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32928 | 159, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32929 | 159, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32930 | 159, // qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32931 | 159, // qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32932 | 159, // qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32933 | 159, // qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32934 | 159, // qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo |
| 32935 | 159, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32936 | 159, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32937 | 159, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo |
| 32938 | 0, // sub_32_x8sub_1_then_sub_32 |
| 32939 | 0, // x8sub_0_x8sub_1 |
| 32940 | 0, // x8sub_2_x8sub_3 |
| 32941 | 0, // x8sub_4_x8sub_5 |
| 32942 | 0, // x8sub_6_x8sub_7 |
| 32943 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 32944 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 32945 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 32946 | 0, // sub_32_subo64_then_sub_32 |
| 32947 | 0, // dsub_zsub1_then_dsub |
| 32948 | 0, // zsub_zsub1_then_zsub |
| 32949 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32950 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 32951 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32952 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 32953 | 0, // zsub0_zsub1 |
| 32954 | 0, // zsub0_zsub1_zsub2 |
| 32955 | 0, // zsub1_zsub2 |
| 32956 | 0, // zsub1_zsub2_zsub3 |
| 32957 | 0, // zsub2_zsub3 |
| 32958 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 32959 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 32960 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 32961 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 32962 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 32963 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 32964 | }, |
| 32965 | { // QQQQ_with_qsub3_in_FPR128_lo |
| 32966 | 160, // bsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 32967 | 160, // dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 32968 | 0, // dsub0 |
| 32969 | 0, // dsub1 |
| 32970 | 0, // dsub2 |
| 32971 | 0, // dsub3 |
| 32972 | 160, // hsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 32973 | 0, // qhisub |
| 32974 | 0, // qsub |
| 32975 | 160, // qsub0 -> QQQQ_with_qsub3_in_FPR128_lo |
| 32976 | 160, // qsub1 -> QQQQ_with_qsub3_in_FPR128_lo |
| 32977 | 160, // qsub2 -> QQQQ_with_qsub3_in_FPR128_lo |
| 32978 | 160, // qsub3 -> QQQQ_with_qsub3_in_FPR128_lo |
| 32979 | 160, // ssub -> QQQQ_with_qsub3_in_FPR128_lo |
| 32980 | 0, // sub_32 |
| 32981 | 0, // sube32 |
| 32982 | 0, // sube64 |
| 32983 | 0, // subo32 |
| 32984 | 0, // subo64 |
| 32985 | 0, // x8sub_0 |
| 32986 | 0, // x8sub_1 |
| 32987 | 0, // x8sub_2 |
| 32988 | 0, // x8sub_3 |
| 32989 | 0, // x8sub_4 |
| 32990 | 0, // x8sub_5 |
| 32991 | 0, // x8sub_6 |
| 32992 | 0, // x8sub_7 |
| 32993 | 0, // zsub |
| 32994 | 0, // zsub0 |
| 32995 | 0, // zsub1 |
| 32996 | 0, // zsub2 |
| 32997 | 0, // zsub3 |
| 32998 | 0, // zsub_hi |
| 32999 | 0, // dsub1_then_bsub |
| 33000 | 0, // dsub1_then_hsub |
| 33001 | 0, // dsub1_then_ssub |
| 33002 | 0, // dsub3_then_bsub |
| 33003 | 0, // dsub3_then_hsub |
| 33004 | 0, // dsub3_then_ssub |
| 33005 | 0, // dsub2_then_bsub |
| 33006 | 0, // dsub2_then_hsub |
| 33007 | 0, // dsub2_then_ssub |
| 33008 | 160, // qsub1_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33009 | 160, // qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33010 | 160, // qsub1_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33011 | 160, // qsub1_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33012 | 160, // qsub3_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33013 | 160, // qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33014 | 160, // qsub3_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33015 | 160, // qsub3_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33016 | 160, // qsub2_then_bsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33017 | 160, // qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33018 | 160, // qsub2_then_hsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33019 | 160, // qsub2_then_ssub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33020 | 0, // x8sub_7_then_sub_32 |
| 33021 | 0, // x8sub_6_then_sub_32 |
| 33022 | 0, // x8sub_5_then_sub_32 |
| 33023 | 0, // x8sub_4_then_sub_32 |
| 33024 | 0, // x8sub_3_then_sub_32 |
| 33025 | 0, // x8sub_2_then_sub_32 |
| 33026 | 0, // x8sub_1_then_sub_32 |
| 33027 | 0, // subo64_then_sub_32 |
| 33028 | 0, // zsub1_then_bsub |
| 33029 | 0, // zsub1_then_dsub |
| 33030 | 0, // zsub1_then_hsub |
| 33031 | 0, // zsub1_then_ssub |
| 33032 | 0, // zsub1_then_zsub |
| 33033 | 0, // zsub1_then_zsub_hi |
| 33034 | 0, // zsub3_then_bsub |
| 33035 | 0, // zsub3_then_dsub |
| 33036 | 0, // zsub3_then_hsub |
| 33037 | 0, // zsub3_then_ssub |
| 33038 | 0, // zsub3_then_zsub |
| 33039 | 0, // zsub3_then_zsub_hi |
| 33040 | 0, // zsub2_then_bsub |
| 33041 | 0, // zsub2_then_dsub |
| 33042 | 0, // zsub2_then_hsub |
| 33043 | 0, // zsub2_then_ssub |
| 33044 | 0, // zsub2_then_zsub |
| 33045 | 0, // zsub2_then_zsub_hi |
| 33046 | 0, // dsub0_dsub1 |
| 33047 | 0, // dsub0_dsub1_dsub2 |
| 33048 | 0, // dsub1_dsub2 |
| 33049 | 0, // dsub1_dsub2_dsub3 |
| 33050 | 0, // dsub2_dsub3 |
| 33051 | 160, // dsub_qsub1_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33052 | 160, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33053 | 160, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33054 | 160, // qsub0_qsub1 -> QQQQ_with_qsub3_in_FPR128_lo |
| 33055 | 160, // qsub0_qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo |
| 33056 | 160, // qsub1_qsub2 -> QQQQ_with_qsub3_in_FPR128_lo |
| 33057 | 160, // qsub1_qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo |
| 33058 | 160, // qsub2_qsub3 -> QQQQ_with_qsub3_in_FPR128_lo |
| 33059 | 160, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33060 | 160, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33061 | 160, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub3_in_FPR128_lo |
| 33062 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33063 | 0, // x8sub_0_x8sub_1 |
| 33064 | 0, // x8sub_2_x8sub_3 |
| 33065 | 0, // x8sub_4_x8sub_5 |
| 33066 | 0, // x8sub_6_x8sub_7 |
| 33067 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33068 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33069 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33070 | 0, // sub_32_subo64_then_sub_32 |
| 33071 | 0, // dsub_zsub1_then_dsub |
| 33072 | 0, // zsub_zsub1_then_zsub |
| 33073 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33074 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 33075 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33076 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 33077 | 0, // zsub0_zsub1 |
| 33078 | 0, // zsub0_zsub1_zsub2 |
| 33079 | 0, // zsub1_zsub2 |
| 33080 | 0, // zsub1_zsub2_zsub3 |
| 33081 | 0, // zsub2_zsub3 |
| 33082 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 33083 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33084 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 33085 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33086 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 33087 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 33088 | }, |
| 33089 | { // ZPR4_with_dsub_in_FPR64_lo |
| 33090 | 161, // bsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33091 | 161, // dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33092 | 0, // dsub0 |
| 33093 | 0, // dsub1 |
| 33094 | 0, // dsub2 |
| 33095 | 0, // dsub3 |
| 33096 | 161, // hsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33097 | 0, // qhisub |
| 33098 | 0, // qsub |
| 33099 | 0, // qsub0 |
| 33100 | 0, // qsub1 |
| 33101 | 0, // qsub2 |
| 33102 | 0, // qsub3 |
| 33103 | 161, // ssub -> ZPR4_with_dsub_in_FPR64_lo |
| 33104 | 0, // sub_32 |
| 33105 | 0, // sube32 |
| 33106 | 0, // sube64 |
| 33107 | 0, // subo32 |
| 33108 | 0, // subo64 |
| 33109 | 0, // x8sub_0 |
| 33110 | 0, // x8sub_1 |
| 33111 | 0, // x8sub_2 |
| 33112 | 0, // x8sub_3 |
| 33113 | 0, // x8sub_4 |
| 33114 | 0, // x8sub_5 |
| 33115 | 0, // x8sub_6 |
| 33116 | 0, // x8sub_7 |
| 33117 | 161, // zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33118 | 161, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo |
| 33119 | 161, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo |
| 33120 | 161, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo |
| 33121 | 161, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo |
| 33122 | 161, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo |
| 33123 | 0, // dsub1_then_bsub |
| 33124 | 0, // dsub1_then_hsub |
| 33125 | 0, // dsub1_then_ssub |
| 33126 | 0, // dsub3_then_bsub |
| 33127 | 0, // dsub3_then_hsub |
| 33128 | 0, // dsub3_then_ssub |
| 33129 | 0, // dsub2_then_bsub |
| 33130 | 0, // dsub2_then_hsub |
| 33131 | 0, // dsub2_then_ssub |
| 33132 | 0, // qsub1_then_bsub |
| 33133 | 0, // qsub1_then_dsub |
| 33134 | 0, // qsub1_then_hsub |
| 33135 | 0, // qsub1_then_ssub |
| 33136 | 0, // qsub3_then_bsub |
| 33137 | 0, // qsub3_then_dsub |
| 33138 | 0, // qsub3_then_hsub |
| 33139 | 0, // qsub3_then_ssub |
| 33140 | 0, // qsub2_then_bsub |
| 33141 | 0, // qsub2_then_dsub |
| 33142 | 0, // qsub2_then_hsub |
| 33143 | 0, // qsub2_then_ssub |
| 33144 | 0, // x8sub_7_then_sub_32 |
| 33145 | 0, // x8sub_6_then_sub_32 |
| 33146 | 0, // x8sub_5_then_sub_32 |
| 33147 | 0, // x8sub_4_then_sub_32 |
| 33148 | 0, // x8sub_3_then_sub_32 |
| 33149 | 0, // x8sub_2_then_sub_32 |
| 33150 | 0, // x8sub_1_then_sub_32 |
| 33151 | 0, // subo64_then_sub_32 |
| 33152 | 161, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33153 | 161, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33154 | 161, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33155 | 161, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo |
| 33156 | 161, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33157 | 161, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo |
| 33158 | 161, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33159 | 161, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33160 | 161, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33161 | 161, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo |
| 33162 | 161, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33163 | 161, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo |
| 33164 | 161, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33165 | 161, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33166 | 161, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33167 | 161, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo |
| 33168 | 161, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33169 | 161, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo |
| 33170 | 0, // dsub0_dsub1 |
| 33171 | 0, // dsub0_dsub1_dsub2 |
| 33172 | 0, // dsub1_dsub2 |
| 33173 | 0, // dsub1_dsub2_dsub3 |
| 33174 | 0, // dsub2_dsub3 |
| 33175 | 0, // dsub_qsub1_then_dsub |
| 33176 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33177 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 33178 | 0, // qsub0_qsub1 |
| 33179 | 0, // qsub0_qsub1_qsub2 |
| 33180 | 0, // qsub1_qsub2 |
| 33181 | 0, // qsub1_qsub2_qsub3 |
| 33182 | 0, // qsub2_qsub3 |
| 33183 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 33184 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33185 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 33186 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33187 | 0, // x8sub_0_x8sub_1 |
| 33188 | 0, // x8sub_2_x8sub_3 |
| 33189 | 0, // x8sub_4_x8sub_5 |
| 33190 | 0, // x8sub_6_x8sub_7 |
| 33191 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33192 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33193 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33194 | 0, // sub_32_subo64_then_sub_32 |
| 33195 | 161, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33196 | 161, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33197 | 161, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33198 | 161, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33199 | 161, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33200 | 161, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33201 | 161, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo |
| 33202 | 161, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo |
| 33203 | 161, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo |
| 33204 | 161, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo |
| 33205 | 161, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo |
| 33206 | 161, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33207 | 161, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33208 | 161, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33209 | 161, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33210 | 161, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33211 | 161, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo |
| 33212 | }, |
| 33213 | { // ZPR4_with_zsub1_in_ZPR_4b |
| 33214 | 162, // bsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33215 | 162, // dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33216 | 0, // dsub0 |
| 33217 | 0, // dsub1 |
| 33218 | 0, // dsub2 |
| 33219 | 0, // dsub3 |
| 33220 | 162, // hsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33221 | 0, // qhisub |
| 33222 | 0, // qsub |
| 33223 | 0, // qsub0 |
| 33224 | 0, // qsub1 |
| 33225 | 0, // qsub2 |
| 33226 | 0, // qsub3 |
| 33227 | 162, // ssub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33228 | 0, // sub_32 |
| 33229 | 0, // sube32 |
| 33230 | 0, // sube64 |
| 33231 | 0, // subo32 |
| 33232 | 0, // subo64 |
| 33233 | 0, // x8sub_0 |
| 33234 | 0, // x8sub_1 |
| 33235 | 0, // x8sub_2 |
| 33236 | 0, // x8sub_3 |
| 33237 | 0, // x8sub_4 |
| 33238 | 0, // x8sub_5 |
| 33239 | 0, // x8sub_6 |
| 33240 | 0, // x8sub_7 |
| 33241 | 162, // zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33242 | 162, // zsub0 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33243 | 162, // zsub1 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33244 | 162, // zsub2 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33245 | 162, // zsub3 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33246 | 162, // zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b |
| 33247 | 0, // dsub1_then_bsub |
| 33248 | 0, // dsub1_then_hsub |
| 33249 | 0, // dsub1_then_ssub |
| 33250 | 0, // dsub3_then_bsub |
| 33251 | 0, // dsub3_then_hsub |
| 33252 | 0, // dsub3_then_ssub |
| 33253 | 0, // dsub2_then_bsub |
| 33254 | 0, // dsub2_then_hsub |
| 33255 | 0, // dsub2_then_ssub |
| 33256 | 0, // qsub1_then_bsub |
| 33257 | 0, // qsub1_then_dsub |
| 33258 | 0, // qsub1_then_hsub |
| 33259 | 0, // qsub1_then_ssub |
| 33260 | 0, // qsub3_then_bsub |
| 33261 | 0, // qsub3_then_dsub |
| 33262 | 0, // qsub3_then_hsub |
| 33263 | 0, // qsub3_then_ssub |
| 33264 | 0, // qsub2_then_bsub |
| 33265 | 0, // qsub2_then_dsub |
| 33266 | 0, // qsub2_then_hsub |
| 33267 | 0, // qsub2_then_ssub |
| 33268 | 0, // x8sub_7_then_sub_32 |
| 33269 | 0, // x8sub_6_then_sub_32 |
| 33270 | 0, // x8sub_5_then_sub_32 |
| 33271 | 0, // x8sub_4_then_sub_32 |
| 33272 | 0, // x8sub_3_then_sub_32 |
| 33273 | 0, // x8sub_2_then_sub_32 |
| 33274 | 0, // x8sub_1_then_sub_32 |
| 33275 | 0, // subo64_then_sub_32 |
| 33276 | 162, // zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33277 | 162, // zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33278 | 162, // zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33279 | 162, // zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33280 | 162, // zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33281 | 162, // zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b |
| 33282 | 162, // zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33283 | 162, // zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33284 | 162, // zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33285 | 162, // zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33286 | 162, // zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33287 | 162, // zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b |
| 33288 | 162, // zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33289 | 162, // zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33290 | 162, // zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33291 | 162, // zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33292 | 162, // zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33293 | 162, // zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b |
| 33294 | 0, // dsub0_dsub1 |
| 33295 | 0, // dsub0_dsub1_dsub2 |
| 33296 | 0, // dsub1_dsub2 |
| 33297 | 0, // dsub1_dsub2_dsub3 |
| 33298 | 0, // dsub2_dsub3 |
| 33299 | 0, // dsub_qsub1_then_dsub |
| 33300 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33301 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 33302 | 0, // qsub0_qsub1 |
| 33303 | 0, // qsub0_qsub1_qsub2 |
| 33304 | 0, // qsub1_qsub2 |
| 33305 | 0, // qsub1_qsub2_qsub3 |
| 33306 | 0, // qsub2_qsub3 |
| 33307 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 33308 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33309 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 33310 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33311 | 0, // x8sub_0_x8sub_1 |
| 33312 | 0, // x8sub_2_x8sub_3 |
| 33313 | 0, // x8sub_4_x8sub_5 |
| 33314 | 0, // x8sub_6_x8sub_7 |
| 33315 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33316 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33317 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33318 | 0, // sub_32_subo64_then_sub_32 |
| 33319 | 162, // dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33320 | 162, // zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33321 | 162, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33322 | 162, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33323 | 162, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33324 | 162, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33325 | 162, // zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33326 | 162, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33327 | 162, // zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33328 | 162, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33329 | 162, // zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b |
| 33330 | 162, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33331 | 162, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33332 | 162, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33333 | 162, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33334 | 162, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33335 | 162, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b |
| 33336 | }, |
| 33337 | { // ZPR4_with_zsub2_in_ZPR_4b |
| 33338 | 163, // bsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33339 | 163, // dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33340 | 0, // dsub0 |
| 33341 | 0, // dsub1 |
| 33342 | 0, // dsub2 |
| 33343 | 0, // dsub3 |
| 33344 | 163, // hsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33345 | 0, // qhisub |
| 33346 | 0, // qsub |
| 33347 | 0, // qsub0 |
| 33348 | 0, // qsub1 |
| 33349 | 0, // qsub2 |
| 33350 | 0, // qsub3 |
| 33351 | 163, // ssub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33352 | 0, // sub_32 |
| 33353 | 0, // sube32 |
| 33354 | 0, // sube64 |
| 33355 | 0, // subo32 |
| 33356 | 0, // subo64 |
| 33357 | 0, // x8sub_0 |
| 33358 | 0, // x8sub_1 |
| 33359 | 0, // x8sub_2 |
| 33360 | 0, // x8sub_3 |
| 33361 | 0, // x8sub_4 |
| 33362 | 0, // x8sub_5 |
| 33363 | 0, // x8sub_6 |
| 33364 | 0, // x8sub_7 |
| 33365 | 163, // zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33366 | 163, // zsub0 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33367 | 163, // zsub1 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33368 | 163, // zsub2 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33369 | 163, // zsub3 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33370 | 163, // zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b |
| 33371 | 0, // dsub1_then_bsub |
| 33372 | 0, // dsub1_then_hsub |
| 33373 | 0, // dsub1_then_ssub |
| 33374 | 0, // dsub3_then_bsub |
| 33375 | 0, // dsub3_then_hsub |
| 33376 | 0, // dsub3_then_ssub |
| 33377 | 0, // dsub2_then_bsub |
| 33378 | 0, // dsub2_then_hsub |
| 33379 | 0, // dsub2_then_ssub |
| 33380 | 0, // qsub1_then_bsub |
| 33381 | 0, // qsub1_then_dsub |
| 33382 | 0, // qsub1_then_hsub |
| 33383 | 0, // qsub1_then_ssub |
| 33384 | 0, // qsub3_then_bsub |
| 33385 | 0, // qsub3_then_dsub |
| 33386 | 0, // qsub3_then_hsub |
| 33387 | 0, // qsub3_then_ssub |
| 33388 | 0, // qsub2_then_bsub |
| 33389 | 0, // qsub2_then_dsub |
| 33390 | 0, // qsub2_then_hsub |
| 33391 | 0, // qsub2_then_ssub |
| 33392 | 0, // x8sub_7_then_sub_32 |
| 33393 | 0, // x8sub_6_then_sub_32 |
| 33394 | 0, // x8sub_5_then_sub_32 |
| 33395 | 0, // x8sub_4_then_sub_32 |
| 33396 | 0, // x8sub_3_then_sub_32 |
| 33397 | 0, // x8sub_2_then_sub_32 |
| 33398 | 0, // x8sub_1_then_sub_32 |
| 33399 | 0, // subo64_then_sub_32 |
| 33400 | 163, // zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33401 | 163, // zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33402 | 163, // zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33403 | 163, // zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33404 | 163, // zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33405 | 163, // zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b |
| 33406 | 163, // zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33407 | 163, // zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33408 | 163, // zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33409 | 163, // zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33410 | 163, // zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33411 | 163, // zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b |
| 33412 | 163, // zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33413 | 163, // zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33414 | 163, // zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33415 | 163, // zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33416 | 163, // zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33417 | 163, // zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b |
| 33418 | 0, // dsub0_dsub1 |
| 33419 | 0, // dsub0_dsub1_dsub2 |
| 33420 | 0, // dsub1_dsub2 |
| 33421 | 0, // dsub1_dsub2_dsub3 |
| 33422 | 0, // dsub2_dsub3 |
| 33423 | 0, // dsub_qsub1_then_dsub |
| 33424 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33425 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 33426 | 0, // qsub0_qsub1 |
| 33427 | 0, // qsub0_qsub1_qsub2 |
| 33428 | 0, // qsub1_qsub2 |
| 33429 | 0, // qsub1_qsub2_qsub3 |
| 33430 | 0, // qsub2_qsub3 |
| 33431 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 33432 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33433 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 33434 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33435 | 0, // x8sub_0_x8sub_1 |
| 33436 | 0, // x8sub_2_x8sub_3 |
| 33437 | 0, // x8sub_4_x8sub_5 |
| 33438 | 0, // x8sub_6_x8sub_7 |
| 33439 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33440 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33441 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33442 | 0, // sub_32_subo64_then_sub_32 |
| 33443 | 163, // dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33444 | 163, // zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33445 | 163, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33446 | 163, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33447 | 163, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33448 | 163, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33449 | 163, // zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33450 | 163, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33451 | 163, // zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33452 | 163, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33453 | 163, // zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b |
| 33454 | 163, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33455 | 163, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33456 | 163, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33457 | 163, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33458 | 163, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33459 | 163, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b |
| 33460 | }, |
| 33461 | { // ZPR4_with_zsub3_in_ZPR_4b |
| 33462 | 164, // bsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33463 | 164, // dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33464 | 0, // dsub0 |
| 33465 | 0, // dsub1 |
| 33466 | 0, // dsub2 |
| 33467 | 0, // dsub3 |
| 33468 | 164, // hsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33469 | 0, // qhisub |
| 33470 | 0, // qsub |
| 33471 | 0, // qsub0 |
| 33472 | 0, // qsub1 |
| 33473 | 0, // qsub2 |
| 33474 | 0, // qsub3 |
| 33475 | 164, // ssub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33476 | 0, // sub_32 |
| 33477 | 0, // sube32 |
| 33478 | 0, // sube64 |
| 33479 | 0, // subo32 |
| 33480 | 0, // subo64 |
| 33481 | 0, // x8sub_0 |
| 33482 | 0, // x8sub_1 |
| 33483 | 0, // x8sub_2 |
| 33484 | 0, // x8sub_3 |
| 33485 | 0, // x8sub_4 |
| 33486 | 0, // x8sub_5 |
| 33487 | 0, // x8sub_6 |
| 33488 | 0, // x8sub_7 |
| 33489 | 164, // zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33490 | 164, // zsub0 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33491 | 164, // zsub1 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33492 | 164, // zsub2 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33493 | 164, // zsub3 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33494 | 164, // zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b |
| 33495 | 0, // dsub1_then_bsub |
| 33496 | 0, // dsub1_then_hsub |
| 33497 | 0, // dsub1_then_ssub |
| 33498 | 0, // dsub3_then_bsub |
| 33499 | 0, // dsub3_then_hsub |
| 33500 | 0, // dsub3_then_ssub |
| 33501 | 0, // dsub2_then_bsub |
| 33502 | 0, // dsub2_then_hsub |
| 33503 | 0, // dsub2_then_ssub |
| 33504 | 0, // qsub1_then_bsub |
| 33505 | 0, // qsub1_then_dsub |
| 33506 | 0, // qsub1_then_hsub |
| 33507 | 0, // qsub1_then_ssub |
| 33508 | 0, // qsub3_then_bsub |
| 33509 | 0, // qsub3_then_dsub |
| 33510 | 0, // qsub3_then_hsub |
| 33511 | 0, // qsub3_then_ssub |
| 33512 | 0, // qsub2_then_bsub |
| 33513 | 0, // qsub2_then_dsub |
| 33514 | 0, // qsub2_then_hsub |
| 33515 | 0, // qsub2_then_ssub |
| 33516 | 0, // x8sub_7_then_sub_32 |
| 33517 | 0, // x8sub_6_then_sub_32 |
| 33518 | 0, // x8sub_5_then_sub_32 |
| 33519 | 0, // x8sub_4_then_sub_32 |
| 33520 | 0, // x8sub_3_then_sub_32 |
| 33521 | 0, // x8sub_2_then_sub_32 |
| 33522 | 0, // x8sub_1_then_sub_32 |
| 33523 | 0, // subo64_then_sub_32 |
| 33524 | 164, // zsub1_then_bsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33525 | 164, // zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33526 | 164, // zsub1_then_hsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33527 | 164, // zsub1_then_ssub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33528 | 164, // zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33529 | 164, // zsub1_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b |
| 33530 | 164, // zsub3_then_bsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33531 | 164, // zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33532 | 164, // zsub3_then_hsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33533 | 164, // zsub3_then_ssub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33534 | 164, // zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33535 | 164, // zsub3_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b |
| 33536 | 164, // zsub2_then_bsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33537 | 164, // zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33538 | 164, // zsub2_then_hsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33539 | 164, // zsub2_then_ssub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33540 | 164, // zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33541 | 164, // zsub2_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_4b |
| 33542 | 0, // dsub0_dsub1 |
| 33543 | 0, // dsub0_dsub1_dsub2 |
| 33544 | 0, // dsub1_dsub2 |
| 33545 | 0, // dsub1_dsub2_dsub3 |
| 33546 | 0, // dsub2_dsub3 |
| 33547 | 0, // dsub_qsub1_then_dsub |
| 33548 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33549 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 33550 | 0, // qsub0_qsub1 |
| 33551 | 0, // qsub0_qsub1_qsub2 |
| 33552 | 0, // qsub1_qsub2 |
| 33553 | 0, // qsub1_qsub2_qsub3 |
| 33554 | 0, // qsub2_qsub3 |
| 33555 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 33556 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 33557 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 33558 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33559 | 0, // x8sub_0_x8sub_1 |
| 33560 | 0, // x8sub_2_x8sub_3 |
| 33561 | 0, // x8sub_4_x8sub_5 |
| 33562 | 0, // x8sub_6_x8sub_7 |
| 33563 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33564 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33565 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33566 | 0, // sub_32_subo64_then_sub_32 |
| 33567 | 164, // dsub_zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33568 | 164, // zsub_zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33569 | 164, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33570 | 164, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33571 | 164, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33572 | 164, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33573 | 164, // zsub0_zsub1 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33574 | 164, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33575 | 164, // zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33576 | 164, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33577 | 164, // zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_4b |
| 33578 | 164, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33579 | 164, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33580 | 164, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33581 | 164, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33582 | 164, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33583 | 164, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_4b |
| 33584 | }, |
| 33585 | { // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33586 | 165, // bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33587 | 165, // dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33588 | 0, // dsub0 |
| 33589 | 0, // dsub1 |
| 33590 | 0, // dsub2 |
| 33591 | 0, // dsub3 |
| 33592 | 165, // hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33593 | 0, // qhisub |
| 33594 | 0, // qsub |
| 33595 | 165, // qsub0 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33596 | 165, // qsub1 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33597 | 165, // qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33598 | 165, // qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33599 | 165, // ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33600 | 0, // sub_32 |
| 33601 | 0, // sube32 |
| 33602 | 0, // sube64 |
| 33603 | 0, // subo32 |
| 33604 | 0, // subo64 |
| 33605 | 0, // x8sub_0 |
| 33606 | 0, // x8sub_1 |
| 33607 | 0, // x8sub_2 |
| 33608 | 0, // x8sub_3 |
| 33609 | 0, // x8sub_4 |
| 33610 | 0, // x8sub_5 |
| 33611 | 0, // x8sub_6 |
| 33612 | 0, // x8sub_7 |
| 33613 | 0, // zsub |
| 33614 | 0, // zsub0 |
| 33615 | 0, // zsub1 |
| 33616 | 0, // zsub2 |
| 33617 | 0, // zsub3 |
| 33618 | 0, // zsub_hi |
| 33619 | 0, // dsub1_then_bsub |
| 33620 | 0, // dsub1_then_hsub |
| 33621 | 0, // dsub1_then_ssub |
| 33622 | 0, // dsub3_then_bsub |
| 33623 | 0, // dsub3_then_hsub |
| 33624 | 0, // dsub3_then_ssub |
| 33625 | 0, // dsub2_then_bsub |
| 33626 | 0, // dsub2_then_hsub |
| 33627 | 0, // dsub2_then_ssub |
| 33628 | 165, // qsub1_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33629 | 165, // qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33630 | 165, // qsub1_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33631 | 165, // qsub1_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33632 | 165, // qsub3_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33633 | 165, // qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33634 | 165, // qsub3_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33635 | 165, // qsub3_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33636 | 165, // qsub2_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33637 | 165, // qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33638 | 165, // qsub2_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33639 | 165, // qsub2_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33640 | 0, // x8sub_7_then_sub_32 |
| 33641 | 0, // x8sub_6_then_sub_32 |
| 33642 | 0, // x8sub_5_then_sub_32 |
| 33643 | 0, // x8sub_4_then_sub_32 |
| 33644 | 0, // x8sub_3_then_sub_32 |
| 33645 | 0, // x8sub_2_then_sub_32 |
| 33646 | 0, // x8sub_1_then_sub_32 |
| 33647 | 0, // subo64_then_sub_32 |
| 33648 | 0, // zsub1_then_bsub |
| 33649 | 0, // zsub1_then_dsub |
| 33650 | 0, // zsub1_then_hsub |
| 33651 | 0, // zsub1_then_ssub |
| 33652 | 0, // zsub1_then_zsub |
| 33653 | 0, // zsub1_then_zsub_hi |
| 33654 | 0, // zsub3_then_bsub |
| 33655 | 0, // zsub3_then_dsub |
| 33656 | 0, // zsub3_then_hsub |
| 33657 | 0, // zsub3_then_ssub |
| 33658 | 0, // zsub3_then_zsub |
| 33659 | 0, // zsub3_then_zsub_hi |
| 33660 | 0, // zsub2_then_bsub |
| 33661 | 0, // zsub2_then_dsub |
| 33662 | 0, // zsub2_then_hsub |
| 33663 | 0, // zsub2_then_ssub |
| 33664 | 0, // zsub2_then_zsub |
| 33665 | 0, // zsub2_then_zsub_hi |
| 33666 | 0, // dsub0_dsub1 |
| 33667 | 0, // dsub0_dsub1_dsub2 |
| 33668 | 0, // dsub1_dsub2 |
| 33669 | 0, // dsub1_dsub2_dsub3 |
| 33670 | 0, // dsub2_dsub3 |
| 33671 | 165, // dsub_qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33672 | 165, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33673 | 165, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33674 | 165, // qsub0_qsub1 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33675 | 165, // qsub0_qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33676 | 165, // qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33677 | 165, // qsub1_qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33678 | 165, // qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33679 | 165, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33680 | 165, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33681 | 165, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 33682 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33683 | 0, // x8sub_0_x8sub_1 |
| 33684 | 0, // x8sub_2_x8sub_3 |
| 33685 | 0, // x8sub_4_x8sub_5 |
| 33686 | 0, // x8sub_6_x8sub_7 |
| 33687 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33688 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33689 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33690 | 0, // sub_32_subo64_then_sub_32 |
| 33691 | 0, // dsub_zsub1_then_dsub |
| 33692 | 0, // zsub_zsub1_then_zsub |
| 33693 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33694 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 33695 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33696 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 33697 | 0, // zsub0_zsub1 |
| 33698 | 0, // zsub0_zsub1_zsub2 |
| 33699 | 0, // zsub1_zsub2 |
| 33700 | 0, // zsub1_zsub2_zsub3 |
| 33701 | 0, // zsub2_zsub3 |
| 33702 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 33703 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33704 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 33705 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33706 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 33707 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 33708 | }, |
| 33709 | { // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33710 | 166, // bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33711 | 166, // dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33712 | 0, // dsub0 |
| 33713 | 0, // dsub1 |
| 33714 | 0, // dsub2 |
| 33715 | 0, // dsub3 |
| 33716 | 166, // hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33717 | 0, // qhisub |
| 33718 | 0, // qsub |
| 33719 | 166, // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33720 | 166, // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33721 | 166, // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33722 | 166, // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33723 | 166, // ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33724 | 0, // sub_32 |
| 33725 | 0, // sube32 |
| 33726 | 0, // sube64 |
| 33727 | 0, // subo32 |
| 33728 | 0, // subo64 |
| 33729 | 0, // x8sub_0 |
| 33730 | 0, // x8sub_1 |
| 33731 | 0, // x8sub_2 |
| 33732 | 0, // x8sub_3 |
| 33733 | 0, // x8sub_4 |
| 33734 | 0, // x8sub_5 |
| 33735 | 0, // x8sub_6 |
| 33736 | 0, // x8sub_7 |
| 33737 | 0, // zsub |
| 33738 | 0, // zsub0 |
| 33739 | 0, // zsub1 |
| 33740 | 0, // zsub2 |
| 33741 | 0, // zsub3 |
| 33742 | 0, // zsub_hi |
| 33743 | 0, // dsub1_then_bsub |
| 33744 | 0, // dsub1_then_hsub |
| 33745 | 0, // dsub1_then_ssub |
| 33746 | 0, // dsub3_then_bsub |
| 33747 | 0, // dsub3_then_hsub |
| 33748 | 0, // dsub3_then_ssub |
| 33749 | 0, // dsub2_then_bsub |
| 33750 | 0, // dsub2_then_hsub |
| 33751 | 0, // dsub2_then_ssub |
| 33752 | 166, // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33753 | 166, // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33754 | 166, // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33755 | 166, // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33756 | 166, // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33757 | 166, // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33758 | 166, // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33759 | 166, // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33760 | 166, // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33761 | 166, // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33762 | 166, // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33763 | 166, // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33764 | 0, // x8sub_7_then_sub_32 |
| 33765 | 0, // x8sub_6_then_sub_32 |
| 33766 | 0, // x8sub_5_then_sub_32 |
| 33767 | 0, // x8sub_4_then_sub_32 |
| 33768 | 0, // x8sub_3_then_sub_32 |
| 33769 | 0, // x8sub_2_then_sub_32 |
| 33770 | 0, // x8sub_1_then_sub_32 |
| 33771 | 0, // subo64_then_sub_32 |
| 33772 | 0, // zsub1_then_bsub |
| 33773 | 0, // zsub1_then_dsub |
| 33774 | 0, // zsub1_then_hsub |
| 33775 | 0, // zsub1_then_ssub |
| 33776 | 0, // zsub1_then_zsub |
| 33777 | 0, // zsub1_then_zsub_hi |
| 33778 | 0, // zsub3_then_bsub |
| 33779 | 0, // zsub3_then_dsub |
| 33780 | 0, // zsub3_then_hsub |
| 33781 | 0, // zsub3_then_ssub |
| 33782 | 0, // zsub3_then_zsub |
| 33783 | 0, // zsub3_then_zsub_hi |
| 33784 | 0, // zsub2_then_bsub |
| 33785 | 0, // zsub2_then_dsub |
| 33786 | 0, // zsub2_then_hsub |
| 33787 | 0, // zsub2_then_ssub |
| 33788 | 0, // zsub2_then_zsub |
| 33789 | 0, // zsub2_then_zsub_hi |
| 33790 | 0, // dsub0_dsub1 |
| 33791 | 0, // dsub0_dsub1_dsub2 |
| 33792 | 0, // dsub1_dsub2 |
| 33793 | 0, // dsub1_dsub2_dsub3 |
| 33794 | 0, // dsub2_dsub3 |
| 33795 | 166, // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33796 | 166, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33797 | 166, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33798 | 166, // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33799 | 166, // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33800 | 166, // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33801 | 166, // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33802 | 166, // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33803 | 166, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33804 | 166, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33805 | 166, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 33806 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33807 | 0, // x8sub_0_x8sub_1 |
| 33808 | 0, // x8sub_2_x8sub_3 |
| 33809 | 0, // x8sub_4_x8sub_5 |
| 33810 | 0, // x8sub_6_x8sub_7 |
| 33811 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33812 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33813 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33814 | 0, // sub_32_subo64_then_sub_32 |
| 33815 | 0, // dsub_zsub1_then_dsub |
| 33816 | 0, // zsub_zsub1_then_zsub |
| 33817 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33818 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 33819 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33820 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 33821 | 0, // zsub0_zsub1 |
| 33822 | 0, // zsub0_zsub1_zsub2 |
| 33823 | 0, // zsub1_zsub2 |
| 33824 | 0, // zsub1_zsub2_zsub3 |
| 33825 | 0, // zsub2_zsub3 |
| 33826 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 33827 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33828 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 33829 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33830 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 33831 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 33832 | }, |
| 33833 | { // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33834 | 167, // bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33835 | 167, // dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33836 | 0, // dsub0 |
| 33837 | 0, // dsub1 |
| 33838 | 0, // dsub2 |
| 33839 | 0, // dsub3 |
| 33840 | 167, // hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33841 | 0, // qhisub |
| 33842 | 0, // qsub |
| 33843 | 167, // qsub0 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33844 | 167, // qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33845 | 167, // qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33846 | 167, // qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33847 | 167, // ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33848 | 0, // sub_32 |
| 33849 | 0, // sube32 |
| 33850 | 0, // sube64 |
| 33851 | 0, // subo32 |
| 33852 | 0, // subo64 |
| 33853 | 0, // x8sub_0 |
| 33854 | 0, // x8sub_1 |
| 33855 | 0, // x8sub_2 |
| 33856 | 0, // x8sub_3 |
| 33857 | 0, // x8sub_4 |
| 33858 | 0, // x8sub_5 |
| 33859 | 0, // x8sub_6 |
| 33860 | 0, // x8sub_7 |
| 33861 | 0, // zsub |
| 33862 | 0, // zsub0 |
| 33863 | 0, // zsub1 |
| 33864 | 0, // zsub2 |
| 33865 | 0, // zsub3 |
| 33866 | 0, // zsub_hi |
| 33867 | 0, // dsub1_then_bsub |
| 33868 | 0, // dsub1_then_hsub |
| 33869 | 0, // dsub1_then_ssub |
| 33870 | 0, // dsub3_then_bsub |
| 33871 | 0, // dsub3_then_hsub |
| 33872 | 0, // dsub3_then_ssub |
| 33873 | 0, // dsub2_then_bsub |
| 33874 | 0, // dsub2_then_hsub |
| 33875 | 0, // dsub2_then_ssub |
| 33876 | 167, // qsub1_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33877 | 167, // qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33878 | 167, // qsub1_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33879 | 167, // qsub1_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33880 | 167, // qsub3_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33881 | 167, // qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33882 | 167, // qsub3_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33883 | 167, // qsub3_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33884 | 167, // qsub2_then_bsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33885 | 167, // qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33886 | 167, // qsub2_then_hsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33887 | 167, // qsub2_then_ssub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33888 | 0, // x8sub_7_then_sub_32 |
| 33889 | 0, // x8sub_6_then_sub_32 |
| 33890 | 0, // x8sub_5_then_sub_32 |
| 33891 | 0, // x8sub_4_then_sub_32 |
| 33892 | 0, // x8sub_3_then_sub_32 |
| 33893 | 0, // x8sub_2_then_sub_32 |
| 33894 | 0, // x8sub_1_then_sub_32 |
| 33895 | 0, // subo64_then_sub_32 |
| 33896 | 0, // zsub1_then_bsub |
| 33897 | 0, // zsub1_then_dsub |
| 33898 | 0, // zsub1_then_hsub |
| 33899 | 0, // zsub1_then_ssub |
| 33900 | 0, // zsub1_then_zsub |
| 33901 | 0, // zsub1_then_zsub_hi |
| 33902 | 0, // zsub3_then_bsub |
| 33903 | 0, // zsub3_then_dsub |
| 33904 | 0, // zsub3_then_hsub |
| 33905 | 0, // zsub3_then_ssub |
| 33906 | 0, // zsub3_then_zsub |
| 33907 | 0, // zsub3_then_zsub_hi |
| 33908 | 0, // zsub2_then_bsub |
| 33909 | 0, // zsub2_then_dsub |
| 33910 | 0, // zsub2_then_hsub |
| 33911 | 0, // zsub2_then_ssub |
| 33912 | 0, // zsub2_then_zsub |
| 33913 | 0, // zsub2_then_zsub_hi |
| 33914 | 0, // dsub0_dsub1 |
| 33915 | 0, // dsub0_dsub1_dsub2 |
| 33916 | 0, // dsub1_dsub2 |
| 33917 | 0, // dsub1_dsub2_dsub3 |
| 33918 | 0, // dsub2_dsub3 |
| 33919 | 167, // dsub_qsub1_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33920 | 167, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33921 | 167, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33922 | 167, // qsub0_qsub1 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33923 | 167, // qsub0_qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33924 | 167, // qsub1_qsub2 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33925 | 167, // qsub1_qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33926 | 167, // qsub2_qsub3 -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33927 | 167, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33928 | 167, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33929 | 167, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 33930 | 0, // sub_32_x8sub_1_then_sub_32 |
| 33931 | 0, // x8sub_0_x8sub_1 |
| 33932 | 0, // x8sub_2_x8sub_3 |
| 33933 | 0, // x8sub_4_x8sub_5 |
| 33934 | 0, // x8sub_6_x8sub_7 |
| 33935 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 33936 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 33937 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 33938 | 0, // sub_32_subo64_then_sub_32 |
| 33939 | 0, // dsub_zsub1_then_dsub |
| 33940 | 0, // zsub_zsub1_then_zsub |
| 33941 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33942 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 33943 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33944 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 33945 | 0, // zsub0_zsub1 |
| 33946 | 0, // zsub0_zsub1_zsub2 |
| 33947 | 0, // zsub1_zsub2 |
| 33948 | 0, // zsub1_zsub2_zsub3 |
| 33949 | 0, // zsub2_zsub3 |
| 33950 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 33951 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 33952 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 33953 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 33954 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 33955 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 33956 | }, |
| 33957 | { // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33958 | 168, // bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33959 | 168, // dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33960 | 0, // dsub0 |
| 33961 | 0, // dsub1 |
| 33962 | 0, // dsub2 |
| 33963 | 0, // dsub3 |
| 33964 | 168, // hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33965 | 0, // qhisub |
| 33966 | 0, // qsub |
| 33967 | 0, // qsub0 |
| 33968 | 0, // qsub1 |
| 33969 | 0, // qsub2 |
| 33970 | 0, // qsub3 |
| 33971 | 168, // ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33972 | 0, // sub_32 |
| 33973 | 0, // sube32 |
| 33974 | 0, // sube64 |
| 33975 | 0, // subo32 |
| 33976 | 0, // subo64 |
| 33977 | 0, // x8sub_0 |
| 33978 | 0, // x8sub_1 |
| 33979 | 0, // x8sub_2 |
| 33980 | 0, // x8sub_3 |
| 33981 | 0, // x8sub_4 |
| 33982 | 0, // x8sub_5 |
| 33983 | 0, // x8sub_6 |
| 33984 | 0, // x8sub_7 |
| 33985 | 168, // zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33986 | 168, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33987 | 168, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33988 | 168, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33989 | 168, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33990 | 168, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 33991 | 0, // dsub1_then_bsub |
| 33992 | 0, // dsub1_then_hsub |
| 33993 | 0, // dsub1_then_ssub |
| 33994 | 0, // dsub3_then_bsub |
| 33995 | 0, // dsub3_then_hsub |
| 33996 | 0, // dsub3_then_ssub |
| 33997 | 0, // dsub2_then_bsub |
| 33998 | 0, // dsub2_then_hsub |
| 33999 | 0, // dsub2_then_ssub |
| 34000 | 0, // qsub1_then_bsub |
| 34001 | 0, // qsub1_then_dsub |
| 34002 | 0, // qsub1_then_hsub |
| 34003 | 0, // qsub1_then_ssub |
| 34004 | 0, // qsub3_then_bsub |
| 34005 | 0, // qsub3_then_dsub |
| 34006 | 0, // qsub3_then_hsub |
| 34007 | 0, // qsub3_then_ssub |
| 34008 | 0, // qsub2_then_bsub |
| 34009 | 0, // qsub2_then_dsub |
| 34010 | 0, // qsub2_then_hsub |
| 34011 | 0, // qsub2_then_ssub |
| 34012 | 0, // x8sub_7_then_sub_32 |
| 34013 | 0, // x8sub_6_then_sub_32 |
| 34014 | 0, // x8sub_5_then_sub_32 |
| 34015 | 0, // x8sub_4_then_sub_32 |
| 34016 | 0, // x8sub_3_then_sub_32 |
| 34017 | 0, // x8sub_2_then_sub_32 |
| 34018 | 0, // x8sub_1_then_sub_32 |
| 34019 | 0, // subo64_then_sub_32 |
| 34020 | 168, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34021 | 168, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34022 | 168, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34023 | 168, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34024 | 168, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34025 | 168, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34026 | 168, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34027 | 168, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34028 | 168, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34029 | 168, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34030 | 168, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34031 | 168, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34032 | 168, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34033 | 168, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34034 | 168, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34035 | 168, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34036 | 168, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34037 | 168, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34038 | 0, // dsub0_dsub1 |
| 34039 | 0, // dsub0_dsub1_dsub2 |
| 34040 | 0, // dsub1_dsub2 |
| 34041 | 0, // dsub1_dsub2_dsub3 |
| 34042 | 0, // dsub2_dsub3 |
| 34043 | 0, // dsub_qsub1_then_dsub |
| 34044 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34045 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 34046 | 0, // qsub0_qsub1 |
| 34047 | 0, // qsub0_qsub1_qsub2 |
| 34048 | 0, // qsub1_qsub2 |
| 34049 | 0, // qsub1_qsub2_qsub3 |
| 34050 | 0, // qsub2_qsub3 |
| 34051 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 34052 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34053 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 34054 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34055 | 0, // x8sub_0_x8sub_1 |
| 34056 | 0, // x8sub_2_x8sub_3 |
| 34057 | 0, // x8sub_4_x8sub_5 |
| 34058 | 0, // x8sub_6_x8sub_7 |
| 34059 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34060 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34061 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34062 | 0, // sub_32_subo64_then_sub_32 |
| 34063 | 168, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34064 | 168, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34065 | 168, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34066 | 168, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34067 | 168, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34068 | 168, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34069 | 168, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34070 | 168, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34071 | 168, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34072 | 168, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34073 | 168, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34074 | 168, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34075 | 168, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34076 | 168, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34077 | 168, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34078 | 168, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34079 | 168, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 34080 | }, |
| 34081 | { // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34082 | 169, // bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34083 | 169, // dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34084 | 0, // dsub0 |
| 34085 | 0, // dsub1 |
| 34086 | 0, // dsub2 |
| 34087 | 0, // dsub3 |
| 34088 | 169, // hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34089 | 0, // qhisub |
| 34090 | 0, // qsub |
| 34091 | 0, // qsub0 |
| 34092 | 0, // qsub1 |
| 34093 | 0, // qsub2 |
| 34094 | 0, // qsub3 |
| 34095 | 169, // ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34096 | 0, // sub_32 |
| 34097 | 0, // sube32 |
| 34098 | 0, // sube64 |
| 34099 | 0, // subo32 |
| 34100 | 0, // subo64 |
| 34101 | 0, // x8sub_0 |
| 34102 | 0, // x8sub_1 |
| 34103 | 0, // x8sub_2 |
| 34104 | 0, // x8sub_3 |
| 34105 | 0, // x8sub_4 |
| 34106 | 0, // x8sub_5 |
| 34107 | 0, // x8sub_6 |
| 34108 | 0, // x8sub_7 |
| 34109 | 169, // zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34110 | 169, // zsub0 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34111 | 169, // zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34112 | 169, // zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34113 | 169, // zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34114 | 169, // zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34115 | 0, // dsub1_then_bsub |
| 34116 | 0, // dsub1_then_hsub |
| 34117 | 0, // dsub1_then_ssub |
| 34118 | 0, // dsub3_then_bsub |
| 34119 | 0, // dsub3_then_hsub |
| 34120 | 0, // dsub3_then_ssub |
| 34121 | 0, // dsub2_then_bsub |
| 34122 | 0, // dsub2_then_hsub |
| 34123 | 0, // dsub2_then_ssub |
| 34124 | 0, // qsub1_then_bsub |
| 34125 | 0, // qsub1_then_dsub |
| 34126 | 0, // qsub1_then_hsub |
| 34127 | 0, // qsub1_then_ssub |
| 34128 | 0, // qsub3_then_bsub |
| 34129 | 0, // qsub3_then_dsub |
| 34130 | 0, // qsub3_then_hsub |
| 34131 | 0, // qsub3_then_ssub |
| 34132 | 0, // qsub2_then_bsub |
| 34133 | 0, // qsub2_then_dsub |
| 34134 | 0, // qsub2_then_hsub |
| 34135 | 0, // qsub2_then_ssub |
| 34136 | 0, // x8sub_7_then_sub_32 |
| 34137 | 0, // x8sub_6_then_sub_32 |
| 34138 | 0, // x8sub_5_then_sub_32 |
| 34139 | 0, // x8sub_4_then_sub_32 |
| 34140 | 0, // x8sub_3_then_sub_32 |
| 34141 | 0, // x8sub_2_then_sub_32 |
| 34142 | 0, // x8sub_1_then_sub_32 |
| 34143 | 0, // subo64_then_sub_32 |
| 34144 | 169, // zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34145 | 169, // zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34146 | 169, // zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34147 | 169, // zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34148 | 169, // zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34149 | 169, // zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34150 | 169, // zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34151 | 169, // zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34152 | 169, // zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34153 | 169, // zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34154 | 169, // zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34155 | 169, // zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34156 | 169, // zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34157 | 169, // zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34158 | 169, // zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34159 | 169, // zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34160 | 169, // zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34161 | 169, // zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34162 | 0, // dsub0_dsub1 |
| 34163 | 0, // dsub0_dsub1_dsub2 |
| 34164 | 0, // dsub1_dsub2 |
| 34165 | 0, // dsub1_dsub2_dsub3 |
| 34166 | 0, // dsub2_dsub3 |
| 34167 | 0, // dsub_qsub1_then_dsub |
| 34168 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34169 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 34170 | 0, // qsub0_qsub1 |
| 34171 | 0, // qsub0_qsub1_qsub2 |
| 34172 | 0, // qsub1_qsub2 |
| 34173 | 0, // qsub1_qsub2_qsub3 |
| 34174 | 0, // qsub2_qsub3 |
| 34175 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 34176 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34177 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 34178 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34179 | 0, // x8sub_0_x8sub_1 |
| 34180 | 0, // x8sub_2_x8sub_3 |
| 34181 | 0, // x8sub_4_x8sub_5 |
| 34182 | 0, // x8sub_6_x8sub_7 |
| 34183 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34184 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34185 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34186 | 0, // sub_32_subo64_then_sub_32 |
| 34187 | 169, // dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34188 | 169, // zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34189 | 169, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34190 | 169, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34191 | 169, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34192 | 169, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34193 | 169, // zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34194 | 169, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34195 | 169, // zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34196 | 169, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34197 | 169, // zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34198 | 169, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34199 | 169, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34200 | 169, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34201 | 169, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34202 | 169, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34203 | 169, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34204 | }, |
| 34205 | { // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34206 | 170, // bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34207 | 170, // dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34208 | 0, // dsub0 |
| 34209 | 0, // dsub1 |
| 34210 | 0, // dsub2 |
| 34211 | 0, // dsub3 |
| 34212 | 170, // hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34213 | 0, // qhisub |
| 34214 | 0, // qsub |
| 34215 | 0, // qsub0 |
| 34216 | 0, // qsub1 |
| 34217 | 0, // qsub2 |
| 34218 | 0, // qsub3 |
| 34219 | 170, // ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34220 | 0, // sub_32 |
| 34221 | 0, // sube32 |
| 34222 | 0, // sube64 |
| 34223 | 0, // subo32 |
| 34224 | 0, // subo64 |
| 34225 | 0, // x8sub_0 |
| 34226 | 0, // x8sub_1 |
| 34227 | 0, // x8sub_2 |
| 34228 | 0, // x8sub_3 |
| 34229 | 0, // x8sub_4 |
| 34230 | 0, // x8sub_5 |
| 34231 | 0, // x8sub_6 |
| 34232 | 0, // x8sub_7 |
| 34233 | 170, // zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34234 | 170, // zsub0 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34235 | 170, // zsub1 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34236 | 170, // zsub2 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34237 | 170, // zsub3 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34238 | 170, // zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34239 | 0, // dsub1_then_bsub |
| 34240 | 0, // dsub1_then_hsub |
| 34241 | 0, // dsub1_then_ssub |
| 34242 | 0, // dsub3_then_bsub |
| 34243 | 0, // dsub3_then_hsub |
| 34244 | 0, // dsub3_then_ssub |
| 34245 | 0, // dsub2_then_bsub |
| 34246 | 0, // dsub2_then_hsub |
| 34247 | 0, // dsub2_then_ssub |
| 34248 | 0, // qsub1_then_bsub |
| 34249 | 0, // qsub1_then_dsub |
| 34250 | 0, // qsub1_then_hsub |
| 34251 | 0, // qsub1_then_ssub |
| 34252 | 0, // qsub3_then_bsub |
| 34253 | 0, // qsub3_then_dsub |
| 34254 | 0, // qsub3_then_hsub |
| 34255 | 0, // qsub3_then_ssub |
| 34256 | 0, // qsub2_then_bsub |
| 34257 | 0, // qsub2_then_dsub |
| 34258 | 0, // qsub2_then_hsub |
| 34259 | 0, // qsub2_then_ssub |
| 34260 | 0, // x8sub_7_then_sub_32 |
| 34261 | 0, // x8sub_6_then_sub_32 |
| 34262 | 0, // x8sub_5_then_sub_32 |
| 34263 | 0, // x8sub_4_then_sub_32 |
| 34264 | 0, // x8sub_3_then_sub_32 |
| 34265 | 0, // x8sub_2_then_sub_32 |
| 34266 | 0, // x8sub_1_then_sub_32 |
| 34267 | 0, // subo64_then_sub_32 |
| 34268 | 170, // zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34269 | 170, // zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34270 | 170, // zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34271 | 170, // zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34272 | 170, // zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34273 | 170, // zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34274 | 170, // zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34275 | 170, // zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34276 | 170, // zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34277 | 170, // zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34278 | 170, // zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34279 | 170, // zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34280 | 170, // zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34281 | 170, // zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34282 | 170, // zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34283 | 170, // zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34284 | 170, // zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34285 | 170, // zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34286 | 0, // dsub0_dsub1 |
| 34287 | 0, // dsub0_dsub1_dsub2 |
| 34288 | 0, // dsub1_dsub2 |
| 34289 | 0, // dsub1_dsub2_dsub3 |
| 34290 | 0, // dsub2_dsub3 |
| 34291 | 0, // dsub_qsub1_then_dsub |
| 34292 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34293 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 34294 | 0, // qsub0_qsub1 |
| 34295 | 0, // qsub0_qsub1_qsub2 |
| 34296 | 0, // qsub1_qsub2 |
| 34297 | 0, // qsub1_qsub2_qsub3 |
| 34298 | 0, // qsub2_qsub3 |
| 34299 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 34300 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34301 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 34302 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34303 | 0, // x8sub_0_x8sub_1 |
| 34304 | 0, // x8sub_2_x8sub_3 |
| 34305 | 0, // x8sub_4_x8sub_5 |
| 34306 | 0, // x8sub_6_x8sub_7 |
| 34307 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34308 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34309 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34310 | 0, // sub_32_subo64_then_sub_32 |
| 34311 | 170, // dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34312 | 170, // zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34313 | 170, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34314 | 170, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34315 | 170, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34316 | 170, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34317 | 170, // zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34318 | 170, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34319 | 170, // zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34320 | 170, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34321 | 170, // zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34322 | 170, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34323 | 170, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34324 | 170, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34325 | 170, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34326 | 170, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34327 | 170, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34328 | }, |
| 34329 | { // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34330 | 171, // bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34331 | 171, // dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34332 | 0, // dsub0 |
| 34333 | 0, // dsub1 |
| 34334 | 0, // dsub2 |
| 34335 | 0, // dsub3 |
| 34336 | 171, // hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34337 | 0, // qhisub |
| 34338 | 0, // qsub |
| 34339 | 171, // qsub0 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34340 | 171, // qsub1 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34341 | 171, // qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34342 | 171, // qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34343 | 171, // ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34344 | 0, // sub_32 |
| 34345 | 0, // sube32 |
| 34346 | 0, // sube64 |
| 34347 | 0, // subo32 |
| 34348 | 0, // subo64 |
| 34349 | 0, // x8sub_0 |
| 34350 | 0, // x8sub_1 |
| 34351 | 0, // x8sub_2 |
| 34352 | 0, // x8sub_3 |
| 34353 | 0, // x8sub_4 |
| 34354 | 0, // x8sub_5 |
| 34355 | 0, // x8sub_6 |
| 34356 | 0, // x8sub_7 |
| 34357 | 0, // zsub |
| 34358 | 0, // zsub0 |
| 34359 | 0, // zsub1 |
| 34360 | 0, // zsub2 |
| 34361 | 0, // zsub3 |
| 34362 | 0, // zsub_hi |
| 34363 | 0, // dsub1_then_bsub |
| 34364 | 0, // dsub1_then_hsub |
| 34365 | 0, // dsub1_then_ssub |
| 34366 | 0, // dsub3_then_bsub |
| 34367 | 0, // dsub3_then_hsub |
| 34368 | 0, // dsub3_then_ssub |
| 34369 | 0, // dsub2_then_bsub |
| 34370 | 0, // dsub2_then_hsub |
| 34371 | 0, // dsub2_then_ssub |
| 34372 | 171, // qsub1_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34373 | 171, // qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34374 | 171, // qsub1_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34375 | 171, // qsub1_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34376 | 171, // qsub3_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34377 | 171, // qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34378 | 171, // qsub3_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34379 | 171, // qsub3_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34380 | 171, // qsub2_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34381 | 171, // qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34382 | 171, // qsub2_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34383 | 171, // qsub2_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34384 | 0, // x8sub_7_then_sub_32 |
| 34385 | 0, // x8sub_6_then_sub_32 |
| 34386 | 0, // x8sub_5_then_sub_32 |
| 34387 | 0, // x8sub_4_then_sub_32 |
| 34388 | 0, // x8sub_3_then_sub_32 |
| 34389 | 0, // x8sub_2_then_sub_32 |
| 34390 | 0, // x8sub_1_then_sub_32 |
| 34391 | 0, // subo64_then_sub_32 |
| 34392 | 0, // zsub1_then_bsub |
| 34393 | 0, // zsub1_then_dsub |
| 34394 | 0, // zsub1_then_hsub |
| 34395 | 0, // zsub1_then_ssub |
| 34396 | 0, // zsub1_then_zsub |
| 34397 | 0, // zsub1_then_zsub_hi |
| 34398 | 0, // zsub3_then_bsub |
| 34399 | 0, // zsub3_then_dsub |
| 34400 | 0, // zsub3_then_hsub |
| 34401 | 0, // zsub3_then_ssub |
| 34402 | 0, // zsub3_then_zsub |
| 34403 | 0, // zsub3_then_zsub_hi |
| 34404 | 0, // zsub2_then_bsub |
| 34405 | 0, // zsub2_then_dsub |
| 34406 | 0, // zsub2_then_hsub |
| 34407 | 0, // zsub2_then_ssub |
| 34408 | 0, // zsub2_then_zsub |
| 34409 | 0, // zsub2_then_zsub_hi |
| 34410 | 0, // dsub0_dsub1 |
| 34411 | 0, // dsub0_dsub1_dsub2 |
| 34412 | 0, // dsub1_dsub2 |
| 34413 | 0, // dsub1_dsub2_dsub3 |
| 34414 | 0, // dsub2_dsub3 |
| 34415 | 171, // dsub_qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34416 | 171, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34417 | 171, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34418 | 171, // qsub0_qsub1 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34419 | 171, // qsub0_qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34420 | 171, // qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34421 | 171, // qsub1_qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34422 | 171, // qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34423 | 171, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34424 | 171, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34425 | 171, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 34426 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34427 | 0, // x8sub_0_x8sub_1 |
| 34428 | 0, // x8sub_2_x8sub_3 |
| 34429 | 0, // x8sub_4_x8sub_5 |
| 34430 | 0, // x8sub_6_x8sub_7 |
| 34431 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34432 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34433 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34434 | 0, // sub_32_subo64_then_sub_32 |
| 34435 | 0, // dsub_zsub1_then_dsub |
| 34436 | 0, // zsub_zsub1_then_zsub |
| 34437 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 34438 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 34439 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 34440 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 34441 | 0, // zsub0_zsub1 |
| 34442 | 0, // zsub0_zsub1_zsub2 |
| 34443 | 0, // zsub1_zsub2 |
| 34444 | 0, // zsub1_zsub2_zsub3 |
| 34445 | 0, // zsub2_zsub3 |
| 34446 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 34447 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 34448 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 34449 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 34450 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 34451 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 34452 | }, |
| 34453 | { // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34454 | 172, // bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34455 | 172, // dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34456 | 0, // dsub0 |
| 34457 | 0, // dsub1 |
| 34458 | 0, // dsub2 |
| 34459 | 0, // dsub3 |
| 34460 | 172, // hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34461 | 0, // qhisub |
| 34462 | 0, // qsub |
| 34463 | 172, // qsub0 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34464 | 172, // qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34465 | 172, // qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34466 | 172, // qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34467 | 172, // ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34468 | 0, // sub_32 |
| 34469 | 0, // sube32 |
| 34470 | 0, // sube64 |
| 34471 | 0, // subo32 |
| 34472 | 0, // subo64 |
| 34473 | 0, // x8sub_0 |
| 34474 | 0, // x8sub_1 |
| 34475 | 0, // x8sub_2 |
| 34476 | 0, // x8sub_3 |
| 34477 | 0, // x8sub_4 |
| 34478 | 0, // x8sub_5 |
| 34479 | 0, // x8sub_6 |
| 34480 | 0, // x8sub_7 |
| 34481 | 0, // zsub |
| 34482 | 0, // zsub0 |
| 34483 | 0, // zsub1 |
| 34484 | 0, // zsub2 |
| 34485 | 0, // zsub3 |
| 34486 | 0, // zsub_hi |
| 34487 | 0, // dsub1_then_bsub |
| 34488 | 0, // dsub1_then_hsub |
| 34489 | 0, // dsub1_then_ssub |
| 34490 | 0, // dsub3_then_bsub |
| 34491 | 0, // dsub3_then_hsub |
| 34492 | 0, // dsub3_then_ssub |
| 34493 | 0, // dsub2_then_bsub |
| 34494 | 0, // dsub2_then_hsub |
| 34495 | 0, // dsub2_then_ssub |
| 34496 | 172, // qsub1_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34497 | 172, // qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34498 | 172, // qsub1_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34499 | 172, // qsub1_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34500 | 172, // qsub3_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34501 | 172, // qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34502 | 172, // qsub3_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34503 | 172, // qsub3_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34504 | 172, // qsub2_then_bsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34505 | 172, // qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34506 | 172, // qsub2_then_hsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34507 | 172, // qsub2_then_ssub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34508 | 0, // x8sub_7_then_sub_32 |
| 34509 | 0, // x8sub_6_then_sub_32 |
| 34510 | 0, // x8sub_5_then_sub_32 |
| 34511 | 0, // x8sub_4_then_sub_32 |
| 34512 | 0, // x8sub_3_then_sub_32 |
| 34513 | 0, // x8sub_2_then_sub_32 |
| 34514 | 0, // x8sub_1_then_sub_32 |
| 34515 | 0, // subo64_then_sub_32 |
| 34516 | 0, // zsub1_then_bsub |
| 34517 | 0, // zsub1_then_dsub |
| 34518 | 0, // zsub1_then_hsub |
| 34519 | 0, // zsub1_then_ssub |
| 34520 | 0, // zsub1_then_zsub |
| 34521 | 0, // zsub1_then_zsub_hi |
| 34522 | 0, // zsub3_then_bsub |
| 34523 | 0, // zsub3_then_dsub |
| 34524 | 0, // zsub3_then_hsub |
| 34525 | 0, // zsub3_then_ssub |
| 34526 | 0, // zsub3_then_zsub |
| 34527 | 0, // zsub3_then_zsub_hi |
| 34528 | 0, // zsub2_then_bsub |
| 34529 | 0, // zsub2_then_dsub |
| 34530 | 0, // zsub2_then_hsub |
| 34531 | 0, // zsub2_then_ssub |
| 34532 | 0, // zsub2_then_zsub |
| 34533 | 0, // zsub2_then_zsub_hi |
| 34534 | 0, // dsub0_dsub1 |
| 34535 | 0, // dsub0_dsub1_dsub2 |
| 34536 | 0, // dsub1_dsub2 |
| 34537 | 0, // dsub1_dsub2_dsub3 |
| 34538 | 0, // dsub2_dsub3 |
| 34539 | 172, // dsub_qsub1_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34540 | 172, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34541 | 172, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34542 | 172, // qsub0_qsub1 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34543 | 172, // qsub0_qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34544 | 172, // qsub1_qsub2 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34545 | 172, // qsub1_qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34546 | 172, // qsub2_qsub3 -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34547 | 172, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34548 | 172, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34549 | 172, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34550 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34551 | 0, // x8sub_0_x8sub_1 |
| 34552 | 0, // x8sub_2_x8sub_3 |
| 34553 | 0, // x8sub_4_x8sub_5 |
| 34554 | 0, // x8sub_6_x8sub_7 |
| 34555 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34556 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34557 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34558 | 0, // sub_32_subo64_then_sub_32 |
| 34559 | 0, // dsub_zsub1_then_dsub |
| 34560 | 0, // zsub_zsub1_then_zsub |
| 34561 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 34562 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 34563 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 34564 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 34565 | 0, // zsub0_zsub1 |
| 34566 | 0, // zsub0_zsub1_zsub2 |
| 34567 | 0, // zsub1_zsub2 |
| 34568 | 0, // zsub1_zsub2_zsub3 |
| 34569 | 0, // zsub2_zsub3 |
| 34570 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 34571 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 34572 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 34573 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 34574 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 34575 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 34576 | }, |
| 34577 | { // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34578 | 173, // bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34579 | 173, // dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34580 | 0, // dsub0 |
| 34581 | 0, // dsub1 |
| 34582 | 0, // dsub2 |
| 34583 | 0, // dsub3 |
| 34584 | 173, // hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34585 | 0, // qhisub |
| 34586 | 0, // qsub |
| 34587 | 0, // qsub0 |
| 34588 | 0, // qsub1 |
| 34589 | 0, // qsub2 |
| 34590 | 0, // qsub3 |
| 34591 | 173, // ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34592 | 0, // sub_32 |
| 34593 | 0, // sube32 |
| 34594 | 0, // sube64 |
| 34595 | 0, // subo32 |
| 34596 | 0, // subo64 |
| 34597 | 0, // x8sub_0 |
| 34598 | 0, // x8sub_1 |
| 34599 | 0, // x8sub_2 |
| 34600 | 0, // x8sub_3 |
| 34601 | 0, // x8sub_4 |
| 34602 | 0, // x8sub_5 |
| 34603 | 0, // x8sub_6 |
| 34604 | 0, // x8sub_7 |
| 34605 | 173, // zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34606 | 173, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34607 | 173, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34608 | 173, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34609 | 173, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34610 | 173, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34611 | 0, // dsub1_then_bsub |
| 34612 | 0, // dsub1_then_hsub |
| 34613 | 0, // dsub1_then_ssub |
| 34614 | 0, // dsub3_then_bsub |
| 34615 | 0, // dsub3_then_hsub |
| 34616 | 0, // dsub3_then_ssub |
| 34617 | 0, // dsub2_then_bsub |
| 34618 | 0, // dsub2_then_hsub |
| 34619 | 0, // dsub2_then_ssub |
| 34620 | 0, // qsub1_then_bsub |
| 34621 | 0, // qsub1_then_dsub |
| 34622 | 0, // qsub1_then_hsub |
| 34623 | 0, // qsub1_then_ssub |
| 34624 | 0, // qsub3_then_bsub |
| 34625 | 0, // qsub3_then_dsub |
| 34626 | 0, // qsub3_then_hsub |
| 34627 | 0, // qsub3_then_ssub |
| 34628 | 0, // qsub2_then_bsub |
| 34629 | 0, // qsub2_then_dsub |
| 34630 | 0, // qsub2_then_hsub |
| 34631 | 0, // qsub2_then_ssub |
| 34632 | 0, // x8sub_7_then_sub_32 |
| 34633 | 0, // x8sub_6_then_sub_32 |
| 34634 | 0, // x8sub_5_then_sub_32 |
| 34635 | 0, // x8sub_4_then_sub_32 |
| 34636 | 0, // x8sub_3_then_sub_32 |
| 34637 | 0, // x8sub_2_then_sub_32 |
| 34638 | 0, // x8sub_1_then_sub_32 |
| 34639 | 0, // subo64_then_sub_32 |
| 34640 | 173, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34641 | 173, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34642 | 173, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34643 | 173, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34644 | 173, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34645 | 173, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34646 | 173, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34647 | 173, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34648 | 173, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34649 | 173, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34650 | 173, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34651 | 173, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34652 | 173, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34653 | 173, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34654 | 173, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34655 | 173, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34656 | 173, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34657 | 173, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34658 | 0, // dsub0_dsub1 |
| 34659 | 0, // dsub0_dsub1_dsub2 |
| 34660 | 0, // dsub1_dsub2 |
| 34661 | 0, // dsub1_dsub2_dsub3 |
| 34662 | 0, // dsub2_dsub3 |
| 34663 | 0, // dsub_qsub1_then_dsub |
| 34664 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34665 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 34666 | 0, // qsub0_qsub1 |
| 34667 | 0, // qsub0_qsub1_qsub2 |
| 34668 | 0, // qsub1_qsub2 |
| 34669 | 0, // qsub1_qsub2_qsub3 |
| 34670 | 0, // qsub2_qsub3 |
| 34671 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 34672 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34673 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 34674 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34675 | 0, // x8sub_0_x8sub_1 |
| 34676 | 0, // x8sub_2_x8sub_3 |
| 34677 | 0, // x8sub_4_x8sub_5 |
| 34678 | 0, // x8sub_6_x8sub_7 |
| 34679 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34680 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34681 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34682 | 0, // sub_32_subo64_then_sub_32 |
| 34683 | 173, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34684 | 173, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34685 | 173, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34686 | 173, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34687 | 173, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34688 | 173, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34689 | 173, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34690 | 173, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34691 | 173, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34692 | 173, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34693 | 173, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34694 | 173, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34695 | 173, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34696 | 173, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34697 | 173, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34698 | 173, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34699 | 173, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 34700 | }, |
| 34701 | { // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34702 | 174, // bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34703 | 174, // dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34704 | 0, // dsub0 |
| 34705 | 0, // dsub1 |
| 34706 | 0, // dsub2 |
| 34707 | 0, // dsub3 |
| 34708 | 174, // hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34709 | 0, // qhisub |
| 34710 | 0, // qsub |
| 34711 | 0, // qsub0 |
| 34712 | 0, // qsub1 |
| 34713 | 0, // qsub2 |
| 34714 | 0, // qsub3 |
| 34715 | 174, // ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34716 | 0, // sub_32 |
| 34717 | 0, // sube32 |
| 34718 | 0, // sube64 |
| 34719 | 0, // subo32 |
| 34720 | 0, // subo64 |
| 34721 | 0, // x8sub_0 |
| 34722 | 0, // x8sub_1 |
| 34723 | 0, // x8sub_2 |
| 34724 | 0, // x8sub_3 |
| 34725 | 0, // x8sub_4 |
| 34726 | 0, // x8sub_5 |
| 34727 | 0, // x8sub_6 |
| 34728 | 0, // x8sub_7 |
| 34729 | 174, // zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34730 | 174, // zsub0 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34731 | 174, // zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34732 | 174, // zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34733 | 174, // zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34734 | 174, // zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34735 | 0, // dsub1_then_bsub |
| 34736 | 0, // dsub1_then_hsub |
| 34737 | 0, // dsub1_then_ssub |
| 34738 | 0, // dsub3_then_bsub |
| 34739 | 0, // dsub3_then_hsub |
| 34740 | 0, // dsub3_then_ssub |
| 34741 | 0, // dsub2_then_bsub |
| 34742 | 0, // dsub2_then_hsub |
| 34743 | 0, // dsub2_then_ssub |
| 34744 | 0, // qsub1_then_bsub |
| 34745 | 0, // qsub1_then_dsub |
| 34746 | 0, // qsub1_then_hsub |
| 34747 | 0, // qsub1_then_ssub |
| 34748 | 0, // qsub3_then_bsub |
| 34749 | 0, // qsub3_then_dsub |
| 34750 | 0, // qsub3_then_hsub |
| 34751 | 0, // qsub3_then_ssub |
| 34752 | 0, // qsub2_then_bsub |
| 34753 | 0, // qsub2_then_dsub |
| 34754 | 0, // qsub2_then_hsub |
| 34755 | 0, // qsub2_then_ssub |
| 34756 | 0, // x8sub_7_then_sub_32 |
| 34757 | 0, // x8sub_6_then_sub_32 |
| 34758 | 0, // x8sub_5_then_sub_32 |
| 34759 | 0, // x8sub_4_then_sub_32 |
| 34760 | 0, // x8sub_3_then_sub_32 |
| 34761 | 0, // x8sub_2_then_sub_32 |
| 34762 | 0, // x8sub_1_then_sub_32 |
| 34763 | 0, // subo64_then_sub_32 |
| 34764 | 174, // zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34765 | 174, // zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34766 | 174, // zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34767 | 174, // zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34768 | 174, // zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34769 | 174, // zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34770 | 174, // zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34771 | 174, // zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34772 | 174, // zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34773 | 174, // zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34774 | 174, // zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34775 | 174, // zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34776 | 174, // zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34777 | 174, // zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34778 | 174, // zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34779 | 174, // zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34780 | 174, // zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34781 | 174, // zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34782 | 0, // dsub0_dsub1 |
| 34783 | 0, // dsub0_dsub1_dsub2 |
| 34784 | 0, // dsub1_dsub2 |
| 34785 | 0, // dsub1_dsub2_dsub3 |
| 34786 | 0, // dsub2_dsub3 |
| 34787 | 0, // dsub_qsub1_then_dsub |
| 34788 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34789 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 34790 | 0, // qsub0_qsub1 |
| 34791 | 0, // qsub0_qsub1_qsub2 |
| 34792 | 0, // qsub1_qsub2 |
| 34793 | 0, // qsub1_qsub2_qsub3 |
| 34794 | 0, // qsub2_qsub3 |
| 34795 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 34796 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 34797 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 34798 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34799 | 0, // x8sub_0_x8sub_1 |
| 34800 | 0, // x8sub_2_x8sub_3 |
| 34801 | 0, // x8sub_4_x8sub_5 |
| 34802 | 0, // x8sub_6_x8sub_7 |
| 34803 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34804 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34805 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34806 | 0, // sub_32_subo64_then_sub_32 |
| 34807 | 174, // dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34808 | 174, // zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34809 | 174, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34810 | 174, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34811 | 174, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34812 | 174, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34813 | 174, // zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34814 | 174, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34815 | 174, // zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34816 | 174, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34817 | 174, // zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34818 | 174, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34819 | 174, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34820 | 174, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34821 | 174, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34822 | 174, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34823 | 174, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34824 | }, |
| 34825 | { // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34826 | 175, // bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34827 | 175, // dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34828 | 0, // dsub0 |
| 34829 | 0, // dsub1 |
| 34830 | 0, // dsub2 |
| 34831 | 0, // dsub3 |
| 34832 | 175, // hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34833 | 0, // qhisub |
| 34834 | 0, // qsub |
| 34835 | 175, // qsub0 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34836 | 175, // qsub1 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34837 | 175, // qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34838 | 175, // qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34839 | 175, // ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34840 | 0, // sub_32 |
| 34841 | 0, // sube32 |
| 34842 | 0, // sube64 |
| 34843 | 0, // subo32 |
| 34844 | 0, // subo64 |
| 34845 | 0, // x8sub_0 |
| 34846 | 0, // x8sub_1 |
| 34847 | 0, // x8sub_2 |
| 34848 | 0, // x8sub_3 |
| 34849 | 0, // x8sub_4 |
| 34850 | 0, // x8sub_5 |
| 34851 | 0, // x8sub_6 |
| 34852 | 0, // x8sub_7 |
| 34853 | 0, // zsub |
| 34854 | 0, // zsub0 |
| 34855 | 0, // zsub1 |
| 34856 | 0, // zsub2 |
| 34857 | 0, // zsub3 |
| 34858 | 0, // zsub_hi |
| 34859 | 0, // dsub1_then_bsub |
| 34860 | 0, // dsub1_then_hsub |
| 34861 | 0, // dsub1_then_ssub |
| 34862 | 0, // dsub3_then_bsub |
| 34863 | 0, // dsub3_then_hsub |
| 34864 | 0, // dsub3_then_ssub |
| 34865 | 0, // dsub2_then_bsub |
| 34866 | 0, // dsub2_then_hsub |
| 34867 | 0, // dsub2_then_ssub |
| 34868 | 175, // qsub1_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34869 | 175, // qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34870 | 175, // qsub1_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34871 | 175, // qsub1_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34872 | 175, // qsub3_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34873 | 175, // qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34874 | 175, // qsub3_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34875 | 175, // qsub3_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34876 | 175, // qsub2_then_bsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34877 | 175, // qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34878 | 175, // qsub2_then_hsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34879 | 175, // qsub2_then_ssub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34880 | 0, // x8sub_7_then_sub_32 |
| 34881 | 0, // x8sub_6_then_sub_32 |
| 34882 | 0, // x8sub_5_then_sub_32 |
| 34883 | 0, // x8sub_4_then_sub_32 |
| 34884 | 0, // x8sub_3_then_sub_32 |
| 34885 | 0, // x8sub_2_then_sub_32 |
| 34886 | 0, // x8sub_1_then_sub_32 |
| 34887 | 0, // subo64_then_sub_32 |
| 34888 | 0, // zsub1_then_bsub |
| 34889 | 0, // zsub1_then_dsub |
| 34890 | 0, // zsub1_then_hsub |
| 34891 | 0, // zsub1_then_ssub |
| 34892 | 0, // zsub1_then_zsub |
| 34893 | 0, // zsub1_then_zsub_hi |
| 34894 | 0, // zsub3_then_bsub |
| 34895 | 0, // zsub3_then_dsub |
| 34896 | 0, // zsub3_then_hsub |
| 34897 | 0, // zsub3_then_ssub |
| 34898 | 0, // zsub3_then_zsub |
| 34899 | 0, // zsub3_then_zsub_hi |
| 34900 | 0, // zsub2_then_bsub |
| 34901 | 0, // zsub2_then_dsub |
| 34902 | 0, // zsub2_then_hsub |
| 34903 | 0, // zsub2_then_ssub |
| 34904 | 0, // zsub2_then_zsub |
| 34905 | 0, // zsub2_then_zsub_hi |
| 34906 | 0, // dsub0_dsub1 |
| 34907 | 0, // dsub0_dsub1_dsub2 |
| 34908 | 0, // dsub1_dsub2 |
| 34909 | 0, // dsub1_dsub2_dsub3 |
| 34910 | 0, // dsub2_dsub3 |
| 34911 | 175, // dsub_qsub1_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34912 | 175, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34913 | 175, // dsub_qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34914 | 175, // qsub0_qsub1 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34915 | 175, // qsub0_qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34916 | 175, // qsub1_qsub2 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34917 | 175, // qsub1_qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34918 | 175, // qsub2_qsub3 -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34919 | 175, // qsub1_then_dsub_qsub2_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34920 | 175, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34921 | 175, // qsub2_then_dsub_qsub3_then_dsub -> QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 34922 | 0, // sub_32_x8sub_1_then_sub_32 |
| 34923 | 0, // x8sub_0_x8sub_1 |
| 34924 | 0, // x8sub_2_x8sub_3 |
| 34925 | 0, // x8sub_4_x8sub_5 |
| 34926 | 0, // x8sub_6_x8sub_7 |
| 34927 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 34928 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 34929 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 34930 | 0, // sub_32_subo64_then_sub_32 |
| 34931 | 0, // dsub_zsub1_then_dsub |
| 34932 | 0, // zsub_zsub1_then_zsub |
| 34933 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 34934 | 0, // dsub_zsub1_then_dsub_zsub2_then_dsub |
| 34935 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 34936 | 0, // zsub_zsub1_then_zsub_zsub2_then_zsub |
| 34937 | 0, // zsub0_zsub1 |
| 34938 | 0, // zsub0_zsub1_zsub2 |
| 34939 | 0, // zsub1_zsub2 |
| 34940 | 0, // zsub1_zsub2_zsub3 |
| 34941 | 0, // zsub2_zsub3 |
| 34942 | 0, // zsub1_then_dsub_zsub2_then_dsub |
| 34943 | 0, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub |
| 34944 | 0, // zsub1_then_zsub_zsub2_then_zsub |
| 34945 | 0, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub |
| 34946 | 0, // zsub2_then_dsub_zsub3_then_dsub |
| 34947 | 0, // zsub2_then_zsub_zsub3_then_zsub |
| 34948 | }, |
| 34949 | { // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34950 | 176, // bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34951 | 176, // dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34952 | 0, // dsub0 |
| 34953 | 0, // dsub1 |
| 34954 | 0, // dsub2 |
| 34955 | 0, // dsub3 |
| 34956 | 176, // hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34957 | 0, // qhisub |
| 34958 | 0, // qsub |
| 34959 | 0, // qsub0 |
| 34960 | 0, // qsub1 |
| 34961 | 0, // qsub2 |
| 34962 | 0, // qsub3 |
| 34963 | 176, // ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34964 | 0, // sub_32 |
| 34965 | 0, // sube32 |
| 34966 | 0, // sube64 |
| 34967 | 0, // subo32 |
| 34968 | 0, // subo64 |
| 34969 | 0, // x8sub_0 |
| 34970 | 0, // x8sub_1 |
| 34971 | 0, // x8sub_2 |
| 34972 | 0, // x8sub_3 |
| 34973 | 0, // x8sub_4 |
| 34974 | 0, // x8sub_5 |
| 34975 | 0, // x8sub_6 |
| 34976 | 0, // x8sub_7 |
| 34977 | 176, // zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34978 | 176, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34979 | 176, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34980 | 176, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34981 | 176, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34982 | 176, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 34983 | 0, // dsub1_then_bsub |
| 34984 | 0, // dsub1_then_hsub |
| 34985 | 0, // dsub1_then_ssub |
| 34986 | 0, // dsub3_then_bsub |
| 34987 | 0, // dsub3_then_hsub |
| 34988 | 0, // dsub3_then_ssub |
| 34989 | 0, // dsub2_then_bsub |
| 34990 | 0, // dsub2_then_hsub |
| 34991 | 0, // dsub2_then_ssub |
| 34992 | 0, // qsub1_then_bsub |
| 34993 | 0, // qsub1_then_dsub |
| 34994 | 0, // qsub1_then_hsub |
| 34995 | 0, // qsub1_then_ssub |
| 34996 | 0, // qsub3_then_bsub |
| 34997 | 0, // qsub3_then_dsub |
| 34998 | 0, // qsub3_then_hsub |
| 34999 | 0, // qsub3_then_ssub |
| 35000 | 0, // qsub2_then_bsub |
| 35001 | 0, // qsub2_then_dsub |
| 35002 | 0, // qsub2_then_hsub |
| 35003 | 0, // qsub2_then_ssub |
| 35004 | 0, // x8sub_7_then_sub_32 |
| 35005 | 0, // x8sub_6_then_sub_32 |
| 35006 | 0, // x8sub_5_then_sub_32 |
| 35007 | 0, // x8sub_4_then_sub_32 |
| 35008 | 0, // x8sub_3_then_sub_32 |
| 35009 | 0, // x8sub_2_then_sub_32 |
| 35010 | 0, // x8sub_1_then_sub_32 |
| 35011 | 0, // subo64_then_sub_32 |
| 35012 | 176, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35013 | 176, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35014 | 176, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35015 | 176, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35016 | 176, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35017 | 176, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35018 | 176, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35019 | 176, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35020 | 176, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35021 | 176, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35022 | 176, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35023 | 176, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35024 | 176, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35025 | 176, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35026 | 176, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35027 | 176, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35028 | 176, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35029 | 176, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35030 | 0, // dsub0_dsub1 |
| 35031 | 0, // dsub0_dsub1_dsub2 |
| 35032 | 0, // dsub1_dsub2 |
| 35033 | 0, // dsub1_dsub2_dsub3 |
| 35034 | 0, // dsub2_dsub3 |
| 35035 | 0, // dsub_qsub1_then_dsub |
| 35036 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35037 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35038 | 0, // qsub0_qsub1 |
| 35039 | 0, // qsub0_qsub1_qsub2 |
| 35040 | 0, // qsub1_qsub2 |
| 35041 | 0, // qsub1_qsub2_qsub3 |
| 35042 | 0, // qsub2_qsub3 |
| 35043 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35044 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35045 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35046 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35047 | 0, // x8sub_0_x8sub_1 |
| 35048 | 0, // x8sub_2_x8sub_3 |
| 35049 | 0, // x8sub_4_x8sub_5 |
| 35050 | 0, // x8sub_6_x8sub_7 |
| 35051 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35052 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35053 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35054 | 0, // sub_32_subo64_then_sub_32 |
| 35055 | 176, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35056 | 176, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35057 | 176, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35058 | 176, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35059 | 176, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35060 | 176, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35061 | 176, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35062 | 176, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35063 | 176, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35064 | 176, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35065 | 176, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35066 | 176, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35067 | 176, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35068 | 176, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35069 | 176, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35070 | 176, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35071 | 176, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 35072 | }, |
| 35073 | { // ZPR4_with_zsub0_in_ZPR_3b |
| 35074 | 177, // bsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35075 | 177, // dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35076 | 0, // dsub0 |
| 35077 | 0, // dsub1 |
| 35078 | 0, // dsub2 |
| 35079 | 0, // dsub3 |
| 35080 | 177, // hsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35081 | 0, // qhisub |
| 35082 | 0, // qsub |
| 35083 | 0, // qsub0 |
| 35084 | 0, // qsub1 |
| 35085 | 0, // qsub2 |
| 35086 | 0, // qsub3 |
| 35087 | 177, // ssub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35088 | 0, // sub_32 |
| 35089 | 0, // sube32 |
| 35090 | 0, // sube64 |
| 35091 | 0, // subo32 |
| 35092 | 0, // subo64 |
| 35093 | 0, // x8sub_0 |
| 35094 | 0, // x8sub_1 |
| 35095 | 0, // x8sub_2 |
| 35096 | 0, // x8sub_3 |
| 35097 | 0, // x8sub_4 |
| 35098 | 0, // x8sub_5 |
| 35099 | 0, // x8sub_6 |
| 35100 | 0, // x8sub_7 |
| 35101 | 177, // zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35102 | 177, // zsub0 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35103 | 177, // zsub1 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35104 | 177, // zsub2 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35105 | 177, // zsub3 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35106 | 177, // zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b |
| 35107 | 0, // dsub1_then_bsub |
| 35108 | 0, // dsub1_then_hsub |
| 35109 | 0, // dsub1_then_ssub |
| 35110 | 0, // dsub3_then_bsub |
| 35111 | 0, // dsub3_then_hsub |
| 35112 | 0, // dsub3_then_ssub |
| 35113 | 0, // dsub2_then_bsub |
| 35114 | 0, // dsub2_then_hsub |
| 35115 | 0, // dsub2_then_ssub |
| 35116 | 0, // qsub1_then_bsub |
| 35117 | 0, // qsub1_then_dsub |
| 35118 | 0, // qsub1_then_hsub |
| 35119 | 0, // qsub1_then_ssub |
| 35120 | 0, // qsub3_then_bsub |
| 35121 | 0, // qsub3_then_dsub |
| 35122 | 0, // qsub3_then_hsub |
| 35123 | 0, // qsub3_then_ssub |
| 35124 | 0, // qsub2_then_bsub |
| 35125 | 0, // qsub2_then_dsub |
| 35126 | 0, // qsub2_then_hsub |
| 35127 | 0, // qsub2_then_ssub |
| 35128 | 0, // x8sub_7_then_sub_32 |
| 35129 | 0, // x8sub_6_then_sub_32 |
| 35130 | 0, // x8sub_5_then_sub_32 |
| 35131 | 0, // x8sub_4_then_sub_32 |
| 35132 | 0, // x8sub_3_then_sub_32 |
| 35133 | 0, // x8sub_2_then_sub_32 |
| 35134 | 0, // x8sub_1_then_sub_32 |
| 35135 | 0, // subo64_then_sub_32 |
| 35136 | 177, // zsub1_then_bsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35137 | 177, // zsub1_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35138 | 177, // zsub1_then_hsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35139 | 177, // zsub1_then_ssub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35140 | 177, // zsub1_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35141 | 177, // zsub1_then_zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b |
| 35142 | 177, // zsub3_then_bsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35143 | 177, // zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35144 | 177, // zsub3_then_hsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35145 | 177, // zsub3_then_ssub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35146 | 177, // zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35147 | 177, // zsub3_then_zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b |
| 35148 | 177, // zsub2_then_bsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35149 | 177, // zsub2_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35150 | 177, // zsub2_then_hsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35151 | 177, // zsub2_then_ssub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35152 | 177, // zsub2_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35153 | 177, // zsub2_then_zsub_hi -> ZPR4_with_zsub0_in_ZPR_3b |
| 35154 | 0, // dsub0_dsub1 |
| 35155 | 0, // dsub0_dsub1_dsub2 |
| 35156 | 0, // dsub1_dsub2 |
| 35157 | 0, // dsub1_dsub2_dsub3 |
| 35158 | 0, // dsub2_dsub3 |
| 35159 | 0, // dsub_qsub1_then_dsub |
| 35160 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35161 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35162 | 0, // qsub0_qsub1 |
| 35163 | 0, // qsub0_qsub1_qsub2 |
| 35164 | 0, // qsub1_qsub2 |
| 35165 | 0, // qsub1_qsub2_qsub3 |
| 35166 | 0, // qsub2_qsub3 |
| 35167 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35168 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35169 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35170 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35171 | 0, // x8sub_0_x8sub_1 |
| 35172 | 0, // x8sub_2_x8sub_3 |
| 35173 | 0, // x8sub_4_x8sub_5 |
| 35174 | 0, // x8sub_6_x8sub_7 |
| 35175 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35176 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35177 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35178 | 0, // sub_32_subo64_then_sub_32 |
| 35179 | 177, // dsub_zsub1_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35180 | 177, // zsub_zsub1_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35181 | 177, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35182 | 177, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35183 | 177, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35184 | 177, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35185 | 177, // zsub0_zsub1 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35186 | 177, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35187 | 177, // zsub1_zsub2 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35188 | 177, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35189 | 177, // zsub2_zsub3 -> ZPR4_with_zsub0_in_ZPR_3b |
| 35190 | 177, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35191 | 177, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35192 | 177, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35193 | 177, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35194 | 177, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35195 | 177, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub0_in_ZPR_3b |
| 35196 | }, |
| 35197 | { // ZPR4_with_zsub1_in_ZPR_3b |
| 35198 | 178, // bsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35199 | 178, // dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35200 | 0, // dsub0 |
| 35201 | 0, // dsub1 |
| 35202 | 0, // dsub2 |
| 35203 | 0, // dsub3 |
| 35204 | 178, // hsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35205 | 0, // qhisub |
| 35206 | 0, // qsub |
| 35207 | 0, // qsub0 |
| 35208 | 0, // qsub1 |
| 35209 | 0, // qsub2 |
| 35210 | 0, // qsub3 |
| 35211 | 178, // ssub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35212 | 0, // sub_32 |
| 35213 | 0, // sube32 |
| 35214 | 0, // sube64 |
| 35215 | 0, // subo32 |
| 35216 | 0, // subo64 |
| 35217 | 0, // x8sub_0 |
| 35218 | 0, // x8sub_1 |
| 35219 | 0, // x8sub_2 |
| 35220 | 0, // x8sub_3 |
| 35221 | 0, // x8sub_4 |
| 35222 | 0, // x8sub_5 |
| 35223 | 0, // x8sub_6 |
| 35224 | 0, // x8sub_7 |
| 35225 | 178, // zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35226 | 178, // zsub0 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35227 | 178, // zsub1 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35228 | 178, // zsub2 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35229 | 178, // zsub3 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35230 | 178, // zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b |
| 35231 | 0, // dsub1_then_bsub |
| 35232 | 0, // dsub1_then_hsub |
| 35233 | 0, // dsub1_then_ssub |
| 35234 | 0, // dsub3_then_bsub |
| 35235 | 0, // dsub3_then_hsub |
| 35236 | 0, // dsub3_then_ssub |
| 35237 | 0, // dsub2_then_bsub |
| 35238 | 0, // dsub2_then_hsub |
| 35239 | 0, // dsub2_then_ssub |
| 35240 | 0, // qsub1_then_bsub |
| 35241 | 0, // qsub1_then_dsub |
| 35242 | 0, // qsub1_then_hsub |
| 35243 | 0, // qsub1_then_ssub |
| 35244 | 0, // qsub3_then_bsub |
| 35245 | 0, // qsub3_then_dsub |
| 35246 | 0, // qsub3_then_hsub |
| 35247 | 0, // qsub3_then_ssub |
| 35248 | 0, // qsub2_then_bsub |
| 35249 | 0, // qsub2_then_dsub |
| 35250 | 0, // qsub2_then_hsub |
| 35251 | 0, // qsub2_then_ssub |
| 35252 | 0, // x8sub_7_then_sub_32 |
| 35253 | 0, // x8sub_6_then_sub_32 |
| 35254 | 0, // x8sub_5_then_sub_32 |
| 35255 | 0, // x8sub_4_then_sub_32 |
| 35256 | 0, // x8sub_3_then_sub_32 |
| 35257 | 0, // x8sub_2_then_sub_32 |
| 35258 | 0, // x8sub_1_then_sub_32 |
| 35259 | 0, // subo64_then_sub_32 |
| 35260 | 178, // zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35261 | 178, // zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35262 | 178, // zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35263 | 178, // zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35264 | 178, // zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35265 | 178, // zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b |
| 35266 | 178, // zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35267 | 178, // zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35268 | 178, // zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35269 | 178, // zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35270 | 178, // zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35271 | 178, // zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b |
| 35272 | 178, // zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35273 | 178, // zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35274 | 178, // zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35275 | 178, // zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35276 | 178, // zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35277 | 178, // zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b |
| 35278 | 0, // dsub0_dsub1 |
| 35279 | 0, // dsub0_dsub1_dsub2 |
| 35280 | 0, // dsub1_dsub2 |
| 35281 | 0, // dsub1_dsub2_dsub3 |
| 35282 | 0, // dsub2_dsub3 |
| 35283 | 0, // dsub_qsub1_then_dsub |
| 35284 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35285 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35286 | 0, // qsub0_qsub1 |
| 35287 | 0, // qsub0_qsub1_qsub2 |
| 35288 | 0, // qsub1_qsub2 |
| 35289 | 0, // qsub1_qsub2_qsub3 |
| 35290 | 0, // qsub2_qsub3 |
| 35291 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35292 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35293 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35294 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35295 | 0, // x8sub_0_x8sub_1 |
| 35296 | 0, // x8sub_2_x8sub_3 |
| 35297 | 0, // x8sub_4_x8sub_5 |
| 35298 | 0, // x8sub_6_x8sub_7 |
| 35299 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35300 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35301 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35302 | 0, // sub_32_subo64_then_sub_32 |
| 35303 | 178, // dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35304 | 178, // zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35305 | 178, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35306 | 178, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35307 | 178, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35308 | 178, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35309 | 178, // zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35310 | 178, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35311 | 178, // zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35312 | 178, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35313 | 178, // zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b |
| 35314 | 178, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35315 | 178, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35316 | 178, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35317 | 178, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35318 | 178, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35319 | 178, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b |
| 35320 | }, |
| 35321 | { // ZPR4_with_zsub2_in_ZPR_3b |
| 35322 | 179, // bsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35323 | 179, // dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35324 | 0, // dsub0 |
| 35325 | 0, // dsub1 |
| 35326 | 0, // dsub2 |
| 35327 | 0, // dsub3 |
| 35328 | 179, // hsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35329 | 0, // qhisub |
| 35330 | 0, // qsub |
| 35331 | 0, // qsub0 |
| 35332 | 0, // qsub1 |
| 35333 | 0, // qsub2 |
| 35334 | 0, // qsub3 |
| 35335 | 179, // ssub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35336 | 0, // sub_32 |
| 35337 | 0, // sube32 |
| 35338 | 0, // sube64 |
| 35339 | 0, // subo32 |
| 35340 | 0, // subo64 |
| 35341 | 0, // x8sub_0 |
| 35342 | 0, // x8sub_1 |
| 35343 | 0, // x8sub_2 |
| 35344 | 0, // x8sub_3 |
| 35345 | 0, // x8sub_4 |
| 35346 | 0, // x8sub_5 |
| 35347 | 0, // x8sub_6 |
| 35348 | 0, // x8sub_7 |
| 35349 | 179, // zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35350 | 179, // zsub0 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35351 | 179, // zsub1 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35352 | 179, // zsub2 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35353 | 179, // zsub3 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35354 | 179, // zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b |
| 35355 | 0, // dsub1_then_bsub |
| 35356 | 0, // dsub1_then_hsub |
| 35357 | 0, // dsub1_then_ssub |
| 35358 | 0, // dsub3_then_bsub |
| 35359 | 0, // dsub3_then_hsub |
| 35360 | 0, // dsub3_then_ssub |
| 35361 | 0, // dsub2_then_bsub |
| 35362 | 0, // dsub2_then_hsub |
| 35363 | 0, // dsub2_then_ssub |
| 35364 | 0, // qsub1_then_bsub |
| 35365 | 0, // qsub1_then_dsub |
| 35366 | 0, // qsub1_then_hsub |
| 35367 | 0, // qsub1_then_ssub |
| 35368 | 0, // qsub3_then_bsub |
| 35369 | 0, // qsub3_then_dsub |
| 35370 | 0, // qsub3_then_hsub |
| 35371 | 0, // qsub3_then_ssub |
| 35372 | 0, // qsub2_then_bsub |
| 35373 | 0, // qsub2_then_dsub |
| 35374 | 0, // qsub2_then_hsub |
| 35375 | 0, // qsub2_then_ssub |
| 35376 | 0, // x8sub_7_then_sub_32 |
| 35377 | 0, // x8sub_6_then_sub_32 |
| 35378 | 0, // x8sub_5_then_sub_32 |
| 35379 | 0, // x8sub_4_then_sub_32 |
| 35380 | 0, // x8sub_3_then_sub_32 |
| 35381 | 0, // x8sub_2_then_sub_32 |
| 35382 | 0, // x8sub_1_then_sub_32 |
| 35383 | 0, // subo64_then_sub_32 |
| 35384 | 179, // zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35385 | 179, // zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35386 | 179, // zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35387 | 179, // zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35388 | 179, // zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35389 | 179, // zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b |
| 35390 | 179, // zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35391 | 179, // zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35392 | 179, // zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35393 | 179, // zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35394 | 179, // zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35395 | 179, // zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b |
| 35396 | 179, // zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35397 | 179, // zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35398 | 179, // zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35399 | 179, // zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35400 | 179, // zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35401 | 179, // zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b |
| 35402 | 0, // dsub0_dsub1 |
| 35403 | 0, // dsub0_dsub1_dsub2 |
| 35404 | 0, // dsub1_dsub2 |
| 35405 | 0, // dsub1_dsub2_dsub3 |
| 35406 | 0, // dsub2_dsub3 |
| 35407 | 0, // dsub_qsub1_then_dsub |
| 35408 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35409 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35410 | 0, // qsub0_qsub1 |
| 35411 | 0, // qsub0_qsub1_qsub2 |
| 35412 | 0, // qsub1_qsub2 |
| 35413 | 0, // qsub1_qsub2_qsub3 |
| 35414 | 0, // qsub2_qsub3 |
| 35415 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35416 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35417 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35418 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35419 | 0, // x8sub_0_x8sub_1 |
| 35420 | 0, // x8sub_2_x8sub_3 |
| 35421 | 0, // x8sub_4_x8sub_5 |
| 35422 | 0, // x8sub_6_x8sub_7 |
| 35423 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35424 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35425 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35426 | 0, // sub_32_subo64_then_sub_32 |
| 35427 | 179, // dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35428 | 179, // zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35429 | 179, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35430 | 179, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35431 | 179, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35432 | 179, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35433 | 179, // zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35434 | 179, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35435 | 179, // zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35436 | 179, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35437 | 179, // zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b |
| 35438 | 179, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35439 | 179, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35440 | 179, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35441 | 179, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35442 | 179, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35443 | 179, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b |
| 35444 | }, |
| 35445 | { // ZPR4_with_zsub3_in_ZPR_3b |
| 35446 | 180, // bsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35447 | 180, // dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35448 | 0, // dsub0 |
| 35449 | 0, // dsub1 |
| 35450 | 0, // dsub2 |
| 35451 | 0, // dsub3 |
| 35452 | 180, // hsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35453 | 0, // qhisub |
| 35454 | 0, // qsub |
| 35455 | 0, // qsub0 |
| 35456 | 0, // qsub1 |
| 35457 | 0, // qsub2 |
| 35458 | 0, // qsub3 |
| 35459 | 180, // ssub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35460 | 0, // sub_32 |
| 35461 | 0, // sube32 |
| 35462 | 0, // sube64 |
| 35463 | 0, // subo32 |
| 35464 | 0, // subo64 |
| 35465 | 0, // x8sub_0 |
| 35466 | 0, // x8sub_1 |
| 35467 | 0, // x8sub_2 |
| 35468 | 0, // x8sub_3 |
| 35469 | 0, // x8sub_4 |
| 35470 | 0, // x8sub_5 |
| 35471 | 0, // x8sub_6 |
| 35472 | 0, // x8sub_7 |
| 35473 | 180, // zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35474 | 180, // zsub0 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35475 | 180, // zsub1 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35476 | 180, // zsub2 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35477 | 180, // zsub3 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35478 | 180, // zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b |
| 35479 | 0, // dsub1_then_bsub |
| 35480 | 0, // dsub1_then_hsub |
| 35481 | 0, // dsub1_then_ssub |
| 35482 | 0, // dsub3_then_bsub |
| 35483 | 0, // dsub3_then_hsub |
| 35484 | 0, // dsub3_then_ssub |
| 35485 | 0, // dsub2_then_bsub |
| 35486 | 0, // dsub2_then_hsub |
| 35487 | 0, // dsub2_then_ssub |
| 35488 | 0, // qsub1_then_bsub |
| 35489 | 0, // qsub1_then_dsub |
| 35490 | 0, // qsub1_then_hsub |
| 35491 | 0, // qsub1_then_ssub |
| 35492 | 0, // qsub3_then_bsub |
| 35493 | 0, // qsub3_then_dsub |
| 35494 | 0, // qsub3_then_hsub |
| 35495 | 0, // qsub3_then_ssub |
| 35496 | 0, // qsub2_then_bsub |
| 35497 | 0, // qsub2_then_dsub |
| 35498 | 0, // qsub2_then_hsub |
| 35499 | 0, // qsub2_then_ssub |
| 35500 | 0, // x8sub_7_then_sub_32 |
| 35501 | 0, // x8sub_6_then_sub_32 |
| 35502 | 0, // x8sub_5_then_sub_32 |
| 35503 | 0, // x8sub_4_then_sub_32 |
| 35504 | 0, // x8sub_3_then_sub_32 |
| 35505 | 0, // x8sub_2_then_sub_32 |
| 35506 | 0, // x8sub_1_then_sub_32 |
| 35507 | 0, // subo64_then_sub_32 |
| 35508 | 180, // zsub1_then_bsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35509 | 180, // zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35510 | 180, // zsub1_then_hsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35511 | 180, // zsub1_then_ssub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35512 | 180, // zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35513 | 180, // zsub1_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b |
| 35514 | 180, // zsub3_then_bsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35515 | 180, // zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35516 | 180, // zsub3_then_hsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35517 | 180, // zsub3_then_ssub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35518 | 180, // zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35519 | 180, // zsub3_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b |
| 35520 | 180, // zsub2_then_bsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35521 | 180, // zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35522 | 180, // zsub2_then_hsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35523 | 180, // zsub2_then_ssub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35524 | 180, // zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35525 | 180, // zsub2_then_zsub_hi -> ZPR4_with_zsub3_in_ZPR_3b |
| 35526 | 0, // dsub0_dsub1 |
| 35527 | 0, // dsub0_dsub1_dsub2 |
| 35528 | 0, // dsub1_dsub2 |
| 35529 | 0, // dsub1_dsub2_dsub3 |
| 35530 | 0, // dsub2_dsub3 |
| 35531 | 0, // dsub_qsub1_then_dsub |
| 35532 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35533 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35534 | 0, // qsub0_qsub1 |
| 35535 | 0, // qsub0_qsub1_qsub2 |
| 35536 | 0, // qsub1_qsub2 |
| 35537 | 0, // qsub1_qsub2_qsub3 |
| 35538 | 0, // qsub2_qsub3 |
| 35539 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35540 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35541 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35542 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35543 | 0, // x8sub_0_x8sub_1 |
| 35544 | 0, // x8sub_2_x8sub_3 |
| 35545 | 0, // x8sub_4_x8sub_5 |
| 35546 | 0, // x8sub_6_x8sub_7 |
| 35547 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35548 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35549 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35550 | 0, // sub_32_subo64_then_sub_32 |
| 35551 | 180, // dsub_zsub1_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35552 | 180, // zsub_zsub1_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35553 | 180, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35554 | 180, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35555 | 180, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35556 | 180, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35557 | 180, // zsub0_zsub1 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35558 | 180, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35559 | 180, // zsub1_zsub2 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35560 | 180, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35561 | 180, // zsub2_zsub3 -> ZPR4_with_zsub3_in_ZPR_3b |
| 35562 | 180, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35563 | 180, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35564 | 180, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35565 | 180, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35566 | 180, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35567 | 180, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub3_in_ZPR_3b |
| 35568 | }, |
| 35569 | { // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35570 | 181, // bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35571 | 181, // dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35572 | 0, // dsub0 |
| 35573 | 0, // dsub1 |
| 35574 | 0, // dsub2 |
| 35575 | 0, // dsub3 |
| 35576 | 181, // hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35577 | 0, // qhisub |
| 35578 | 0, // qsub |
| 35579 | 0, // qsub0 |
| 35580 | 0, // qsub1 |
| 35581 | 0, // qsub2 |
| 35582 | 0, // qsub3 |
| 35583 | 181, // ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35584 | 0, // sub_32 |
| 35585 | 0, // sube32 |
| 35586 | 0, // sube64 |
| 35587 | 0, // subo32 |
| 35588 | 0, // subo64 |
| 35589 | 0, // x8sub_0 |
| 35590 | 0, // x8sub_1 |
| 35591 | 0, // x8sub_2 |
| 35592 | 0, // x8sub_3 |
| 35593 | 0, // x8sub_4 |
| 35594 | 0, // x8sub_5 |
| 35595 | 0, // x8sub_6 |
| 35596 | 0, // x8sub_7 |
| 35597 | 181, // zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35598 | 181, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35599 | 181, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35600 | 181, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35601 | 181, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35602 | 181, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35603 | 0, // dsub1_then_bsub |
| 35604 | 0, // dsub1_then_hsub |
| 35605 | 0, // dsub1_then_ssub |
| 35606 | 0, // dsub3_then_bsub |
| 35607 | 0, // dsub3_then_hsub |
| 35608 | 0, // dsub3_then_ssub |
| 35609 | 0, // dsub2_then_bsub |
| 35610 | 0, // dsub2_then_hsub |
| 35611 | 0, // dsub2_then_ssub |
| 35612 | 0, // qsub1_then_bsub |
| 35613 | 0, // qsub1_then_dsub |
| 35614 | 0, // qsub1_then_hsub |
| 35615 | 0, // qsub1_then_ssub |
| 35616 | 0, // qsub3_then_bsub |
| 35617 | 0, // qsub3_then_dsub |
| 35618 | 0, // qsub3_then_hsub |
| 35619 | 0, // qsub3_then_ssub |
| 35620 | 0, // qsub2_then_bsub |
| 35621 | 0, // qsub2_then_dsub |
| 35622 | 0, // qsub2_then_hsub |
| 35623 | 0, // qsub2_then_ssub |
| 35624 | 0, // x8sub_7_then_sub_32 |
| 35625 | 0, // x8sub_6_then_sub_32 |
| 35626 | 0, // x8sub_5_then_sub_32 |
| 35627 | 0, // x8sub_4_then_sub_32 |
| 35628 | 0, // x8sub_3_then_sub_32 |
| 35629 | 0, // x8sub_2_then_sub_32 |
| 35630 | 0, // x8sub_1_then_sub_32 |
| 35631 | 0, // subo64_then_sub_32 |
| 35632 | 181, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35633 | 181, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35634 | 181, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35635 | 181, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35636 | 181, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35637 | 181, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35638 | 181, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35639 | 181, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35640 | 181, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35641 | 181, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35642 | 181, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35643 | 181, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35644 | 181, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35645 | 181, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35646 | 181, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35647 | 181, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35648 | 181, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35649 | 181, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35650 | 0, // dsub0_dsub1 |
| 35651 | 0, // dsub0_dsub1_dsub2 |
| 35652 | 0, // dsub1_dsub2 |
| 35653 | 0, // dsub1_dsub2_dsub3 |
| 35654 | 0, // dsub2_dsub3 |
| 35655 | 0, // dsub_qsub1_then_dsub |
| 35656 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35657 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35658 | 0, // qsub0_qsub1 |
| 35659 | 0, // qsub0_qsub1_qsub2 |
| 35660 | 0, // qsub1_qsub2 |
| 35661 | 0, // qsub1_qsub2_qsub3 |
| 35662 | 0, // qsub2_qsub3 |
| 35663 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35664 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35665 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35666 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35667 | 0, // x8sub_0_x8sub_1 |
| 35668 | 0, // x8sub_2_x8sub_3 |
| 35669 | 0, // x8sub_4_x8sub_5 |
| 35670 | 0, // x8sub_6_x8sub_7 |
| 35671 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35672 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35673 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35674 | 0, // sub_32_subo64_then_sub_32 |
| 35675 | 181, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35676 | 181, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35677 | 181, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35678 | 181, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35679 | 181, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35680 | 181, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35681 | 181, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35682 | 181, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35683 | 181, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35684 | 181, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35685 | 181, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35686 | 181, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35687 | 181, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35688 | 181, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35689 | 181, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35690 | 181, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35691 | 181, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 35692 | }, |
| 35693 | { // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35694 | 182, // bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35695 | 182, // dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35696 | 0, // dsub0 |
| 35697 | 0, // dsub1 |
| 35698 | 0, // dsub2 |
| 35699 | 0, // dsub3 |
| 35700 | 182, // hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35701 | 0, // qhisub |
| 35702 | 0, // qsub |
| 35703 | 0, // qsub0 |
| 35704 | 0, // qsub1 |
| 35705 | 0, // qsub2 |
| 35706 | 0, // qsub3 |
| 35707 | 182, // ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35708 | 0, // sub_32 |
| 35709 | 0, // sube32 |
| 35710 | 0, // sube64 |
| 35711 | 0, // subo32 |
| 35712 | 0, // subo64 |
| 35713 | 0, // x8sub_0 |
| 35714 | 0, // x8sub_1 |
| 35715 | 0, // x8sub_2 |
| 35716 | 0, // x8sub_3 |
| 35717 | 0, // x8sub_4 |
| 35718 | 0, // x8sub_5 |
| 35719 | 0, // x8sub_6 |
| 35720 | 0, // x8sub_7 |
| 35721 | 182, // zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35722 | 182, // zsub0 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35723 | 182, // zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35724 | 182, // zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35725 | 182, // zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35726 | 182, // zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35727 | 0, // dsub1_then_bsub |
| 35728 | 0, // dsub1_then_hsub |
| 35729 | 0, // dsub1_then_ssub |
| 35730 | 0, // dsub3_then_bsub |
| 35731 | 0, // dsub3_then_hsub |
| 35732 | 0, // dsub3_then_ssub |
| 35733 | 0, // dsub2_then_bsub |
| 35734 | 0, // dsub2_then_hsub |
| 35735 | 0, // dsub2_then_ssub |
| 35736 | 0, // qsub1_then_bsub |
| 35737 | 0, // qsub1_then_dsub |
| 35738 | 0, // qsub1_then_hsub |
| 35739 | 0, // qsub1_then_ssub |
| 35740 | 0, // qsub3_then_bsub |
| 35741 | 0, // qsub3_then_dsub |
| 35742 | 0, // qsub3_then_hsub |
| 35743 | 0, // qsub3_then_ssub |
| 35744 | 0, // qsub2_then_bsub |
| 35745 | 0, // qsub2_then_dsub |
| 35746 | 0, // qsub2_then_hsub |
| 35747 | 0, // qsub2_then_ssub |
| 35748 | 0, // x8sub_7_then_sub_32 |
| 35749 | 0, // x8sub_6_then_sub_32 |
| 35750 | 0, // x8sub_5_then_sub_32 |
| 35751 | 0, // x8sub_4_then_sub_32 |
| 35752 | 0, // x8sub_3_then_sub_32 |
| 35753 | 0, // x8sub_2_then_sub_32 |
| 35754 | 0, // x8sub_1_then_sub_32 |
| 35755 | 0, // subo64_then_sub_32 |
| 35756 | 182, // zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35757 | 182, // zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35758 | 182, // zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35759 | 182, // zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35760 | 182, // zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35761 | 182, // zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35762 | 182, // zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35763 | 182, // zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35764 | 182, // zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35765 | 182, // zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35766 | 182, // zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35767 | 182, // zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35768 | 182, // zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35769 | 182, // zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35770 | 182, // zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35771 | 182, // zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35772 | 182, // zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35773 | 182, // zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35774 | 0, // dsub0_dsub1 |
| 35775 | 0, // dsub0_dsub1_dsub2 |
| 35776 | 0, // dsub1_dsub2 |
| 35777 | 0, // dsub1_dsub2_dsub3 |
| 35778 | 0, // dsub2_dsub3 |
| 35779 | 0, // dsub_qsub1_then_dsub |
| 35780 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35781 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35782 | 0, // qsub0_qsub1 |
| 35783 | 0, // qsub0_qsub1_qsub2 |
| 35784 | 0, // qsub1_qsub2 |
| 35785 | 0, // qsub1_qsub2_qsub3 |
| 35786 | 0, // qsub2_qsub3 |
| 35787 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35788 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35789 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35790 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35791 | 0, // x8sub_0_x8sub_1 |
| 35792 | 0, // x8sub_2_x8sub_3 |
| 35793 | 0, // x8sub_4_x8sub_5 |
| 35794 | 0, // x8sub_6_x8sub_7 |
| 35795 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35796 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35797 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35798 | 0, // sub_32_subo64_then_sub_32 |
| 35799 | 182, // dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35800 | 182, // zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35801 | 182, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35802 | 182, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35803 | 182, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35804 | 182, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35805 | 182, // zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35806 | 182, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35807 | 182, // zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35808 | 182, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35809 | 182, // zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35810 | 182, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35811 | 182, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35812 | 182, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35813 | 182, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35814 | 182, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35815 | 182, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35816 | }, |
| 35817 | { // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35818 | 183, // bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35819 | 183, // dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35820 | 0, // dsub0 |
| 35821 | 0, // dsub1 |
| 35822 | 0, // dsub2 |
| 35823 | 0, // dsub3 |
| 35824 | 183, // hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35825 | 0, // qhisub |
| 35826 | 0, // qsub |
| 35827 | 0, // qsub0 |
| 35828 | 0, // qsub1 |
| 35829 | 0, // qsub2 |
| 35830 | 0, // qsub3 |
| 35831 | 183, // ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35832 | 0, // sub_32 |
| 35833 | 0, // sube32 |
| 35834 | 0, // sube64 |
| 35835 | 0, // subo32 |
| 35836 | 0, // subo64 |
| 35837 | 0, // x8sub_0 |
| 35838 | 0, // x8sub_1 |
| 35839 | 0, // x8sub_2 |
| 35840 | 0, // x8sub_3 |
| 35841 | 0, // x8sub_4 |
| 35842 | 0, // x8sub_5 |
| 35843 | 0, // x8sub_6 |
| 35844 | 0, // x8sub_7 |
| 35845 | 183, // zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35846 | 183, // zsub0 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35847 | 183, // zsub1 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35848 | 183, // zsub2 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35849 | 183, // zsub3 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35850 | 183, // zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35851 | 0, // dsub1_then_bsub |
| 35852 | 0, // dsub1_then_hsub |
| 35853 | 0, // dsub1_then_ssub |
| 35854 | 0, // dsub3_then_bsub |
| 35855 | 0, // dsub3_then_hsub |
| 35856 | 0, // dsub3_then_ssub |
| 35857 | 0, // dsub2_then_bsub |
| 35858 | 0, // dsub2_then_hsub |
| 35859 | 0, // dsub2_then_ssub |
| 35860 | 0, // qsub1_then_bsub |
| 35861 | 0, // qsub1_then_dsub |
| 35862 | 0, // qsub1_then_hsub |
| 35863 | 0, // qsub1_then_ssub |
| 35864 | 0, // qsub3_then_bsub |
| 35865 | 0, // qsub3_then_dsub |
| 35866 | 0, // qsub3_then_hsub |
| 35867 | 0, // qsub3_then_ssub |
| 35868 | 0, // qsub2_then_bsub |
| 35869 | 0, // qsub2_then_dsub |
| 35870 | 0, // qsub2_then_hsub |
| 35871 | 0, // qsub2_then_ssub |
| 35872 | 0, // x8sub_7_then_sub_32 |
| 35873 | 0, // x8sub_6_then_sub_32 |
| 35874 | 0, // x8sub_5_then_sub_32 |
| 35875 | 0, // x8sub_4_then_sub_32 |
| 35876 | 0, // x8sub_3_then_sub_32 |
| 35877 | 0, // x8sub_2_then_sub_32 |
| 35878 | 0, // x8sub_1_then_sub_32 |
| 35879 | 0, // subo64_then_sub_32 |
| 35880 | 183, // zsub1_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35881 | 183, // zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35882 | 183, // zsub1_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35883 | 183, // zsub1_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35884 | 183, // zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35885 | 183, // zsub1_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35886 | 183, // zsub3_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35887 | 183, // zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35888 | 183, // zsub3_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35889 | 183, // zsub3_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35890 | 183, // zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35891 | 183, // zsub3_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35892 | 183, // zsub2_then_bsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35893 | 183, // zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35894 | 183, // zsub2_then_hsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35895 | 183, // zsub2_then_ssub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35896 | 183, // zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35897 | 183, // zsub2_then_zsub_hi -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35898 | 0, // dsub0_dsub1 |
| 35899 | 0, // dsub0_dsub1_dsub2 |
| 35900 | 0, // dsub1_dsub2 |
| 35901 | 0, // dsub1_dsub2_dsub3 |
| 35902 | 0, // dsub2_dsub3 |
| 35903 | 0, // dsub_qsub1_then_dsub |
| 35904 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35905 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 35906 | 0, // qsub0_qsub1 |
| 35907 | 0, // qsub0_qsub1_qsub2 |
| 35908 | 0, // qsub1_qsub2 |
| 35909 | 0, // qsub1_qsub2_qsub3 |
| 35910 | 0, // qsub2_qsub3 |
| 35911 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 35912 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 35913 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 35914 | 0, // sub_32_x8sub_1_then_sub_32 |
| 35915 | 0, // x8sub_0_x8sub_1 |
| 35916 | 0, // x8sub_2_x8sub_3 |
| 35917 | 0, // x8sub_4_x8sub_5 |
| 35918 | 0, // x8sub_6_x8sub_7 |
| 35919 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 35920 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 35921 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 35922 | 0, // sub_32_subo64_then_sub_32 |
| 35923 | 183, // dsub_zsub1_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35924 | 183, // zsub_zsub1_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35925 | 183, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35926 | 183, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35927 | 183, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35928 | 183, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35929 | 183, // zsub0_zsub1 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35930 | 183, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35931 | 183, // zsub1_zsub2 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35932 | 183, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35933 | 183, // zsub2_zsub3 -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35934 | 183, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35935 | 183, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35936 | 183, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35937 | 183, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35938 | 183, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35939 | 183, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 35940 | }, |
| 35941 | { // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35942 | 184, // bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35943 | 184, // dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35944 | 0, // dsub0 |
| 35945 | 0, // dsub1 |
| 35946 | 0, // dsub2 |
| 35947 | 0, // dsub3 |
| 35948 | 184, // hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35949 | 0, // qhisub |
| 35950 | 0, // qsub |
| 35951 | 0, // qsub0 |
| 35952 | 0, // qsub1 |
| 35953 | 0, // qsub2 |
| 35954 | 0, // qsub3 |
| 35955 | 184, // ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35956 | 0, // sub_32 |
| 35957 | 0, // sube32 |
| 35958 | 0, // sube64 |
| 35959 | 0, // subo32 |
| 35960 | 0, // subo64 |
| 35961 | 0, // x8sub_0 |
| 35962 | 0, // x8sub_1 |
| 35963 | 0, // x8sub_2 |
| 35964 | 0, // x8sub_3 |
| 35965 | 0, // x8sub_4 |
| 35966 | 0, // x8sub_5 |
| 35967 | 0, // x8sub_6 |
| 35968 | 0, // x8sub_7 |
| 35969 | 184, // zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35970 | 184, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35971 | 184, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35972 | 184, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35973 | 184, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35974 | 184, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 35975 | 0, // dsub1_then_bsub |
| 35976 | 0, // dsub1_then_hsub |
| 35977 | 0, // dsub1_then_ssub |
| 35978 | 0, // dsub3_then_bsub |
| 35979 | 0, // dsub3_then_hsub |
| 35980 | 0, // dsub3_then_ssub |
| 35981 | 0, // dsub2_then_bsub |
| 35982 | 0, // dsub2_then_hsub |
| 35983 | 0, // dsub2_then_ssub |
| 35984 | 0, // qsub1_then_bsub |
| 35985 | 0, // qsub1_then_dsub |
| 35986 | 0, // qsub1_then_hsub |
| 35987 | 0, // qsub1_then_ssub |
| 35988 | 0, // qsub3_then_bsub |
| 35989 | 0, // qsub3_then_dsub |
| 35990 | 0, // qsub3_then_hsub |
| 35991 | 0, // qsub3_then_ssub |
| 35992 | 0, // qsub2_then_bsub |
| 35993 | 0, // qsub2_then_dsub |
| 35994 | 0, // qsub2_then_hsub |
| 35995 | 0, // qsub2_then_ssub |
| 35996 | 0, // x8sub_7_then_sub_32 |
| 35997 | 0, // x8sub_6_then_sub_32 |
| 35998 | 0, // x8sub_5_then_sub_32 |
| 35999 | 0, // x8sub_4_then_sub_32 |
| 36000 | 0, // x8sub_3_then_sub_32 |
| 36001 | 0, // x8sub_2_then_sub_32 |
| 36002 | 0, // x8sub_1_then_sub_32 |
| 36003 | 0, // subo64_then_sub_32 |
| 36004 | 184, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36005 | 184, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36006 | 184, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36007 | 184, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36008 | 184, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36009 | 184, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36010 | 184, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36011 | 184, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36012 | 184, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36013 | 184, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36014 | 184, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36015 | 184, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36016 | 184, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36017 | 184, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36018 | 184, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36019 | 184, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36020 | 184, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36021 | 184, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36022 | 0, // dsub0_dsub1 |
| 36023 | 0, // dsub0_dsub1_dsub2 |
| 36024 | 0, // dsub1_dsub2 |
| 36025 | 0, // dsub1_dsub2_dsub3 |
| 36026 | 0, // dsub2_dsub3 |
| 36027 | 0, // dsub_qsub1_then_dsub |
| 36028 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 36029 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 36030 | 0, // qsub0_qsub1 |
| 36031 | 0, // qsub0_qsub1_qsub2 |
| 36032 | 0, // qsub1_qsub2 |
| 36033 | 0, // qsub1_qsub2_qsub3 |
| 36034 | 0, // qsub2_qsub3 |
| 36035 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 36036 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 36037 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 36038 | 0, // sub_32_x8sub_1_then_sub_32 |
| 36039 | 0, // x8sub_0_x8sub_1 |
| 36040 | 0, // x8sub_2_x8sub_3 |
| 36041 | 0, // x8sub_4_x8sub_5 |
| 36042 | 0, // x8sub_6_x8sub_7 |
| 36043 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 36044 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 36045 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 36046 | 0, // sub_32_subo64_then_sub_32 |
| 36047 | 184, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36048 | 184, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36049 | 184, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36050 | 184, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36051 | 184, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36052 | 184, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36053 | 184, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36054 | 184, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36055 | 184, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36056 | 184, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36057 | 184, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36058 | 184, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36059 | 184, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36060 | 184, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36061 | 184, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36062 | 184, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36063 | 184, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36064 | }, |
| 36065 | { // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36066 | 185, // bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36067 | 185, // dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36068 | 0, // dsub0 |
| 36069 | 0, // dsub1 |
| 36070 | 0, // dsub2 |
| 36071 | 0, // dsub3 |
| 36072 | 185, // hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36073 | 0, // qhisub |
| 36074 | 0, // qsub |
| 36075 | 0, // qsub0 |
| 36076 | 0, // qsub1 |
| 36077 | 0, // qsub2 |
| 36078 | 0, // qsub3 |
| 36079 | 185, // ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36080 | 0, // sub_32 |
| 36081 | 0, // sube32 |
| 36082 | 0, // sube64 |
| 36083 | 0, // subo32 |
| 36084 | 0, // subo64 |
| 36085 | 0, // x8sub_0 |
| 36086 | 0, // x8sub_1 |
| 36087 | 0, // x8sub_2 |
| 36088 | 0, // x8sub_3 |
| 36089 | 0, // x8sub_4 |
| 36090 | 0, // x8sub_5 |
| 36091 | 0, // x8sub_6 |
| 36092 | 0, // x8sub_7 |
| 36093 | 185, // zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36094 | 185, // zsub0 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36095 | 185, // zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36096 | 185, // zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36097 | 185, // zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36098 | 185, // zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36099 | 0, // dsub1_then_bsub |
| 36100 | 0, // dsub1_then_hsub |
| 36101 | 0, // dsub1_then_ssub |
| 36102 | 0, // dsub3_then_bsub |
| 36103 | 0, // dsub3_then_hsub |
| 36104 | 0, // dsub3_then_ssub |
| 36105 | 0, // dsub2_then_bsub |
| 36106 | 0, // dsub2_then_hsub |
| 36107 | 0, // dsub2_then_ssub |
| 36108 | 0, // qsub1_then_bsub |
| 36109 | 0, // qsub1_then_dsub |
| 36110 | 0, // qsub1_then_hsub |
| 36111 | 0, // qsub1_then_ssub |
| 36112 | 0, // qsub3_then_bsub |
| 36113 | 0, // qsub3_then_dsub |
| 36114 | 0, // qsub3_then_hsub |
| 36115 | 0, // qsub3_then_ssub |
| 36116 | 0, // qsub2_then_bsub |
| 36117 | 0, // qsub2_then_dsub |
| 36118 | 0, // qsub2_then_hsub |
| 36119 | 0, // qsub2_then_ssub |
| 36120 | 0, // x8sub_7_then_sub_32 |
| 36121 | 0, // x8sub_6_then_sub_32 |
| 36122 | 0, // x8sub_5_then_sub_32 |
| 36123 | 0, // x8sub_4_then_sub_32 |
| 36124 | 0, // x8sub_3_then_sub_32 |
| 36125 | 0, // x8sub_2_then_sub_32 |
| 36126 | 0, // x8sub_1_then_sub_32 |
| 36127 | 0, // subo64_then_sub_32 |
| 36128 | 185, // zsub1_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36129 | 185, // zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36130 | 185, // zsub1_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36131 | 185, // zsub1_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36132 | 185, // zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36133 | 185, // zsub1_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36134 | 185, // zsub3_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36135 | 185, // zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36136 | 185, // zsub3_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36137 | 185, // zsub3_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36138 | 185, // zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36139 | 185, // zsub3_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36140 | 185, // zsub2_then_bsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36141 | 185, // zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36142 | 185, // zsub2_then_hsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36143 | 185, // zsub2_then_ssub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36144 | 185, // zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36145 | 185, // zsub2_then_zsub_hi -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36146 | 0, // dsub0_dsub1 |
| 36147 | 0, // dsub0_dsub1_dsub2 |
| 36148 | 0, // dsub1_dsub2 |
| 36149 | 0, // dsub1_dsub2_dsub3 |
| 36150 | 0, // dsub2_dsub3 |
| 36151 | 0, // dsub_qsub1_then_dsub |
| 36152 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 36153 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 36154 | 0, // qsub0_qsub1 |
| 36155 | 0, // qsub0_qsub1_qsub2 |
| 36156 | 0, // qsub1_qsub2 |
| 36157 | 0, // qsub1_qsub2_qsub3 |
| 36158 | 0, // qsub2_qsub3 |
| 36159 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 36160 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 36161 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 36162 | 0, // sub_32_x8sub_1_then_sub_32 |
| 36163 | 0, // x8sub_0_x8sub_1 |
| 36164 | 0, // x8sub_2_x8sub_3 |
| 36165 | 0, // x8sub_4_x8sub_5 |
| 36166 | 0, // x8sub_6_x8sub_7 |
| 36167 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 36168 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 36169 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 36170 | 0, // sub_32_subo64_then_sub_32 |
| 36171 | 185, // dsub_zsub1_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36172 | 185, // zsub_zsub1_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36173 | 185, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36174 | 185, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36175 | 185, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36176 | 185, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36177 | 185, // zsub0_zsub1 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36178 | 185, // zsub0_zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36179 | 185, // zsub1_zsub2 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36180 | 185, // zsub1_zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36181 | 185, // zsub2_zsub3 -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36182 | 185, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36183 | 185, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36184 | 185, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36185 | 185, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36186 | 185, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36187 | 185, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36188 | }, |
| 36189 | { // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36190 | 186, // bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36191 | 186, // dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36192 | 0, // dsub0 |
| 36193 | 0, // dsub1 |
| 36194 | 0, // dsub2 |
| 36195 | 0, // dsub3 |
| 36196 | 186, // hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36197 | 0, // qhisub |
| 36198 | 0, // qsub |
| 36199 | 0, // qsub0 |
| 36200 | 0, // qsub1 |
| 36201 | 0, // qsub2 |
| 36202 | 0, // qsub3 |
| 36203 | 186, // ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36204 | 0, // sub_32 |
| 36205 | 0, // sube32 |
| 36206 | 0, // sube64 |
| 36207 | 0, // subo32 |
| 36208 | 0, // subo64 |
| 36209 | 0, // x8sub_0 |
| 36210 | 0, // x8sub_1 |
| 36211 | 0, // x8sub_2 |
| 36212 | 0, // x8sub_3 |
| 36213 | 0, // x8sub_4 |
| 36214 | 0, // x8sub_5 |
| 36215 | 0, // x8sub_6 |
| 36216 | 0, // x8sub_7 |
| 36217 | 186, // zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36218 | 186, // zsub0 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36219 | 186, // zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36220 | 186, // zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36221 | 186, // zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36222 | 186, // zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36223 | 0, // dsub1_then_bsub |
| 36224 | 0, // dsub1_then_hsub |
| 36225 | 0, // dsub1_then_ssub |
| 36226 | 0, // dsub3_then_bsub |
| 36227 | 0, // dsub3_then_hsub |
| 36228 | 0, // dsub3_then_ssub |
| 36229 | 0, // dsub2_then_bsub |
| 36230 | 0, // dsub2_then_hsub |
| 36231 | 0, // dsub2_then_ssub |
| 36232 | 0, // qsub1_then_bsub |
| 36233 | 0, // qsub1_then_dsub |
| 36234 | 0, // qsub1_then_hsub |
| 36235 | 0, // qsub1_then_ssub |
| 36236 | 0, // qsub3_then_bsub |
| 36237 | 0, // qsub3_then_dsub |
| 36238 | 0, // qsub3_then_hsub |
| 36239 | 0, // qsub3_then_ssub |
| 36240 | 0, // qsub2_then_bsub |
| 36241 | 0, // qsub2_then_dsub |
| 36242 | 0, // qsub2_then_hsub |
| 36243 | 0, // qsub2_then_ssub |
| 36244 | 0, // x8sub_7_then_sub_32 |
| 36245 | 0, // x8sub_6_then_sub_32 |
| 36246 | 0, // x8sub_5_then_sub_32 |
| 36247 | 0, // x8sub_4_then_sub_32 |
| 36248 | 0, // x8sub_3_then_sub_32 |
| 36249 | 0, // x8sub_2_then_sub_32 |
| 36250 | 0, // x8sub_1_then_sub_32 |
| 36251 | 0, // subo64_then_sub_32 |
| 36252 | 186, // zsub1_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36253 | 186, // zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36254 | 186, // zsub1_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36255 | 186, // zsub1_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36256 | 186, // zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36257 | 186, // zsub1_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36258 | 186, // zsub3_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36259 | 186, // zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36260 | 186, // zsub3_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36261 | 186, // zsub3_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36262 | 186, // zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36263 | 186, // zsub3_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36264 | 186, // zsub2_then_bsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36265 | 186, // zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36266 | 186, // zsub2_then_hsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36267 | 186, // zsub2_then_ssub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36268 | 186, // zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36269 | 186, // zsub2_then_zsub_hi -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36270 | 0, // dsub0_dsub1 |
| 36271 | 0, // dsub0_dsub1_dsub2 |
| 36272 | 0, // dsub1_dsub2 |
| 36273 | 0, // dsub1_dsub2_dsub3 |
| 36274 | 0, // dsub2_dsub3 |
| 36275 | 0, // dsub_qsub1_then_dsub |
| 36276 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 36277 | 0, // dsub_qsub1_then_dsub_qsub2_then_dsub |
| 36278 | 0, // qsub0_qsub1 |
| 36279 | 0, // qsub0_qsub1_qsub2 |
| 36280 | 0, // qsub1_qsub2 |
| 36281 | 0, // qsub1_qsub2_qsub3 |
| 36282 | 0, // qsub2_qsub3 |
| 36283 | 0, // qsub1_then_dsub_qsub2_then_dsub |
| 36284 | 0, // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub |
| 36285 | 0, // qsub2_then_dsub_qsub3_then_dsub |
| 36286 | 0, // sub_32_x8sub_1_then_sub_32 |
| 36287 | 0, // x8sub_0_x8sub_1 |
| 36288 | 0, // x8sub_2_x8sub_3 |
| 36289 | 0, // x8sub_4_x8sub_5 |
| 36290 | 0, // x8sub_6_x8sub_7 |
| 36291 | 0, // x8sub_6_then_sub_32_x8sub_7_then_sub_32 |
| 36292 | 0, // x8sub_4_then_sub_32_x8sub_5_then_sub_32 |
| 36293 | 0, // x8sub_2_then_sub_32_x8sub_3_then_sub_32 |
| 36294 | 0, // sub_32_subo64_then_sub_32 |
| 36295 | 186, // dsub_zsub1_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36296 | 186, // zsub_zsub1_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36297 | 186, // dsub_zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36298 | 186, // dsub_zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36299 | 186, // zsub_zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36300 | 186, // zsub_zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36301 | 186, // zsub0_zsub1 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36302 | 186, // zsub0_zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36303 | 186, // zsub1_zsub2 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36304 | 186, // zsub1_zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36305 | 186, // zsub2_zsub3 -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36306 | 186, // zsub1_then_dsub_zsub2_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36307 | 186, // zsub1_then_dsub_zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36308 | 186, // zsub1_then_zsub_zsub2_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36309 | 186, // zsub1_then_zsub_zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36310 | 186, // zsub2_then_dsub_zsub3_then_dsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36311 | 186, // zsub2_then_zsub_zsub3_then_zsub -> ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36312 | }, |
| 36313 | }; |
| 36314 | assert(RC && "Missing regclass" ); |
| 36315 | if (!Idx) return RC; |
| 36316 | --Idx; |
| 36317 | assert(Idx < 122 && "Bad subreg" ); |
| 36318 | unsigned TV = Table[RC->getID()][Idx]; |
| 36319 | return TV ? getRegClass(TV - 1) : nullptr; |
| 36320 | } |
| 36321 | |
| 36322 | /// Get the weight in units of pressure for this register class. |
| 36323 | const RegClassWeight &AArch64GenRegisterInfo:: |
| 36324 | getRegClassWeight(const TargetRegisterClass *RC) const { |
| 36325 | static const RegClassWeight RCWeightTable[] = { |
| 36326 | {1, 32}, // FPR8 |
| 36327 | {1, 32}, // FPR16 |
| 36328 | {1, 16}, // FPR16_lo |
| 36329 | {1, 16}, // PPR |
| 36330 | {1, 8}, // PPR_3b |
| 36331 | {1, 33}, // GPR32all |
| 36332 | {1, 32}, // FPR32 |
| 36333 | {1, 32}, // GPR32 |
| 36334 | {1, 32}, // GPR32sp |
| 36335 | {1, 31}, // GPR32common |
| 36336 | {1, 16}, // FPR32_with_hsub_in_FPR16_lo |
| 36337 | {1, 8}, // GPR32arg |
| 36338 | {0, 0}, // CCR |
| 36339 | {1, 1}, // GPR32sponly |
| 36340 | {2, 32}, // WSeqPairsClass |
| 36341 | {2, 30}, // WSeqPairsClass_with_subo32_in_GPR32common |
| 36342 | {2, 8}, // WSeqPairsClass_with_sube32_in_GPR32arg |
| 36343 | {1, 33}, // GPR64all |
| 36344 | {1, 32}, // FPR64 |
| 36345 | {1, 32}, // GPR64 |
| 36346 | {1, 32}, // GPR64sp |
| 36347 | {1, 31}, // GPR64common |
| 36348 | {1, 29}, // GPR64noip |
| 36349 | {1, 28}, // GPR64common_and_GPR64noip |
| 36350 | {1, 19}, // tcGPR64 |
| 36351 | {1, 17}, // GPR64noip_and_tcGPR64 |
| 36352 | {1, 16}, // FPR64_lo |
| 36353 | {8, 30}, // GPR64x8Class |
| 36354 | {8, 30}, // GPR64x8Class_with_x8sub_0_in_GPR64noip |
| 36355 | {8, 30}, // GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 36356 | {8, 30}, // GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36357 | {8, 30}, // GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36358 | {8, 30}, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 36359 | {8, 30}, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36360 | {8, 30}, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36361 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 36362 | {8, 30}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36363 | {8, 30}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36364 | {8, 30}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36365 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_GPR64noip_and_tcGPR64 |
| 36366 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 36367 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36368 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36369 | {8, 24}, // GPR64x8Class_with_x8sub_1_in_tcGPR64 |
| 36370 | {8, 30}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36371 | {8, 30}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36372 | {8, 30}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36373 | {8, 30}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36374 | {1, 8}, // GPR64arg |
| 36375 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip |
| 36376 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36377 | {8, 26}, // GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36378 | {8, 22}, // GPR64x8Class_with_x8sub_1_in_GPR64noip_and_tcGPR64 |
| 36379 | {8, 24}, // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36380 | {8, 24}, // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36381 | {8, 26}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36382 | {8, 26}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36383 | {8, 24}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_tcGPR64 |
| 36384 | {8, 26}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36385 | {8, 28}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36386 | {8, 22}, // GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36387 | {8, 26}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36388 | {8, 26}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36389 | {8, 24}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_4_in_GPR64noip |
| 36390 | {8, 24}, // GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36391 | {8, 20}, // GPR64x8Class_with_x8sub_3_in_GPR64noip_and_tcGPR64 |
| 36392 | {8, 26}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36393 | {8, 24}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36394 | {8, 26}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36395 | {8, 22}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_tcGPR64 |
| 36396 | {8, 22}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36397 | {8, 24}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_0_in_tcGPR64_and_GPR64x8Class_with_x8sub_0_in_GPR64noip_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36398 | {8, 24}, // GPR64x8Class_with_x8sub_4_in_GPR64noip_and_GPR64x8Class_with_x8sub_2_in_GPR64noip_and_GPR64x8Class_with_x8sub_1_in_tcGPR64_and_GPR64x8Class_with_x8sub_6_in_GPR64noip |
| 36399 | {8, 18}, // GPR64x8Class_with_x8sub_5_in_GPR64noip_and_tcGPR64 |
| 36400 | {8, 20}, // GPR64x8Class_with_x8sub_6_in_GPR64noip_and_tcGPR64 |
| 36401 | {8, 16}, // GPR64x8Class_with_x8sub_7_in_GPR64noip_and_tcGPR64 |
| 36402 | {8, 14}, // GPR64x8Class_with_sub_32_in_GPR32arg |
| 36403 | {8, 12}, // GPR64x8Class_with_x8sub_2_in_GPR64arg |
| 36404 | {8, 10}, // GPR64x8Class_with_x8sub_4_in_GPR64arg |
| 36405 | {1, 2}, // rtcGPR64 |
| 36406 | {1, 1}, // GPR64sponly |
| 36407 | {8, 8}, // GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 36408 | {8, 8}, // GPR64x8Class_with_x8sub_2_in_rtcGPR64 |
| 36409 | {8, 8}, // GPR64x8Class_with_x8sub_4_in_rtcGPR64 |
| 36410 | {8, 8}, // GPR64x8Class_with_x8sub_6_in_GPR64arg |
| 36411 | {8, 8}, // GPR64x8Class_with_x8sub_6_in_rtcGPR64 |
| 36412 | {2, 32}, // DD |
| 36413 | {2, 17}, // DD_with_dsub0_in_FPR64_lo |
| 36414 | {2, 17}, // DD_with_dsub1_in_FPR64_lo |
| 36415 | {2, 32}, // XSeqPairsClass |
| 36416 | {2, 16}, // DD_with_dsub0_in_FPR64_lo_and_DD_with_dsub1_in_FPR64_lo |
| 36417 | {2, 30}, // XSeqPairsClass_with_subo64_in_GPR64common |
| 36418 | {2, 30}, // XSeqPairsClass_with_subo64_in_GPR64noip |
| 36419 | {2, 28}, // XSeqPairsClass_with_sube64_in_GPR64noip |
| 36420 | {2, 20}, // XSeqPairsClass_with_sube64_in_tcGPR64 |
| 36421 | {2, 18}, // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64 |
| 36422 | {2, 18}, // XSeqPairsClass_with_subo64_in_tcGPR64 |
| 36423 | {2, 16}, // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64 |
| 36424 | {2, 8}, // XSeqPairsClass_with_sub_32_in_GPR32arg |
| 36425 | {2, 2}, // XSeqPairsClass_with_sube64_in_rtcGPR64 |
| 36426 | {1, 32}, // FPR128 |
| 36427 | {2, 64}, // ZPR |
| 36428 | {1, 16}, // FPR128_lo |
| 36429 | {2, 32}, // ZPR_4b |
| 36430 | {2, 16}, // ZPR_3b |
| 36431 | {3, 32}, // DDD |
| 36432 | {3, 18}, // DDD_with_dsub0_in_FPR64_lo |
| 36433 | {3, 18}, // DDD_with_dsub1_in_FPR64_lo |
| 36434 | {3, 18}, // DDD_with_dsub2_in_FPR64_lo |
| 36435 | {3, 17}, // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub1_in_FPR64_lo |
| 36436 | {3, 17}, // DDD_with_dsub1_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 36437 | {3, 16}, // DDD_with_dsub0_in_FPR64_lo_and_DDD_with_dsub2_in_FPR64_lo |
| 36438 | {4, 32}, // DDDD |
| 36439 | {4, 19}, // DDDD_with_dsub0_in_FPR64_lo |
| 36440 | {4, 19}, // DDDD_with_dsub1_in_FPR64_lo |
| 36441 | {4, 19}, // DDDD_with_dsub2_in_FPR64_lo |
| 36442 | {4, 19}, // DDDD_with_dsub3_in_FPR64_lo |
| 36443 | {4, 18}, // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub1_in_FPR64_lo |
| 36444 | {4, 18}, // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 36445 | {4, 18}, // DDDD_with_dsub2_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 36446 | {4, 17}, // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub2_in_FPR64_lo |
| 36447 | {4, 17}, // DDDD_with_dsub1_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 36448 | {4, 16}, // DDDD_with_dsub0_in_FPR64_lo_and_DDDD_with_dsub3_in_FPR64_lo |
| 36449 | {2, 32}, // QQ |
| 36450 | {4, 64}, // ZPR2 |
| 36451 | {2, 17}, // QQ_with_dsub_in_FPR64_lo |
| 36452 | {2, 17}, // QQ_with_qsub1_in_FPR128_lo |
| 36453 | {4, 34}, // ZPR2_with_dsub_in_FPR64_lo |
| 36454 | {4, 34}, // ZPR2_with_zsub1_in_ZPR_4b |
| 36455 | {2, 16}, // QQ_with_dsub_in_FPR64_lo_and_QQ_with_qsub1_in_FPR128_lo |
| 36456 | {4, 32}, // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_4b |
| 36457 | {4, 18}, // ZPR2_with_zsub0_in_ZPR_3b |
| 36458 | {4, 18}, // ZPR2_with_zsub1_in_ZPR_3b |
| 36459 | {4, 16}, // ZPR2_with_dsub_in_FPR64_lo_and_ZPR2_with_zsub1_in_ZPR_3b |
| 36460 | {3, 32}, // QQQ |
| 36461 | {6, 64}, // ZPR3 |
| 36462 | {3, 18}, // QQQ_with_dsub_in_FPR64_lo |
| 36463 | {3, 18}, // QQQ_with_qsub1_in_FPR128_lo |
| 36464 | {3, 18}, // QQQ_with_qsub2_in_FPR128_lo |
| 36465 | {6, 36}, // ZPR3_with_dsub_in_FPR64_lo |
| 36466 | {6, 36}, // ZPR3_with_zsub1_in_ZPR_4b |
| 36467 | {6, 36}, // ZPR3_with_zsub2_in_ZPR_4b |
| 36468 | {3, 17}, // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub1_in_FPR128_lo |
| 36469 | {3, 17}, // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 36470 | {6, 34}, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_4b |
| 36471 | {6, 34}, // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b |
| 36472 | {3, 16}, // QQQ_with_dsub_in_FPR64_lo_and_QQQ_with_qsub2_in_FPR128_lo |
| 36473 | {6, 32}, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_4b |
| 36474 | {6, 20}, // ZPR3_with_zsub0_in_ZPR_3b |
| 36475 | {6, 20}, // ZPR3_with_zsub1_in_ZPR_3b |
| 36476 | {6, 20}, // ZPR3_with_zsub2_in_ZPR_3b |
| 36477 | {6, 18}, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub1_in_ZPR_3b |
| 36478 | {6, 18}, // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b |
| 36479 | {6, 16}, // ZPR3_with_dsub_in_FPR64_lo_and_ZPR3_with_zsub2_in_ZPR_3b |
| 36480 | {4, 32}, // QQQQ |
| 36481 | {8, 64}, // ZPR4 |
| 36482 | {4, 19}, // QQQQ_with_dsub_in_FPR64_lo |
| 36483 | {4, 19}, // QQQQ_with_qsub1_in_FPR128_lo |
| 36484 | {4, 19}, // QQQQ_with_qsub2_in_FPR128_lo |
| 36485 | {4, 19}, // QQQQ_with_qsub3_in_FPR128_lo |
| 36486 | {8, 38}, // ZPR4_with_dsub_in_FPR64_lo |
| 36487 | {8, 38}, // ZPR4_with_zsub1_in_ZPR_4b |
| 36488 | {8, 38}, // ZPR4_with_zsub2_in_ZPR_4b |
| 36489 | {8, 38}, // ZPR4_with_zsub3_in_ZPR_4b |
| 36490 | {4, 18}, // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub1_in_FPR128_lo |
| 36491 | {4, 18}, // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 36492 | {4, 18}, // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 36493 | {8, 36}, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_4b |
| 36494 | {8, 36}, // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b |
| 36495 | {8, 36}, // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 36496 | {4, 17}, // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub2_in_FPR128_lo |
| 36497 | {4, 17}, // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 36498 | {8, 34}, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_4b |
| 36499 | {8, 34}, // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b |
| 36500 | {4, 16}, // QQQQ_with_dsub_in_FPR64_lo_and_QQQQ_with_qsub3_in_FPR128_lo |
| 36501 | {8, 32}, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_4b |
| 36502 | {8, 22}, // ZPR4_with_zsub0_in_ZPR_3b |
| 36503 | {8, 22}, // ZPR4_with_zsub1_in_ZPR_3b |
| 36504 | {8, 22}, // ZPR4_with_zsub2_in_ZPR_3b |
| 36505 | {8, 22}, // ZPR4_with_zsub3_in_ZPR_3b |
| 36506 | {8, 20}, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub1_in_ZPR_3b |
| 36507 | {8, 20}, // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36508 | {8, 20}, // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36509 | {8, 18}, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub2_in_ZPR_3b |
| 36510 | {8, 18}, // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36511 | {8, 16}, // ZPR4_with_dsub_in_FPR64_lo_and_ZPR4_with_zsub3_in_ZPR_3b |
| 36512 | }; |
| 36513 | return RCWeightTable[RC->getID()]; |
| 36514 | } |
| 36515 | |
| 36516 | /// Get the weight in units of pressure for this register unit. |
| 36517 | unsigned AArch64GenRegisterInfo:: |
| 36518 | getRegUnitWeight(unsigned RegUnit) const { |
| 36519 | assert(RegUnit < 116 && "invalid register unit" ); |
| 36520 | // All register units have unit weight. |
| 36521 | return 1; |
| 36522 | } |
| 36523 | |
| 36524 | |
| 36525 | // Get the number of dimensions of register pressure. |
| 36526 | unsigned AArch64GenRegisterInfo::getNumRegPressureSets() const { |
| 36527 | return 32; |
| 36528 | } |
| 36529 | |
| 36530 | // Get the name of this register unit pressure set. |
| 36531 | const char *AArch64GenRegisterInfo:: |
| 36532 | getRegPressureSetName(unsigned Idx) const { |
| 36533 | static const char *const PressureNameTable[] = { |
| 36534 | "GPR32sponly" , |
| 36535 | "rtcGPR64" , |
| 36536 | "PPR_3b" , |
| 36537 | "GPR64x8Class_with_x8sub_0_in_rtcGPR64" , |
| 36538 | "PPR" , |
| 36539 | "FPR16_lo" , |
| 36540 | "GPR64x8Class_with_x8sub_0_in_tcGPR64" , |
| 36541 | "ZPR_3b" , |
| 36542 | "FPR16_lo_with_ZPR_3b" , |
| 36543 | "DD_with_dsub1_in_FPR64_lo_with_ZPR_3b" , |
| 36544 | "DDD_with_dsub2_in_FPR64_lo_with_ZPR_3b" , |
| 36545 | "DDD_with_dsub2_in_FPR64_lo_with_ZPR4_with_zsub1_in_ZPR_3b" , |
| 36546 | "DDDD_with_dsub3_in_FPR64_lo_with_ZPR_3b" , |
| 36547 | "DDDD_with_dsub3_in_FPR64_lo_with_ZPR4_with_zsub1_in_ZPR_3b" , |
| 36548 | "DDDD_with_dsub3_in_FPR64_lo_with_ZPR4_with_zsub2_in_ZPR_3b" , |
| 36549 | "FPR16_lo_with_ZPR4_with_zsub1_in_ZPR_3b" , |
| 36550 | "FPR8" , |
| 36551 | "FPR16_lo_with_ZPR4_with_zsub2_in_ZPR_3b" , |
| 36552 | "GPR32" , |
| 36553 | "FPR16_lo_with_ZPR4_with_zsub3_in_ZPR_3b" , |
| 36554 | "ZPR4_with_zsub3_in_ZPR_4b" , |
| 36555 | "ZPR_4b" , |
| 36556 | "FPR8_with_ZPR_3b" , |
| 36557 | "FPR8_with_ZPR4_with_zsub1_in_ZPR_3b" , |
| 36558 | "FPR8_with_ZPR4_with_zsub2_in_ZPR_3b" , |
| 36559 | "FPR8_with_ZPR4_with_zsub3_in_ZPR_3b" , |
| 36560 | "ZPR4_with_zsub2_in_ZPR_4b" , |
| 36561 | "FPR8_with_ZPR_4b" , |
| 36562 | "FPR8_with_ZPR4_with_zsub1_in_ZPR_4b" , |
| 36563 | "FPR8_with_ZPR4_with_zsub2_in_ZPR_4b" , |
| 36564 | "FPR8_with_ZPR4_with_zsub3_in_ZPR_4b" , |
| 36565 | "ZPR" , |
| 36566 | }; |
| 36567 | return PressureNameTable[Idx]; |
| 36568 | } |
| 36569 | |
| 36570 | // Get the register unit pressure limit for this dimension. |
| 36571 | // This limit must be adjusted dynamically for reserved registers. |
| 36572 | unsigned AArch64GenRegisterInfo:: |
| 36573 | getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
| 36574 | static const uint8_t PressureLimitTable[] = { |
| 36575 | 1, // 0: GPR32sponly |
| 36576 | 2, // 1: rtcGPR64 |
| 36577 | 8, // 2: PPR_3b |
| 36578 | 14, // 3: GPR64x8Class_with_x8sub_0_in_rtcGPR64 |
| 36579 | 16, // 4: PPR |
| 36580 | 22, // 5: FPR16_lo |
| 36581 | 26, // 6: GPR64x8Class_with_x8sub_0_in_tcGPR64 |
| 36582 | 28, // 7: ZPR_3b |
| 36583 | 30, // 8: FPR16_lo_with_ZPR_3b |
| 36584 | 30, // 9: DD_with_dsub1_in_FPR64_lo_with_ZPR_3b |
| 36585 | 30, // 10: DDD_with_dsub2_in_FPR64_lo_with_ZPR_3b |
| 36586 | 30, // 11: DDD_with_dsub2_in_FPR64_lo_with_ZPR4_with_zsub1_in_ZPR_3b |
| 36587 | 30, // 12: DDDD_with_dsub3_in_FPR64_lo_with_ZPR_3b |
| 36588 | 30, // 13: DDDD_with_dsub3_in_FPR64_lo_with_ZPR4_with_zsub1_in_ZPR_3b |
| 36589 | 30, // 14: DDDD_with_dsub3_in_FPR64_lo_with_ZPR4_with_zsub2_in_ZPR_3b |
| 36590 | 31, // 15: FPR16_lo_with_ZPR4_with_zsub1_in_ZPR_3b |
| 36591 | 32, // 16: FPR8 |
| 36592 | 32, // 17: FPR16_lo_with_ZPR4_with_zsub2_in_ZPR_3b |
| 36593 | 33, // 18: GPR32 |
| 36594 | 33, // 19: FPR16_lo_with_ZPR4_with_zsub3_in_ZPR_3b |
| 36595 | 41, // 20: ZPR4_with_zsub3_in_ZPR_4b |
| 36596 | 41, // 21: ZPR_4b |
| 36597 | 43, // 22: FPR8_with_ZPR_3b |
| 36598 | 43, // 23: FPR8_with_ZPR4_with_zsub1_in_ZPR_3b |
| 36599 | 43, // 24: FPR8_with_ZPR4_with_zsub2_in_ZPR_3b |
| 36600 | 43, // 25: FPR8_with_ZPR4_with_zsub3_in_ZPR_3b |
| 36601 | 44, // 26: ZPR4_with_zsub2_in_ZPR_4b |
| 36602 | 51, // 27: FPR8_with_ZPR_4b |
| 36603 | 51, // 28: FPR8_with_ZPR4_with_zsub1_in_ZPR_4b |
| 36604 | 51, // 29: FPR8_with_ZPR4_with_zsub2_in_ZPR_4b |
| 36605 | 51, // 30: FPR8_with_ZPR4_with_zsub3_in_ZPR_4b |
| 36606 | 64, // 31: ZPR |
| 36607 | }; |
| 36608 | return PressureLimitTable[Idx]; |
| 36609 | } |
| 36610 | |
| 36611 | /// Table of pressure sets per register class or unit. |
| 36612 | static const int RCSetsTable[] = { |
| 36613 | /* 0 */ 2, 4, -1, |
| 36614 | /* 3 */ 0, 18, -1, |
| 36615 | /* 6 */ 1, 3, 6, 18, -1, |
| 36616 | /* 11 */ 21, 26, 27, 31, -1, |
| 36617 | /* 16 */ 26, 28, 31, -1, |
| 36618 | /* 20 */ 21, 26, 27, 28, 31, -1, |
| 36619 | /* 26 */ 26, 29, 31, -1, |
| 36620 | /* 30 */ 26, 28, 29, 31, -1, |
| 36621 | /* 35 */ 21, 26, 27, 28, 29, 31, -1, |
| 36622 | /* 42 */ 20, 26, 30, 31, -1, |
| 36623 | /* 47 */ 7, 19, 20, 25, 26, 30, 31, -1, |
| 36624 | /* 55 */ 20, 26, 29, 30, 31, -1, |
| 36625 | /* 61 */ 7, 14, 17, 20, 24, 26, 29, 30, 31, -1, |
| 36626 | /* 71 */ 7, 14, 17, 19, 20, 24, 25, 26, 29, 30, 31, -1, |
| 36627 | /* 83 */ 20, 26, 28, 29, 30, 31, -1, |
| 36628 | /* 90 */ 7, 11, 13, 15, 20, 23, 26, 28, 29, 30, 31, -1, |
| 36629 | /* 102 */ 7, 11, 13, 14, 15, 17, 20, 23, 24, 26, 28, 29, 30, 31, -1, |
| 36630 | /* 117 */ 7, 11, 13, 14, 15, 17, 19, 20, 23, 24, 25, 26, 28, 29, 30, 31, -1, |
| 36631 | /* 134 */ 16, 22, 23, 24, 25, 27, 28, 29, 30, 31, -1, |
| 36632 | /* 145 */ 20, 21, 26, 27, 28, 29, 30, 31, -1, |
| 36633 | /* 154 */ 7, 8, 9, 10, 12, 20, 21, 22, 26, 27, 28, 29, 30, 31, -1, |
| 36634 | /* 169 */ 7, 8, 9, 10, 11, 12, 13, 15, 20, 21, 22, 23, 26, 27, 28, 29, 30, 31, -1, |
| 36635 | /* 188 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, -1, |
| 36636 | /* 210 */ 5, 12, 13, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36637 | /* 229 */ 5, 7, 12, 13, 14, 16, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36638 | /* 249 */ 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36639 | /* 273 */ 5, 10, 11, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36640 | /* 292 */ 5, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36641 | /* 314 */ 5, 7, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36642 | /* 337 */ 5, 8, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36643 | /* 356 */ 5, 9, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36644 | /* 375 */ 5, 8, 9, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36645 | /* 395 */ 5, 9, 10, 11, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36646 | /* 416 */ 5, 8, 9, 10, 11, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36647 | /* 438 */ 5, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36648 | /* 462 */ 5, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36649 | /* 487 */ 5, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36650 | /* 512 */ 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, -1, |
| 36651 | }; |
| 36652 | |
| 36653 | /// Get the dimensions of register pressure impacted by this register class. |
| 36654 | /// Returns a -1 terminated array of pressure set IDs |
| 36655 | const int *AArch64GenRegisterInfo:: |
| 36656 | getRegClassPressureSets(const TargetRegisterClass *RC) const { |
| 36657 | static const uint16_t RCSetStartTable[] = { |
| 36658 | 134,134,487,1,0,4,134,4,4,4,487,8,2,3,4,4,8,4,134,4,4,4,4,4,8,8,487,4,4,4,4,4,4,4,4,8,4,4,4,8,8,8,8,8,4,4,4,4,8,8,8,8,8,8,8,8,8,8,8,4,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,6,3,7,7,7,8,7,134,416,438,4,487,4,4,4,8,8,8,8,8,6,134,14,487,145,249,134,375,395,292,416,438,487,134,337,356,273,210,375,395,292,416,438,487,134,14,416,438,35,83,487,145,188,117,249,134,14,375,395,292,20,30,55,416,438,35,83,487,145,169,102,71,188,117,249,134,14,337,356,273,210,11,16,26,42,375,395,292,20,30,55,416,438,35,83,487,145,154,90,61,47,169,102,71,188,117,249,}; |
| 36659 | return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
| 36660 | } |
| 36661 | |
| 36662 | /// Get the dimensions of register pressure impacted by this register unit. |
| 36663 | /// Returns a -1 terminated array of pressure set IDs |
| 36664 | const int *AArch64GenRegisterInfo:: |
| 36665 | getRegUnitPressureSets(unsigned RegUnit) const { |
| 36666 | assert(RegUnit < 116 && "invalid register unit" ); |
| 36667 | static const uint16_t RUSetStartTable[] = { |
| 36668 | 2,4,4,2,3,2,4,512,512,512,512,512,512,512,512,512,512,512,487,487,487,487,487,416,375,337,134,134,134,134,134,134,134,134,134,134,229,314,462,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,8,8,8,8,8,8,8,8,8,8,7,7,7,7,7,7,6,6,7,7,7,7,7,7,8,8,4,4,4,249,249,249,249,249,249,249,249,188,169,154,145,145,145,145,145,35,20,11,14,14,14,14,14,14,14,14,14,14,47,71,117,}; |
| 36669 | return &RCSetsTable[RUSetStartTable[RegUnit]]; |
| 36670 | } |
| 36671 | |
| 36672 | extern const MCRegisterDesc AArch64RegDesc[]; |
| 36673 | extern const MCPhysReg AArch64RegDiffLists[]; |
| 36674 | extern const LaneBitmask AArch64LaneMaskLists[]; |
| 36675 | extern const char AArch64RegStrings[]; |
| 36676 | extern const char AArch64RegClassStrings[]; |
| 36677 | extern const MCPhysReg AArch64RegUnitRoots[][2]; |
| 36678 | extern const uint16_t AArch64SubRegIdxLists[]; |
| 36679 | extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[]; |
| 36680 | extern const uint16_t AArch64RegEncodingTable[]; |
| 36681 | // AArch64 Dwarf<->LLVM register mappings. |
| 36682 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[]; |
| 36683 | extern const unsigned AArch64DwarfFlavour0Dwarf2LSize; |
| 36684 | |
| 36685 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[]; |
| 36686 | extern const unsigned AArch64EHFlavour0Dwarf2LSize; |
| 36687 | |
| 36688 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[]; |
| 36689 | extern const unsigned AArch64DwarfFlavour0L2DwarfSize; |
| 36690 | |
| 36691 | extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[]; |
| 36692 | extern const unsigned AArch64EHFlavour0L2DwarfSize; |
| 36693 | |
| 36694 | AArch64GenRegisterInfo:: |
| 36695 | AArch64GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
| 36696 | unsigned PC, unsigned HwMode) |
| 36697 | : TargetRegisterInfo(AArch64RegInfoDesc, RegisterClasses, RegisterClasses+186, |
| 36698 | SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
| 36699 | LaneBitmask(0xFFFFFFFFFFFFFFB6), RegClassInfos, HwMode) { |
| 36700 | InitMCRegisterInfo(AArch64RegDesc, 642, RA, PC, |
| 36701 | AArch64MCRegisterClasses, 186, |
| 36702 | AArch64RegUnitRoots, |
| 36703 | 116, |
| 36704 | AArch64RegDiffLists, |
| 36705 | AArch64LaneMaskLists, |
| 36706 | AArch64RegStrings, |
| 36707 | AArch64RegClassStrings, |
| 36708 | AArch64SubRegIdxLists, |
| 36709 | 123, |
| 36710 | AArch64SubRegIdxRanges, |
| 36711 | AArch64RegEncodingTable); |
| 36712 | |
| 36713 | switch (DwarfFlavour) { |
| 36714 | default: |
| 36715 | llvm_unreachable("Unknown DWARF flavour" ); |
| 36716 | case 0: |
| 36717 | mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false); |
| 36718 | break; |
| 36719 | } |
| 36720 | switch (EHFlavour) { |
| 36721 | default: |
| 36722 | llvm_unreachable("Unknown DWARF flavour" ); |
| 36723 | case 0: |
| 36724 | mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true); |
| 36725 | break; |
| 36726 | } |
| 36727 | switch (DwarfFlavour) { |
| 36728 | default: |
| 36729 | llvm_unreachable("Unknown DWARF flavour" ); |
| 36730 | case 0: |
| 36731 | mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false); |
| 36732 | break; |
| 36733 | } |
| 36734 | switch (EHFlavour) { |
| 36735 | default: |
| 36736 | llvm_unreachable("Unknown DWARF flavour" ); |
| 36737 | case 0: |
| 36738 | mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true); |
| 36739 | break; |
| 36740 | } |
| 36741 | } |
| 36742 | |
| 36743 | static const MCPhysReg CSR_AArch64_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 }; |
| 36744 | static const uint32_t CSR_AArch64_AAPCS_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36745 | static const MCPhysReg CSR_AArch64_AAPCS_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X18, 0 }; |
| 36746 | static const uint32_t CSR_AArch64_AAPCS_SCS_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01fff000, 0x003ff800, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xe00bf003, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36747 | static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 }; |
| 36748 | static const uint32_t CSR_AArch64_AAPCS_SwiftError_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ff6000, 0x003fb000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0x800bc000, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36749 | static const MCPhysReg CSR_AArch64_AAPCS_SwiftError_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X18, 0 }; |
| 36750 | static const uint32_t CSR_AArch64_AAPCS_SwiftError_SCS_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ff7000, 0x003fb800, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xa00bd000, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36751 | static const MCPhysReg CSR_AArch64_AAPCS_ThisReturn_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, 0 }; |
| 36752 | static const uint32_t CSR_AArch64_AAPCS_ThisReturn_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x040003fc, 0x03ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36753 | static const MCPhysReg CSR_AArch64_AAPCS_X18_SaveList[] = { AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 }; |
| 36754 | static const uint32_t CSR_AArch64_AAPCS_X18_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01fff000, 0x003ff800, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xe00bf003, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36755 | static const MCPhysReg CSR_AArch64_AAVPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, 0 }; |
| 36756 | static const uint32_t CSR_AArch64_AAVPCS_RegMask[] = { 0xfffc000c, 0xfffc0003, 0xfffc0003, 0x00000003, 0x0003fffc, 0x0003fffc, 0x01ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc0001fff, 0xc00007ff, 0xc0000fff, 0xc0001fff, 0xc00007ff, 0x00400fff, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36757 | static const MCPhysReg CSR_AArch64_AAVPCS_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::X18, 0 }; |
| 36758 | static const uint32_t CSR_AArch64_AAVPCS_SCS_RegMask[] = { 0xfffc000c, 0xfffc0003, 0xfffc0003, 0x00000003, 0x0003fffc, 0x0003fffc, 0x01fff000, 0x003ff800, 0x00000000, 0xc0000000, 0xc0001fff, 0xc00007ff, 0xc0000fff, 0xc0001fff, 0xc00007ff, 0x00400fff, 0xe00bf003, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36759 | static const MCPhysReg CSR_AArch64_AllRegs_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 }; |
| 36760 | static const uint32_t CSR_AArch64_AllRegs_RegMask[] = { 0xfffffcac, 0xffffffff, 0xffffffff, 0xfc0003ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x003fffff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xfffbfffb, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36761 | static const MCPhysReg CSR_AArch64_AllRegs_SCS_SaveList[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 }; |
| 36762 | static const uint32_t CSR_AArch64_AllRegs_SCS_RegMask[] = { 0xfffffcac, 0xffffffff, 0xffffffff, 0xfc0003ff, 0xffffffff, 0xffffffff, 0xffffffff, 0x003fffff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xfffbfffb, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36763 | static const MCPhysReg CSR_AArch64_NoRegs_SaveList[] = { 0 }; |
| 36764 | static const uint32_t CSR_AArch64_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| 36765 | static const MCPhysReg CSR_AArch64_NoRegs_SCS_SaveList[] = { AArch64::X18, 0 }; |
| 36766 | static const uint32_t CSR_AArch64_NoRegs_SCS_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001000, 0x00000800, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| 36767 | static const MCPhysReg CSR_AArch64_RT_MostRegs_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, 0 }; |
| 36768 | static const uint32_t CSR_AArch64_RT_MostRegs_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ffe3f8, 0x003ff1fc, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xce0be702, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36769 | static const MCPhysReg CSR_AArch64_RT_MostRegs_SCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, 0 }; |
| 36770 | static const uint32_t CSR_AArch64_RT_MostRegs_SCS_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01fff3f8, 0x003ff9fc, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xee0bf703, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36771 | static const MCPhysReg CSR_AArch64_SVE_AAPCS_SaveList[] = { AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, 0 }; |
| 36772 | static const uint32_t CSR_AArch64_SVE_AAPCS_RegMask[] = { 0xfffc000c, 0xfffc0003, 0xfffc0003, 0x03ffc003, 0x0003fffc, 0x0003fffc, 0x01ffe000, 0xc03ff000, 0xc0003fff, 0xc0003fff, 0xc0001fff, 0xc00007ff, 0xc0000fff, 0xc0001fff, 0xc00007ff, 0x00400fff, 0xc00be002, 0x01fffc03, 0x007ffc00, 0x00fffc00, 0x00000000, }; |
| 36773 | static const MCPhysReg CSR_AArch64_SVE_AAPCS_SCS_SaveList[] = { AArch64::Z8, AArch64::Z9, AArch64::Z10, AArch64::Z11, AArch64::Z12, AArch64::Z13, AArch64::Z14, AArch64::Z15, AArch64::Z16, AArch64::Z17, AArch64::Z18, AArch64::Z19, AArch64::Z20, AArch64::Z21, AArch64::Z22, AArch64::Z23, AArch64::P4, AArch64::P5, AArch64::P6, AArch64::P7, AArch64::P8, AArch64::P9, AArch64::P10, AArch64::P11, AArch64::P12, AArch64::P13, AArch64::P14, AArch64::P15, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::LR, AArch64::FP, AArch64::X18, 0 }; |
| 36774 | static const uint32_t CSR_AArch64_SVE_AAPCS_SCS_RegMask[] = { 0xfffc000c, 0xfffc0003, 0xfffc0003, 0x03ffc003, 0x0003fffc, 0x0003fffc, 0x01fff000, 0xc03ff800, 0xc0003fff, 0xc0003fff, 0xc0001fff, 0xc00007ff, 0xc0000fff, 0xc0001fff, 0xc00007ff, 0x00400fff, 0xe00bf003, 0x01fffc03, 0x007ffc00, 0x00fffc00, 0x00000000, }; |
| 36775 | static const MCPhysReg CSR_AArch64_StackProbe_Windows_SaveList[] = { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::SP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 }; |
| 36776 | static const uint32_t CSR_AArch64_StackProbe_Windows_RegMask[] = { 0xfffffca4, 0xffffffff, 0xffffffff, 0xfc0003ff, 0xffffffff, 0xffffffff, 0xfefff3ff, 0x003ff9ff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff, 0xeffbf7fb, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36777 | static const MCPhysReg CSR_AArch64_TLS_ELF_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 }; |
| 36778 | static const uint32_t CSR_AArch64_TLS_ELF_RegMask[] = { 0xfffffc04, 0xffffffff, 0xffffffff, 0xfc0003ff, 0xffffffff, 0xfbffffff, 0xfcffffff, 0x003fffff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xff7fffff, 0xffebfff3, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36779 | static const MCPhysReg CSR_Darwin_AArch64_AAPCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 }; |
| 36780 | static const uint32_t CSR_Darwin_AArch64_AAPCS_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36781 | static const MCPhysReg CSR_Darwin_AArch64_AAPCS_SwiftError_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 }; |
| 36782 | static const uint32_t CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ff6000, 0x003fb000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0x800bc000, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36783 | static const MCPhysReg CSR_Darwin_AArch64_AAPCS_ThisReturn_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, 0 }; |
| 36784 | static const uint32_t CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x040003fc, 0x03ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36785 | static const MCPhysReg CSR_Darwin_AArch64_AAVPCS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, 0 }; |
| 36786 | static const uint32_t CSR_Darwin_AArch64_AAVPCS_RegMask[] = { 0xfffc000c, 0xfffc0003, 0xfffc0003, 0x00000003, 0x0003fffc, 0x0003fffc, 0x01ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc0001fff, 0xc00007ff, 0xc0000fff, 0xc0001fff, 0xc00007ff, 0x00400fff, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36787 | static const MCPhysReg CSR_Darwin_AArch64_CXX_TLS_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 }; |
| 36788 | static const uint32_t CSR_Darwin_AArch64_CXX_TLS_RegMask[] = { 0xfffffc0c, 0xffffffff, 0xffffffff, 0x000003ff, 0xfc000000, 0xfbffffff, 0xfdffe1ff, 0x003ff0ff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0x003fffff, 0x00000000, 0x00000000, 0x07400000, 0xc7ebe3f2, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36789 | static const MCPhysReg CSR_Darwin_AArch64_CXX_TLS_PE_SaveList[] = { AArch64::LR, AArch64::FP, 0 }; |
| 36790 | static const uint32_t CSR_Darwin_AArch64_CXX_TLS_PE_RegMask[] = { 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01800000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| 36791 | static const MCPhysReg CSR_Darwin_AArch64_CXX_TLS_ViaCopy_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 0 }; |
| 36792 | static const uint32_t CSR_Darwin_AArch64_CXX_TLS_ViaCopy_RegMask[] = { 0xfffffc00, 0xffffffff, 0xffffffff, 0x000003ff, 0xfc000000, 0xfbffffff, 0xfc7fe1ff, 0x003ff0ff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0x003fffff, 0x00000000, 0x00000000, 0x07000000, 0xc7e1e3f2, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36793 | static const MCPhysReg CSR_Darwin_AArch64_RT_MostRegs_SaveList[] = { AArch64::LR, AArch64::FP, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, 0 }; |
| 36794 | static const uint32_t CSR_Darwin_AArch64_RT_MostRegs_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ffe3f8, 0x003ff1fc, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xce0be702, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36795 | static const MCPhysReg CSR_Darwin_AArch64_TLS_SaveList[] = { AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 0 }; |
| 36796 | static const uint32_t CSR_Darwin_AArch64_TLS_RegMask[] = { 0xfffffc04, 0xffffffff, 0xffffffff, 0xfc0003ff, 0xffffffff, 0xfbffffff, 0xfcfff3ff, 0x003ff9ff, 0x00000000, 0xffc00000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0f7fffff, 0xefebf7f3, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36797 | static const MCPhysReg CSR_Win_AArch64_AAPCS_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, 0 }; |
| 36798 | static const uint32_t CSR_Win_AArch64_AAPCS_RegMask[] = { 0x03fc000c, 0x03fc0000, 0x03fc0000, 0x00000000, 0x00000000, 0x000003fc, 0x01ffe000, 0x003ff000, 0x00000000, 0xc0000000, 0xc000001f, 0xc0000007, 0x0000000f, 0x00000000, 0x00000000, 0x00400000, 0xc00be002, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36799 | static const MCPhysReg CSR_Win_AArch64_CFGuard_Check_SaveList[] = { AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, 0 }; |
| 36800 | static const uint32_t CSR_Win_AArch64_CFGuard_Check_RegMask[] = { 0x03fffc0c, 0x03fffc00, 0x03fffc00, 0xfc000000, 0xfc000003, 0xfc0003ff, 0xffffe007, 0x003ff003, 0x00000000, 0xffc00000, 0xffc0001f, 0xffc00007, 0x1fc0000f, 0x07c00000, 0x0fc00000, 0x00c00000, 0xc0fbe07a, 0x00000003, 0x00000000, 0x00000000, 0x00000000, }; |
| 36801 | |
| 36802 | |
| 36803 | ArrayRef<const uint32_t *> AArch64GenRegisterInfo::getRegMasks() const { |
| 36804 | static const uint32_t *const Masks[] = { |
| 36805 | CSR_AArch64_AAPCS_RegMask, |
| 36806 | CSR_AArch64_AAPCS_SCS_RegMask, |
| 36807 | CSR_AArch64_AAPCS_SwiftError_RegMask, |
| 36808 | CSR_AArch64_AAPCS_SwiftError_SCS_RegMask, |
| 36809 | CSR_AArch64_AAPCS_ThisReturn_RegMask, |
| 36810 | CSR_AArch64_AAPCS_X18_RegMask, |
| 36811 | CSR_AArch64_AAVPCS_RegMask, |
| 36812 | CSR_AArch64_AAVPCS_SCS_RegMask, |
| 36813 | CSR_AArch64_AllRegs_RegMask, |
| 36814 | CSR_AArch64_AllRegs_SCS_RegMask, |
| 36815 | CSR_AArch64_NoRegs_RegMask, |
| 36816 | CSR_AArch64_NoRegs_SCS_RegMask, |
| 36817 | CSR_AArch64_RT_MostRegs_RegMask, |
| 36818 | CSR_AArch64_RT_MostRegs_SCS_RegMask, |
| 36819 | CSR_AArch64_SVE_AAPCS_RegMask, |
| 36820 | CSR_AArch64_SVE_AAPCS_SCS_RegMask, |
| 36821 | CSR_AArch64_StackProbe_Windows_RegMask, |
| 36822 | CSR_AArch64_TLS_ELF_RegMask, |
| 36823 | CSR_Darwin_AArch64_AAPCS_RegMask, |
| 36824 | CSR_Darwin_AArch64_AAPCS_SwiftError_RegMask, |
| 36825 | CSR_Darwin_AArch64_AAPCS_ThisReturn_RegMask, |
| 36826 | CSR_Darwin_AArch64_AAVPCS_RegMask, |
| 36827 | CSR_Darwin_AArch64_CXX_TLS_RegMask, |
| 36828 | CSR_Darwin_AArch64_CXX_TLS_PE_RegMask, |
| 36829 | CSR_Darwin_AArch64_CXX_TLS_ViaCopy_RegMask, |
| 36830 | CSR_Darwin_AArch64_RT_MostRegs_RegMask, |
| 36831 | CSR_Darwin_AArch64_TLS_RegMask, |
| 36832 | CSR_Win_AArch64_AAPCS_RegMask, |
| 36833 | CSR_Win_AArch64_CFGuard_Check_RegMask, |
| 36834 | }; |
| 36835 | return makeArrayRef(Masks); |
| 36836 | } |
| 36837 | |
| 36838 | ArrayRef<const char *> AArch64GenRegisterInfo::getRegMaskNames() const { |
| 36839 | static const char *const Names[] = { |
| 36840 | "CSR_AArch64_AAPCS" , |
| 36841 | "CSR_AArch64_AAPCS_SCS" , |
| 36842 | "CSR_AArch64_AAPCS_SwiftError" , |
| 36843 | "CSR_AArch64_AAPCS_SwiftError_SCS" , |
| 36844 | "CSR_AArch64_AAPCS_ThisReturn" , |
| 36845 | "CSR_AArch64_AAPCS_X18" , |
| 36846 | "CSR_AArch64_AAVPCS" , |
| 36847 | "CSR_AArch64_AAVPCS_SCS" , |
| 36848 | "CSR_AArch64_AllRegs" , |
| 36849 | "CSR_AArch64_AllRegs_SCS" , |
| 36850 | "CSR_AArch64_NoRegs" , |
| 36851 | "CSR_AArch64_NoRegs_SCS" , |
| 36852 | "CSR_AArch64_RT_MostRegs" , |
| 36853 | "CSR_AArch64_RT_MostRegs_SCS" , |
| 36854 | "CSR_AArch64_SVE_AAPCS" , |
| 36855 | "CSR_AArch64_SVE_AAPCS_SCS" , |
| 36856 | "CSR_AArch64_StackProbe_Windows" , |
| 36857 | "CSR_AArch64_TLS_ELF" , |
| 36858 | "CSR_Darwin_AArch64_AAPCS" , |
| 36859 | "CSR_Darwin_AArch64_AAPCS_SwiftError" , |
| 36860 | "CSR_Darwin_AArch64_AAPCS_ThisReturn" , |
| 36861 | "CSR_Darwin_AArch64_AAVPCS" , |
| 36862 | "CSR_Darwin_AArch64_CXX_TLS" , |
| 36863 | "CSR_Darwin_AArch64_CXX_TLS_PE" , |
| 36864 | "CSR_Darwin_AArch64_CXX_TLS_ViaCopy" , |
| 36865 | "CSR_Darwin_AArch64_RT_MostRegs" , |
| 36866 | "CSR_Darwin_AArch64_TLS" , |
| 36867 | "CSR_Win_AArch64_AAPCS" , |
| 36868 | "CSR_Win_AArch64_CFGuard_Check" , |
| 36869 | }; |
| 36870 | return makeArrayRef(Names); |
| 36871 | } |
| 36872 | |
| 36873 | const AArch64FrameLowering * |
| 36874 | AArch64GenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
| 36875 | return static_cast<const AArch64FrameLowering *>( |
| 36876 | MF.getSubtarget().getFrameLowering()); |
| 36877 | } |
| 36878 | |
| 36879 | } // end namespace llvm |
| 36880 | |
| 36881 | #endif // GET_REGINFO_TARGET_DESC |
| 36882 | |
| 36883 | |